Simple Processor Unit V1



Simple Processor Unit V5.4

Programmer visible registers.

PC = PC(15..0), SP = SP(15..0), A = A(7..0), F = F(7..0) = CY|Z|S|…

M = M(0..FFFFH) = M(0..FFFFH; 7..0), IO = IO(0..FFH) = IO(0..FFH; 7..0)

The instruction set

|Opcode |Operands |RTF |Flags |

|INC |A |A ( A + 1, PC ( PC + 1 |Z,S |

|DEC |A |A ( A - 1, PC ( PC + 1 |Z,S |

|NOT |A |[pic], PC ( PC + 1 |Z,S |

|NEG |A |A ( -A, PC ( PC + 1 |Z,CY,S |

|CLR |A |A ( 0, PC ( PC + 1 |Z,CY,S |

|SLL |A |CY|A ( A|0, PC ( PC + 1 |Z,CY,S |

|SRL |A |A|CY ( 0|A, PC ( PC + 1 |Z,CY,S |

|LDI |A, data |A ( M(PC+1), PC ( PC + 2 |- |

|ADDI |A, data |A ( A + M(PC + 1), PC ( PC + 2 |Z,CY,S |

|ADDCI |A, data |A ( A + M(PC + 1) + CY, PC ( PC + 2 |Z,CY,S |

|SUBI |A, data |A ( A - M(PC + 1), PC ( PC + 2 |Z,CY,S |

|CMPI |A, data |Flags set based on A - M(PC + 1), PC ( PC + 2 |Z,CY,S |

|ANDI |A, data |A ( A ( M(PC + 1), PC ( PC + 2 |Z,CY,S |

|ORI |A, data |A ( A ( M(PC + 1), PC ( PC + 2 |Z,CY,S |

|ADD |A, addr |A ( A + M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|ADDC |A, addr |A ( A + M[M(PC+2)|M(PC+1)] + CY, PC ( PC + 3 |Z,CY,S |

|SUB |A, addr |A ( A – M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|CMP |A, addr |Flags based on A – M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|AND |A, addr |A ( A ( M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|OR |A, addr |A ( A ( M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|LD |A, addr |A ( M[M(PC+2)|M(PC+1)], PC ( PC + 3 |- |

|ST |addr, A |M[M(PC+2)|M(PC+1)] ( A, PC ( PC + 3 |- |

|JMP |addr |PC ( M(PC+2)|M(PC+1) |- |

|JZ |addr |If Z=1 then PC ( M(PC+2)|M(PC+1) else PC ( PC+3 |- |

|JNZ |addr |If Z=0 then PC ( M(PC+2)|M(PC+1) else PC ( PC+3 |- |

|JC |addr |If C=1 then PC ( M(PC+2)|M(PC+1) else PC ( PC+3 |- |

|JNC |addr |If C=0 then PC ( M(PC+2)|M(PC+1) else PC ( PC+3 |- |

|CLR |addr |M[M(PC+2)|M(PC+1)] ( 0, PC ( PC + 3 |Z,CY,S |

|INC |addr |M[M(PC+2)|M(PC+1)] ( M[M(PC+2)|M(PC+1)] + 1 |Z,S |

|DEC |addr |M[M(PC+2)|M(PC+1)] ( M[M(PC+2)|M(PC+1)] + 1 |Z,S |

|LWI |SP, addr |SP ( M(PC+2)|M(PC+1), PC ( PC + 3 |- |

|PUSH |A |M(SP-1) ( A, SP ( SP – 1, PC ( PC + 1 |- |

|POP |A |A ( M(SP), SP ( SP + 1, PC ( PC + 1 |- |

|CALL |addr |PC ( M(PC+2)|M(PC+1), M(SP-2)|M(SP-1) ( PC + 3 |- |

| | |SP ( SP - 2 | |

|RET | |PC ( M(SP)|M(SP+1), SP ( SP + 2 |- |

|IN |A, port |A ( IO[M(PC+1)], PC ( PC + 2 | |

|OUT |port, A |IO[M(PC+1)] ( A, PC ( PC + 2 | |

|XORI |A, data |A ( A ( M(PC + 1), PC ( PC + 2 |Z,CY,S |

|XOR |A, addr |A ( A ( M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

|SWAP |A, addr |A ( M[M(PC+2)|M(PC+1)], PC ( PC + 3 |Z,CY,S |

Example programs.

Transfer byte on input port 80H to output port FFH,

START: IN A,80H ; Read byte on input port 80H

OUT 0FFH,A ;Output byte to port FFH

JMP START

Convert the 4 least significant bit on input port 80H, convert to an ASCII character, and output the ASCII to port FFH.

START: LWI SP, 8000H ; Initialize SP

LOOP: CALL GET ; Get hex value

CALL ASCII ; Convert to ASCII

CALL PUT ; Output ASCII value

JMP LOOP ; Do it forever

GET: IN A, 80H ; Read port

AND A, 0FH ; Save only low nibble

RET

PUT: OUT 0FFH,A ; Output ASCII value

RET

ASCII:

; Do this as homework problem #2 see class web page.

RET

Example 2: Compute S = [pic] put result in A.

COUNT: BYTE 1 ; Reserve one byte for count

SUM: LDI A, 100 ; Get final count

ST COUNT, A ; Put in count.

CLR A ; Clear SUM

LOOP: ADD A, COUNT ; Add count to sum

DEC COUNT ; Decrement count

JNZ LOOP ; Continue till done

DONE: … ; Sum is in A

Sum 16 bit word X and 16 bit word Y put result in Z.

X: WORD 1 ; Reserve one word for A

Y: WORD 1 ; Reserve one word for B

Z: WORD 1 ; Reserve one word for C

SUN16: LD A, LOW X ; Get low byte of X

ADD A, LOW Y ; Add low byte of X

ST LOW Z, A ; Save in low byte of Z

LD A, HIGH X ; Get High byte of X

ADDC A, HIGH Y ; Add Y and carry form low byte

ST HIGH, Z ; Save result

Microinstructions V1.1

Internal registers not visible to the programmer: IR = IR(7..0), T = T(7..0), S = S(7..0)

MAR = MARH|MARL = MARH(7..0)|MARL(7..0)

The microinstructions listed below can execute on the same clock cycle provided there are no conflicts. For example:

PC ( PC + 1, A ( M(MAR), SP ( MAR, T ( M(MAR), MARH ( T

could all take place on the same clock cycle. However, the following examples cause conflicts and could occur on the same clock cycle.

• A ( M(MAR), IR ( M(PC) ; Can’t read memory using two different addresses.

• A ( M(MAR), M(MAR) ( A ; Can’t read and write memory at same time.

• MAR ( SP, MAR ( PC ; Can’t put two different values into MAR register.

|Memory |ALU |PC |SP |

|read |CY|A ( A + T |PC ( 0 |SP ( SP + 1 |

|IR ( M(PC) |CY|A ( A - T |PC ( PC + 1 |SP ( SP - 1 |

|A ( M(MAR) |CY|A ( A + T+CY |PC ( MAR |SP ( MAR |

|A ( M(SP) |A ( A ( T |PC ( PC |SP ( SP |

|MARL ( M(PC) |A ( A ( T | | |

|MARH ( M(PC) |A ( [pic] |IR ( IR |MAR ( SP |

|T ( M(PC) |A ( 0 | |MAR ( PC |

|T ( M(MAR) |CY|A ( A|0 | |MARL ( T |

|T ( M(SP) |A|CY ( 0|A |T ( MARL |MARH ( T |

|write |A ( A + 1 |T ( MARH |MARL ( MARL |

|M(MAR) ( A |A ( A - 1 |T ( A |MARH ( MARH |

|M(SP) ( A |A ( T |T ( T | |

|M(MAR) ( T |A ( A |S ( A |IO(MAR) ( T |

|M(SP) ( T |CY ( CY |A ( S |T ( IO(MAR) |

Note: If no specification is made for a register it will be assumed that the register maintains its value.

Control unit state diagram definitions:

Imm inst ( {LDI, ADDI, SUBI, ANDI. ORI}

addr inst ( {ADD, SUB, AND, OR, LD, ST, JMP, JZ, JNZ, JC, JNC, CALL}

AL inst ( {ADDI, SUBI, ANDI. ORI, ADD, SUB, AND, OR}

op = “+” if IR = ADD or ADDI[1]

op = “-” if IR = SUB or SUBI

op = “(” if IR = AND or ANDI

op = “(” if IR = OR or ORI

S0: Fetch

PC ( PC+1, IR ( M(PC)[2], GOTO S1;

S1: Decode

IF (IR = addr[3] inst) then

MARL ( M(PC), PC ( PC + 1

GOTO S2

IF (IR = Imm[4] inst) then

T ( M(PC), PC ( PC + 1

GOTO S4

IF (IR = CLR) then A ( 0 GOTO S0

IF (IR = NOT) then A ( [pic] GOTO S0

IF (IR = DEC) then A ( A - 1 GOTO S0

IF (IR = INC) then A ( A + 1 GOTO S0

IF (IR = SLL) then CY|A ( A|0 GOTO S0

IF (IR = SRL) then A|CY ( 0|A GOTO S0

S2:

MARH ( M(PC), PC ( PC + 1, GOTO S3

S3: where MAR = addr

IF (IR = AL[5] inst) or (IR = LD) then T ( M(MAR), GOTO S4

IF (IR = ST) then M(MAR)[6] ( A, GOTO S0

IF (IR = JMP) or [(IR = JZ) and Z] or [(IR = JNZ) and not Z]

or [(IR = JCY) and CY] or [(IR = JNC) and not CY]then

PC ( MAR, GOTO S0

IF [(IR = JNZ) and Z] or [(IR = JZ) and not Z]

or [(IR = JNC) and CY] or [(IR = JC) and not CY]then GOTO S0

S4: where T = data

IF (IR = LDI) or (IR = LD) then A ( T, GOTO S0

IF (AL inst) A ( A op T, GOTO S0

[pic]

[pic]

Non-Deterministic version.

S0: Fetch

PC ( PC+1, IR ( M(PC)[7], GOTO S1;

S1: Decode

IF (IR = addr[8] inst) then

MARL ( M(PC), PC ( PC + 1

GOTO S2

IF (IR = Imm[9] inst) then

T ( M(PC), PC ( PC + 1

GOTO S4 and S0

IF (IR = CLR) then A ( 0 GOTO S0

IF (IR = NOT) then A ( [pic] GOTO S0

IF (IR = DEC) then A ( A - 1 GOTO S0

IF (IR = INC) then A ( A + 1 GOTO S0

IF (IR = SLL) then CY|A ( A|0 GOTO S0

IF (IR = SRL) then A|CY ( 0|A GOTO S0

S2:

MARH ( M(PC), PC ( PC + 1, GOTO S3

S3: where MAR = addr

IF (IR = AL[10] inst) or (IR = LD) then T ( M(MAR), GOTO S4 and S0

IF (IR = ST) then M(MAR)[11] ( A, GOTO S0

IF (IR = JMP) or [(IR = JZ) and Z] or [(IR = JNZ) and not Z]

or [(IR = JCY) and CY] or [(IR = JNC) and not CY]then

PC ( MAR, GOTO S0

IF [(IR = JNZ) and Z] or [(IR = JZ) and not Z]

or [(IR = JNC) and CY] or [(IR = JC) and not CY]then GOTO S0

S4: where T = data

IF (IR = LDI) or (IR = LD) then A ( T, GOTO NULL

IF (AL inst) A ( A op T, GOTO NULL

[pic]

[pic]

Deterministic FSM control unit with PUSH, POP, RET, and CALL instructions. Check for errors!

S0: Fetch

PC ( PC+1, IR ( M(PC)[12], GOTO S1;

S1: Decode

IF (IR = PUSH) then

SP ( SP – 1

GOTO S5

IF (IR = POP) then

A ( M(SP), SP ( SP + 1

GOTO S0

IF (IR = RET) then

SP ( SP + 1, MAR ( SP

GOTO S6

IF (IR = addr[13] inst) then

MARL ( M(PC), PC ( PC + 1

GOTO S2

IF (IR = Imm[14] inst) then

T ( M(PC), PC ( PC + 1

GOTO S4

IF (IR = CLR) then A ( 0 GOTO S0

IF (IR = NOT) then A ( [pic] GOTO S0

IF (IR = DEC) then A ( A - 1 GOTO S0

IF (IR = INC) then A ( A + 1 GOTO S0

IF (IR = SLL) then CY|A ( A|0 GOTO S0

IF (IR = SRL) then A|CY ( 0|A GOTO S0

S2:

MARH ( M(PC), PC ( PC + 1, GOTO S3

S3: where MAR = addr

IF (IR = CALL) then

PC ( MAR, MAR ( PC, SP ( SP – 1, GOTO S10

IF (IR = AL[15] inst) then T ( M(MAR), GOTO S4

IF (IR = ST) then M(MAR)[16] ( A, GOTO S0

IF (IR = JMP) or [(IR = JZ) and Z] or [(IR = JNZ) and not Z]

or [(IR = JCY) and CY] or [(IR = JNC) and not CY]then

PC ( MAR, GOTO S0

IF [(IR = JNZ) and Z] or [(IR = JZ) and not Z]

or [(IR = JNC) and CY] or [(IR = JC) and not CY]then GOTO S0

S4: where T = data

IF (IR = LDI) or (IR = LD) then A ( T, GOTO S0

IF (AL inst) A ( A op T, GOTO S0

S5:

IF (IR = PUSH) then M(SP) ( A, GOTO S0

S6:

IF (IR = RET) then T ( M(MAR), MAR ( SP, GOTO S7

S7:

IF (IR = RET) then MARH ( T, T ( M(MAR), SP ( SP + 1, GOTO S8

S8:

IF (IR = RET) then MARL ( T, GOTO S9

S9:

IF (IR = RET) then PC ( MAR, GOTO S0

S10:

IF (IR = CALL) then T ( MARL, GOTO S11

S11:

IF (IR = CALL) then T ( MARH, M(SP) ( T, SP ( SP – 1, GOTO S12

S12:

IF (IR = CALL) then M(SP) ( T, GOTO S0

[pic]

-----------------------

[1] The IR register contains the opcode for an ADD or ADDI instructions.

[2] Memory read

[3] ADD, SUB, AND, OR, LD, ST, JMP, JZ, JNZ, JC, JNC, CALL

[4] LDI, ADDI, SUBI, ANDI., ORI

[5] ADDI, SUBI, ANDI. ORI, ADD, SUB, AND, OR

[6] Memory write.

[7] Memory read

[8] ADD, SUB, AND, OR, LD, ST, JMP, JZ, JNZ, JC, JNC, CALL

[9] LDI, ADDI, SUBI, ANDI., ORI

[10] ADDI, SUBI, ANDI. ORI, ADD, SUB, AND, OR

[11] Memory write.

[12] Memory read

[13] ADD, SUB, AND, OR, LD, ST, JMP, JZ, JNZ, JC, JNC, CALL

[14] LDI, ADDI, SUBI, ANDI., ORI

[15] ADDI, SUBI, ANDI. ORI, ADD, SUB, AND, OR

[16] Memory write.

................
................

In order to avoid copyright disputes, this page is only a partial summary.

Google Online Preview   Download