Name:____________________________
Name:____________________________
CMIS 310 – Spring 2013
HOMEWORK #4 – Week 4
This homework is worth 10% of your course grade and consists of ten problems worth a total of 105 points.
Problems 1 through 5 are worth fifteen points each.
Problems 6 through 10 are worth six points each.
Submit the completed homework via your Assignment folder in our Tycho classroom, hard copy through US Mail, or electronic mail. Mailed copies should be sent to:
Richard Daumit
5450 Whitley Park Terrace #512
Bethesda, MD 20814-2055
For problems 1 through 3, convert the decimal numbers into 8-bit binary numbers as required for 2's complement math, and perform the indicated operations. Circle or bold your binary answer and show your work.
Remember that positive numbers are represented in sign-magnitude format in 2's complement math
1.
+38
+30
=
The above addition is carried out in the following table. 1s in red color are carries.
| | |1 |1 |
|0 |0 |0 |A’B’C’ |
|0 |0 |1 | |
|0 |1 |0 | |
|0 |1 |1 |A’BC |
|1 |0 |0 |AB’C’ |
|1 |0 |1 |AB’C |
|1 |1 |0 | |
|1 |1 |1 |ABC |
5. Draw a simple NOT, AND, OR circuit in sum of products (SOP) form that represents the equation in problem 4.
We can make the following Karnaugh map for minimizing the function.
[pic]
We get Y = BC+AC+AB`+B`C`.
We can realize the function as given below.
[pic]
For problems 6 through 10, you are to identify the diagram (1 through 11) and/or circuit description (a through h), and/or truth table (A through H) that best describes the gate or circuit.
Gates should have three parts – figure, circuit description, and truth table.
Circuits will only require a figure number.
| | |Figure |Description |Truth table |
|6 |NAND gate |2 |d |H |
|7 |Multiplexer |7 | | |
|8 |XOR gate |6 |b |C |
|9 |ALU |11 | | |
|10 |OR gate |5 |c |D |
Figure Description Truth Table
6. NAND gate ________, _________, and _________
7. Multiplexer ________
8. XOR gate ________, __________, and _________
9. ALU _________
10. OR gate ________, __________, and _________
[pic] [pic]
Figure 1 Figure 2
[pic] [pic]
Figure 3 Figure 4
[pic] [pic]
Figure 5 Figure 6
Circuit descriptions:
a. The output is one if and only if all of the inputs are one.
b. The output is one if and only if one of the two inputs is one.
c. The output is one if any of the inputs are one.
d. The output is zero if and only if all of the inputs are one.
e. The output is zero if and only if one of the two inputs is one.
f. The output is zero if any of the inputs are one.
g. The output state is identical to that of the input state.
h. The output state is opposite to that of its input state.
Truth tables:
Table A: Table B: Table C: Table D:
Input |output | |Inputs |output | |inputs |output | |inputs |Output | |X |A | |X |Y |B | |X |Y |C | |X |Y |D | |0 |0 | |0 |0 |0 | |0 |0 |0 | |0 |0 |0 | |1 |1 | |0 |1 |0 | |0 |1 |1 | |0 |1 |1 | | | | |1 |0 |0 | |1 |0 |1 | |1 |0 |1 | | | | |1 |1 |1 | |1 |1 |0 | |1 |1 |1 | |
Table E: Table F: Table G: Table H:
Input |Output | |Inputs |Output | |Inputs |Output | |Inputs |Output | |X |E | |X |Y |F | |X |Y |G | |X |Y |H | |0 |1 | |0 |0 |1 | |0 |0 |1 | |0 |0 |1 | |1 |0 | |0 |1 |0 | |0 |1 |0 | |0 |1 |1 | | | | |1 |0 |0 | |1 |0 |0 | |1 |0 |1 | | | | |1 |1 |0 | |1 |1 |1 | |1 |1 |0 | |
[pic]
Figure 7
[pic]
Figure 8
[pic]
Figure 9
[pic]
Figure 10
[pic]
Figure 11
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