Silicon Imaging
Silicon Imaging
SI-3300 MegaCamera(
3.2 Million Pixel Progressive Scan Digital Camera
[pic]
Revision 1.0
July 8, 2004
[pic] 3.2 Million Pixels
[pic] 2048 x 1536 Image Sensor
[pic] 3.2 um Square Pixel
[pic] ½ Optical format
[pic] Rolling Shutter
[pic] Subsampling & Binning
[pic] 20~80Mhz Clock rates (-H version)
[pic] 10 Bit Digital Sampling
[pic] Auto Black Level Correction
[pic] 62.9dB Dynamic Range
[pic] CL High-Speed Interface
**** Company Confidential ****
|MegaCamera™ SI-3300M & RGB |Silicon Imaging Inc. |
|3.2 Megapixel, 10-Bit, 40/80MHz |[pic] |
|Progressive Scan Digital Camera | |
| | |
|INTRODUCTION | |
| |[pic] |
|Silicon Imaging is proud to continue its innovation in high-resolution color | |
|vision camera. Driven by the growing demand for consumer Digital Still Cameras, |[pic] |
|CMOS sensors are continuing to break technical barriers and surpass the | |
|performance characteristics of CCD’s in many photonic, imaging and consumer |FEATURES |
|applications. By utilizing a single highly integrated CMOS device, which | |
|incorporates Megapixel sensing areas, timing generation, Analog-to-digital |· 2048 x 1536 Resolution (3.2 Million Pixels) |
|Conversion and signal processing, Silicon Imaging has developed a very compact, |· 1/2” Imaging Format , 5.2um Square Pixel |
|low-power, ultra high speed Megapixel digital camera system. |· Rolling Shutter, Progressive scan |
| |· 640 x 480 VGA Windowing at 120fps |
|2048 x 1536 Megapixel - Ultra Resolution |· 10 Bits per Pixel, 48MHz Sampling (Nominal) |
|The SI-3300 is an all-digital ½” format CMOS camera that delivers 3.2 Million |· 20 ~ 80MHz Programmable Clock (– H Version) |
|pixels of resolution and is capable of running at over 12 frames/second at its |· Programmable Gain, Exposure & Clocks |
|full 2048 x 1536 resolution. The entire package is only 45 x 52 x 50mm (33 x |· Auto Black Level Calibration |
|40mm x 22mm in PCB) and is small enough to placed on a robot for semiconductor |· Monochrome & Color Bayer RGB Model |
|machine vision inspection or placed in an outdoor housing for remote |· Custom PCB Version |
|surveillance. It is ideal for live visualization and handheld instrumentation. |· Cameralink Interface |
| |· C-Mount Precision Machined Housing |
|10-Bits Sampling – Sub-Pixel Accuracy | |
|The SI-3300 MegaCamera( uses 10-Bit digitizers to sample the pixel data. | |
|Converting the pixel data directly to digital at the sensor head eliminates | |
|pixel-sampling jitter and enables accurate sub-pixel metrology, image analysis | |
|and improved live video reconstruction. A programmable clock which ranges from | |
|20~40Mhz or up to 80MHz with -H version, allows for trade-offs in speed versus | |
|exposure time and lower noise. | |
| | |
|Subsampling with Binning – Video Preview | |
|Ideal for high speed preview and focusing, the SI-3300 is capable of generating | |
|imagery at over 30 frames per second by reducing the size of the readout image in| |
|color subsampling mode, This entire imager is readout by binning 4x4 groups of | |
|pixels into 2x2 bayer super pixels with increased sensitivity, less aliasing and | |
|faster readout rates. The camera also supports up to 3x binning and 8x | |
|subsampling. | |
| | |
|1000FPS Windowing and 720/1080P HD Modes | |
|A small region of the imager can be readout at frame rates in excess of 1000fps, | |
|with speed increasing with reduced vertical and horizontal settings. At 1920 x | |
|1080 and a 75MHz clock the output rate would be 30fps or 1280x720 at 73MHz will | |
|be 60fps. The window size and position can be adaptively changed on | |
|frame-by-frame basis. | |
| | |
|Automatic Black Level Correction | |
|The SI-3300 has automatic black level calibration, which measures the average | |
|value pixels from two dark rows of the imager for each of the four colors. The | |
|pixels are averaged as if they were light sensitive and passed through the | |
|appropriate color gain. This average is then digitally filtered over many frames | |
|and compared to minimum and maximum acceptable thresholds for automatic | |
|correction. | |
| | |
|CameraLink( Digital Interfaces (12-Bit 1-Tap) | |
|An industry standard forum has adopted Camera Link, for low cost connectivity and| |
|cabling of cameras and frame grabbers at very high speeds. The SI-3300-CL | |
|utilizes the high speed CameraLink interface to output data continuously to a | |
|frame grabber and directly into PC memory for further processing. The single | |
|cable includes image data, synch, Triggering and 9600 baud Serial communication. | |
|As this camera complies with the standard, it is compatible with many popular | |
|frame grabber and image processing hardware devices and GigaBit Ethernet or | |
|fiber-optic repeaters for extended distance transmission. | |
| |
|SI-3300 MegaCamera CameraLink Specifications |
| | |
|Sensor: |CameraLink Frame Grabber Control: |
|Optical Imaging Format |Serial Communication |
|1/2” (6.55mm x 4.91mm, 8.19mm diagonal) |RS-232 Protocol 9600bps (57.6k) |
| | |
|Active Pixels |Serial Signaling |
|2,048H x 1,536V |TX & RX (LVDS) |
| | |
|Pixel Size (pitch) |Triggers |
|3.2 µm x 3.2 µm |LVDS – CC1 (-CL) |
| |TTL Trigger-In / Strobe-Out (option) |
|Pixel Type | |
|CMOS |Region-of–Interest |
| |Programmable Horiz & Vertical |
|Aspect Ratio | |
|1 : 1 |Programmable Modes |
| |Exposure, Gain, Windowing, Clock Rates, Auto black, trigger. |
|Spectral Response | |
|350 ~ 1000 nm (Bayer Color Filtered) |Gains (R,G,B,G & Global) |
| |Individual RGBG Gains |
|Responsivity |Range: 18X, Min step size 0.125 |
|> 1.0 V/lux-sec (550nm) | |
| |Setting Timing |
|Temporal Noise |Next top of Frame |
|TBD | |
| |Ext Clock Sync |
|Saturation Charge |Clock in or Clock Out (-X Option) |
|TBD | |
| | |
|Dynamic range |Power |
|61dB |Input Voltage |
| |+5 VDC +/- 10% |
|SNR max | |
|43dB |Power |
| |2.5 Watts |
|Windowing (ROI) | |
|Horizontal & Vertical speed increase |Power/Trigger Connection |
| |Tajimi RO3-PB3M 3Pin (-CL) |
|Sub-sampling |Tajimi RO3-PB5M 5Pin (-X) |
|Full, 1/2, 1/3, 1/4, 1/8 | |
| | |
|Binning |Mechanical |
|2x (4x4 to 2x2 / 4:1) & 3x (6x6 to 2x2 / 9:1) |Lens Mount |
| |C-Mount, 7mm Back focus Adj. |
|Gain MAX | |
|8x Analog, 18x with Digital |Enclosure Size |
| |45mm W x 52mm H x 50mm L |
|Readout Method | |
|Progressive Scan |Weight |
| |12 oz. |
|Black Level | |
|Auto Black Level Calibration |Camera Mount |
| |¼” x 20 standard tripod mount |
|Shutter | |
|Rolling Shutter with Global Reset option |Cable Connector |
| |Cameralink MDR-26 |
|Shutter Speed / Integration | |
|Variable, approx. 50usec ~ 50sec | |
| | |
|Horizontal Blanking |Mechanical Dimensions |
|390 Clocks/line |[pic] |
| | |
|Minimum Row Time | |
|647 clocks (257 + 390 blanking) | |
| | |
|Vertical Blanking | |
|4 Rows | |
| | |
|Row/Frame Time (default) | |
|2438 clocks/row x 1540/rows @ 40MHz | |
| | |
| | |
| | |
|A/D Conversion & Sampling Clock Synthesizer | |
|A/D Conversion | |
|Nominal 40Mhz (12fps @ 3.2MP) | |
| | |
|Readout Rate | |
|20 ~ 80Mhz x 12bit format | |
| | |
|A/D Resolution | |
|10 Bit (CL Format = 12bit Single-Tap) | |
| | |
|Pixel Clock Frequency | |
|20 ~ 40 Mhz Programmable | |
|20 ~ 80Mhz (-H option) | |
| | |
| | |
| | |
|Digital Video Output | |
|Interface | |
|Cameralink Base, Single-tap, 12bit | |
| | |
|Readout Format | |
|CL - 12 Bit Base | |
|Duplicated data on Ports A, B | |
| | |
|Effective Data Rate | |
|20~ 80MB/sec (8-bit, using MSB) | |
|40~160MB/sec (12-bit Unpacked) | |
| | |
|Frame Rate | |
|2048 x 1536 | |
|1600 x 1200 | |
|1920 x 1080 | |
|1280 x 720 | |
|640 x 480 | |
|320 x 240 | |
|128 x 128 | |
|40MHz | |
|11 | |
|17 | |
|16 | |
|33 | |
|80 | |
|243 | |
|296 | |
|75MHz | |
|20 | |
|31 | |
|30 | |
|62 | |
|150 | |
|456 | |
|555 | |
| | |
|Row/Frame Time (default) | |
|1524 clocks/row x 1050/rows = 30fps | |
| | |
ORDERING INFORMATION
|SI-3300-[RGB or M]-S |3.2 MP Digital Camera, 2M Cable, PCI Frame Grabber & Win NT/2K/XP Imaging Software System | |
|SI-3300-[RGB or M]-CL |3.2 MP Digital Camera (RGB for Color, M for Monochrome) Cameralink (-CL) | |
| -X - H |High-Speed CL 80MHz (–H), Add external clock sync (-X) | |
|FG-1300-xx |Frame Grabber PCI (32 = 32Bit PCI -64 = 64bit PCI) | |
|CL-2M, 3M, 5M, 10M |2 / 3 / 5 / 10 Meter Digital Cameralink Cable | |
|PC-3 |Power Cable (3M) | |
|PCT-3 |Power supply & External TTL trigger (3M | |
|PS-5 |5VDC Power supply | |
SI-3300 Camera Architecture Overview
The MegaCamera( SI-3300 consists of 6 major component sections, which are built on two circuit boards.
Camera Block Diagram
[pic]
3.2 Megapixel Sensor
Digital Clock Synthesizer
Digital Control Logic
Microprocessor
CL Interface
Power Regulation
Trigger & Strobe Controls
3.2 Megapixel CMOS Image Sensor (2048 x 1536)
The MegaCamera( SI-3300 utilizes a proprietary 3.2 Million pixel high-speed CMOS image sensor. Each pixel is 5.2um Square, ideal for image processing, and the entire array fits the 1/2” format for flexible optic choices. This reduction in process geometry allows for both an increase in transistors and fill factor without compromising performance, plus offers more advanced readout controls, greater speeds and lower power dissipation.
This new sensor technology offers a more responsive pixel design with added circuitry for increased dynamic range, greater sensitivity, decreased fixed pattern noise and low dark current for long exposure applications. Unlike CCD, which leak charge to adjacent pixels when the registers overflows (blooms), the SI-3300 provides inherent anti-blooming protection in each pixel, so that there is no blooming.
The array has 2048 pixels on a line and 1536 rows, which result in a 4:3 aspect ratio. The sensor array design is based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme (aka. Rolling Shutter Method)
[pic]
Analog Gain Amplifier & Offset
The imager signal path consists of two stages, a programmable gain stage and a programmable analog offset stage. The gain settings can be independently adjusted for the colors Green1, Blue, Red, and Green2 and are programmed through registers. A total programmable gain of 18x is available. The programmable analog offset stage corrects for analog offset that might be present in the analog signal. The analog offset settings can be independently adjusted for each color (R/G1/G2/B).
Automatic Black Level Compensation
The automatic black level calibration measures the average value of 256 pixels from two dark rows of the imager for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered average is compared to minimum and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased. If it is above the maximum level, the level is decreased. The upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting (out of all four colors), according to Register settings. This prevents clipping of the black level. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers.
10-Bit Digital Sampling System
A 10-Bit Analog-to-digital (A/D) converter samples each pixel value and quantizes it into 1024 levels inside the sensor. Pixel clock sampling ensures precise measurement of the photonic charge without the jitter and sampling uncertainty associated with traditional analog video systems, such as RS-170 and CCIR. This produces images which can deliver improved photometry accuracy and sub-pixel metrology. The use of 10-bit converters versus traditional 8-bit systems further enhances the image dynamic range. The combination of 10-bit vertical resolution and pixel clock sampling provide precise sub-pixel measurement accuracy (ex. 1/10 pixel).
Digital Clock Synthesizer
A wide range a master clock frequencies (eg. 20 to 80MHz) can by precisely generated using the Digital Clock Synthesizer. The Frame Grabber, which is used with the camera, must be capable of receiving 12bit at 40Mhz for standard cameras or up to 80Mhz for the High-Speed (-H) model to achieve the highest data rates. Without any byte packing of the 12-bit word the data rate would be 160MHz (2pixel x 2bytes/pixel x 80MHz). In standard 32Bit/33MHz PCI computers the maximum data rate directly to host memory is usually below 120Mbytes/sec (from 132MB/sec bus) without system interrupts. However, 100MB/sec is more reasonable rate to achieve with other system devices operating (eg. display, clock, mouse etc.). Under these condition the 12-bit data can be mapped to 8-bits/pixel to reduce the bus traffic or the clock rate can be reduced to and still maintain 12bits/pixel. The frequency of the clock synthesizer can be set by serial command. A table with associated clock frequency is found in the serial programming section of the manual. Due to minimum frequency restriction on the digital transmission link, the pixel clock frequency cannot be lower than 20Mhz.
Embedded Microprocessor
A microprocessor in the camera provides the control interface between the PC and the functional block in the camera (Sensor, Clock Synthesizer, Register Memory, Channel Link Interface & Serial port (CameraLink). The Microprocessor receives commands thru the LVDS level serial port and issues commands to the other devices. It also can store preset values for camera setting, which can be recalled with single ASCII character commands. Several digital I/O or analog sampling signals are available on the processor from PCB header points for custom OEM applications.
12-Bit CameraLink Interface (Base Configuration)
Camera Link is a new digital transmission method designed by imaging component manufacturers as an easy and standard way to connect digital cameras to frame grabbers. The Camera Link specification includes greater than 1.2Gb/sec data transmission as well as camera control and asynchronous serial communications all on a single cable with high-density 26pin connector. Only two connections are required to quickly interface your digital camera to a multitude of frame grabbers. This standardization will ultimately reduce cost of high performance digital cameras through open market competition and a simple migration path to faster and higher resolution systems.
As a standard that has been defined by industry members, Camera Link provides the following benefits:
• Standard Interface: Every Camera Link product will use the same cable and signaling. Cameras and frame grabbers can easily be interchanged using the same cable.
• Simple Connection: Only two connections will be required to interface a camera and frame grabber: Power and Camera Link.
• Lower Cost: Because Camera Link is an industry-wide standard, consumers will be able to take advantage of lower cable prices.
• Smaller connectors & cables: The technology used in Camera Link reduces the number of wires required to transmit data over traditional LVDS or RS-422 parallel interfaces, allowing for smaller cables. Smaller cables are more robust and less prone to breakage.
• Higher data rates: The technology used in Camera Link has a maximum data rate of 2.3GB/s, for use in the most demanding high definition, high frame rate and line scan.
CameraLink Camera Signal
This section provides definitions for the signals used in the Camera Link interface. The standard Camera Link cable uses a MDR 26-pin connector (3M Part# 10226-6212VC)provides the following signaling:
• Video Data (4 Pairs using 28:4 Mux, 24 Video, 4 Control)
• Camera control signals (1 Pair)
• Serial communication (2 Pairs)
Video Data
The 24 bit image data (2 words x 12 bit) and 4 control bits are transmitted over only 4 differential pairs using a 28:4 multiplexer (National Semiconductor DS90CR285 Channel Link device). The Four enable signals are defined as:
• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.
• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.
• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.
• Spare— A spare has been defined for future use.
All four enables are provided on the camera, via the Channel Link chip. The unused data bits are tied to a known value by the camera. For more information on image data bit allocations, see page 11, CameraLink Base Configuration Bit Assignment Configuration.
Communication
Two LVDS pairs have been allocated for asynchronous serial communication to and from the camera and frame grabber. Cameras and frame grabbers should support at least 9600 baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface operates at 9600 baud, one start bit, one stop bit, no parity, and no handshaking. For applications requiring high serial throughput, such as real time windowing update at over 200FPS, the camera can support a serial link mode at 57kbs (not specified in CameraLink spec). The frame grabber serial communication must be set to match this speed.
Camera Control Signals & Power
Four LVDS pairs are reserved for general-purpose camera control. They are defined as camera inputs and frame grabber outputs. Camera manufacturers can define these signals to meet their needs for a particular product. The signals are:
• Camera Control 1 (CC1) - Used to do triggered image capture
• Camera Control 2 (CC2) for external master clock (optional)
[pic] [pic]
Tajimi RO3-PB3M – POWER CABLE
[pic]
5VDC Power Supplies
[pic][pic]
3-PIN POWER & TRIGGER INPUT WIRING
[pic]
PhotoEye Trigger and Power Connection
[pic]
Power-On Communication & Presets
Initial State
When the power is first applied to the camera the camera will load its default (Preset #0) settings and will be generating live video and a serial status message. Preset #1 can be overwritten thru programming commands. Once Preset#1 is overwritten it will be the new power-on default setting.
If the Frame Grabber supports a serial terminal mode the following menu will appear:
100: Booted
108: CameraLink SI3300 3.12.08
120:C2010610 Sensor tag
190:66633035 Configuration code
's' - status
Returns the firmware version, clock configuration word, Sensor Tag, and FPGA Configuration code. Camera output example:
108: CameraLink SI3300 3.06.08
110:306882 Clock
120:C2010610 Sensor tag
190:66633035 Configuration code
Default Settings
When first turned on, the SI-3300 will be in the default mode, which will be 10 fps Full Frame Readout at 40MHz master clock. See serial programming section for details on changing formats.
Full Resolution, Rolling Shutter, Single-slope, 40MHz
Resolution = 2048 x 1536
Clock = 40MHz
Integration = 1561 Rows
Global Gain = 2.0
Frame Rate = 11 FPS
Serial Communication & Protocol
The SI-3300 is capable of mode programming through its serial interface. Commands are sent from the CameraLink frame grabber to the camera. The commands are processed by the micro controller and communicated to various devices in the camera including the sensor, digital clock synthesizer and the Flash memory inside the microprocessor itself.
The communication uses an asynchronous serial format, similar to RS232, but is transferred to the camera using LVDS as part of the CameraLink interface specification.
Format: Asynchronous, ASCII
Rate: 9600
Data Bits: 8 + 2 Stop bits
Parity: No Parity
Interface: Serial LVDS (thru CameraLink)
The baud rate is set to 9600 and 8 data bits with no parity. This is the format set by the CameraLink standard. However, faster rates can be set by the factory and coordination with the Frame Grabber supplier.
Serial Commands
There are two types of commands Single character and Register String (multiple characters followed by Carriage Return). Once the camera receives the string ending with a it will respond. For each command, there is a corresponding action and response from the camera.
Single Character commands
|“s” |Camera status including firmware version, clock configuration word, sensor tag and CPLD configuration codes. |
|“f” |Arm single frame capture. Trigger frame capture & readout if already armed. |
|“c” |Continuous Live Rolling Shutter Operation. Return tpo ERS after arming with an ‘f’ |
|“g” |Enter Genlock Mode. Use “c” to return to continuous (supported by -H model) |
|“h” |Change to high-speed serial mode for operation at 57.6kbaud |
*** Note: All commands must terminate with a (carriage return).
Register String commands
Each command may be entered through the Terminal communication mode from the frame grabber software. All ASCII characters sent should be lower case and no spaces between characters. The string is terminated with a carriage return . Hex numbers are sent as ASCII characters: 0Fh is sent as “0F” character. There are no spaces between characters being sent in strings. These are multiple character string commands with a common format.
Register String Commands
|Command |Description |Parameters |Response |
|lc xxxxxx |Load Clock Register |xxxxxx = 6 hex values from table |114: Clock updated |
| |(See clock table) | | |
|ly rr xxx |Load Sensor Registers |rr = register number 00~ff |104: Sensor updated |
| |Loads registers 00 to ff with 16bit values, |xxx = x0000~xFFFF | |
| |which are sent as 4 ascii characters | | |
| |representing hex. | | |
|le x |Load EEPROM preset value ***overwrites factory|x = 1 |106: Preset updated |
| |values |le1 = stores preset #1 | |
|ld x |Load Bootup Default |x = 0 or 1 | |
| | |ld1 = boots camera with preset #1 | |
|'luAA[YYXXx16]' |Load upper/user memory |AA = slot (00 ~FF | |
| |7k-Bytes. Configured in 256 slots. Each slot |YY = Memory (00-10) | |
| |has 16 memory locations of14bits for |XX = 14 bit value (00~ F | |
| | |The first two bits (MSBs) of the first byte and of| |
| | |every odd byte are not stored. | |
|lr xxxx |Read back user/upper memory | | |
|ln xxxx |Load new firmware |xxxx = password to enable firmware upgrade | |
| | |(contact factory) | |
*** Note: All commands must terminate with a (carriage return). Hex characters are lower case, no spaces.
Load Sensor Command Format
The following registers for SI-3300 control the sensor readout, timing and signal output levels. These are programmed thorough ‘ly’ register commands. The register number is represented by 2 characters. All sensor registers are 16 bits in length and are represented by 4 characters. The ASCII command format is:
ly rr xxxx rr = register number xxxx = values 0000 to ffff
The ly stands for load sensor array and must be sent as lower case. The “rr” is the register to be changed. The “xxxx”, “represents four HEX values that are to be loaded into each register. The sequence must end with a carriage return .
The following is an example of a 10-character command string
l y 0 1 0 0 6 4
This command will load the WIDTH register “01” with hex “0064”. The resulting value loaded into the Width register is “0064” or 101 in decimal. The actual resulting width in the image is width-, which equals 100.
SI-3300 Sensor Register Programming
|Register |Name |Default |Description |
|0x00 |Chip Version |0x1601 or 11 |Chip ID Response |
|0x01 |Row Start |0x0014 |First row to be read out + 20. (Bits 10~0) |
| | |(20) |Note: Register value must be an even number. |
|0x02 |Column Start |0x0020 |First column to be read out + 32. (Bits 11~0) |
| | |(32) |Note: Register value must be an even number. If column bin is enabled, the value |
| | | |must be a multiple of Reg0x23 [5-4] + 1. |
|0x03 |Height |0x05FF |Number of rows – 1. Min = 0x0001. (Bits 10~0) |
| | |(1535) |Note: Register value must be an odd number. |
|0x04 |Width |0x07FF |Number of columns – 1. Min = 0x0001. (Bits 10~0) |
| | |(2047) |Note: Register value must be an odd number. |
|0x05 |Horizontal Blanking |0x0015 |Number of extra blanking clocks in row. Min = x0015 (21). (Bits 10~0) |
| | |(21) |Horizontal Blanking = 390 clocks + (Regx05 - 21) |
|0x06 |Vertical Blanking |0x0003 |Number of rows + 1 in vertical blanking. Min = x0003 (3). (Bits 10~0) |
| | |(3) |Typically used to slow down frame rate and allow time for register updates between|
| | | |images. |
|0x08 |Long Exposure |0x000 |The MSB of Exposure Reg0x09. (Bits 15~0) |
| | |(0) |Long Exposure = (Reg8 x 65536) + Reg9 |
|0x09 |Exposure Time |0x0619 |Number of rows of integration (exposure time). Min = x0001 (Bits 15~0) |
| | |(1561) |Exposure = Row_Time x Reg0x09. Row_Time = Width + 390 + Reg0x05 |
| | | |Min_Row_Time = 647 clocks (even if width Reg05 is set smaller) |
|0x0C |Shutter Delay |0x0000 |Number of master clocks times four that the sensor waits before asserting the |
| |(Short Exposure) |(0) |reset for a given row. Used for Sub-row exposure times |
|0x1E |Snapshot |0x8040 |Snapshot Mode—default is 0 (continuous mode).1 = enable snaphsot. |
| |Mode | |This register bit is automatically controlled by ‘f’ command. |
| | | |Strobe Enable = 1 |
| | | |Strobe Width: 0 = one row, 1 = all rows of integration |
| | | |1=Strobe Override, set high, 0 for low |
|0x21 |Global Reset or ERS Readout Mode |0x0000 |Set to x0003 for Global Reset Snaphsot mode - Release all pixels from reset |
| | |(0) |simultaneously (use with flash & mechanical shutter. x000: for ERS. |
| | | |Note: global reset requires model SI3300–T with external trigger cable. |
|0x22 |Row Subsampling |0x0000 | |
| |Skip & Bin |(0) |Subsampling |
| | | |Skip only |
| | | |Reg 22 & 23 |
| | | |Skip + Bin |
| | | |Reg 22 & 23 |
| | | | |
| | | |None |
| | | |x0000 |
| | | |x0000 |
| | | | |
| | | |2x |
| | | |x0001 |
| | | |x0011 |
| | | | |
| | | |3x |
| | | |x0002 |
| | | |x0022 |
| | | | |
| | | |4x |
| | | |x0003 |
| | | |x0023 |
| | | | |
| | | |8x |
| | | |x0007 |
| | | |x0027 |
| | | | |
| | | |Load register x22 and x23 to get subsampling in both rows & columns. |
|0x23 |Column Subsampling |0x0000 | |
| |Skip & Bin |(0) | |
|0x2B |Green1 Gain |0x0008 (8) | Gain Increments Settings |
| | |1x gain. |1.000 to 4.000 0.125 0x0008 to 0x0020 |
| | | |4.25 to 8.00 0.25 0x0051 to 0x0060 |
| | | |9.0 to 18.0 1.0 0x0160 to 0x7860 |
| | | | |
| | | |Bits 6~0 : Analog Gain = (Bit[6] + 1) x Bit[5-0] x 0.125) |
| | | |Bits 14~8: Digital Gain = 1 + Bit[14-8] / 8 |
| | | |Total Gain = Analog x Digital Gain |
|0x2C |Blue Gain |0x0008 (8) | |
| | |1x gain. | |
|0x2D |Red Gain |0x0008 (8) | |
| | |1x gain. | |
|0x2E |Green2 Gain |0x0008 (8) | |
| | |1x gain. | |
|0x35 |Global Gain |0x0008 (8) |This register can be used to set all four gains at once. When read, it will return|
| | |1x gain. |the value stored in Reg0x2B. |
|0x49 |Black Level Target |0x00A8 |Target Black Level (Bits 15~0). Digital offset will be applied such that the |
| | | |average black level of a frame in a resulting image equals the value of this |
| | | |register. This adjustment happens after black level calibration. |
|0x62 |Auto Black Level Control |X0000 |0 0= Auto Black Calc, 1= Use Manual Black Levels (x60, x61, x63, x64) |
| | | |1 0 = Enable Correction, 1 = Disable Correction Voltage |
|0x60, 0x61 |Manual Black Offsets | 0x0020 |Two's compliment representation of analog offset correction value. |
|0x63, 0x64 |Green1, Green2, Red, Blue | |Bit[8] =1 causes the analog offset correction to be negative. Bit[7-0] = value |
| | | |Green1 (x60), Green2 (x61), Red (x63), Blue (x64) |
|0x5D |Auto Black |0x2D13 |6-0 Low Coarse Threshold. Max =less than High Target Threshold. |
| |Coarse Thresholds | | |
| | | |14-8 High Coarse Threshold. Min = greater than Low Target Threshold. |
| | | |If the average black value for a color is higher than this value or lower than Low|
| | | |Coarse Threshold, the coarse mode will be activated (if enabled). |
| | | |Once the black level is in range the fine method will be used. |
| 0x5F |Auto Black |0x231D |6-0 Thresh_lo: default = 29 Lower threshold for black level in ADC LSBs |
| |Fine Thresholds | | |
| | | |14-8 Thresh_hi: default = 35. Upper threshold for black level in ADC LSB. When |
| | | |the black value is within these thresholds, it is considered on target. |
Digital Clock Synthesizer Programming
The SI-3300 has a Digital Clock Synthesizer capable of generating a range of frequencies from 20MHz to 40 or up 80Mhz with –H version. The pixel data output rate is the same as the sampling clock rate. The clock frequency is set by the “lc” Register String command. A range of sample frequencies are listed below:
|Command |Clock Rate |SI-3300 Frame Rate |
| |MHz | |
|0x03 |Height |0x05FF |Number of rows – 1. Min = 0x0001. (Bits 10~0) |
| | |(1535) |Note: Register value must be an odd number. |
|0x04 |Width |0x07FF |Number of columns – 1. Min = 0x0001. (Bits 10~0) |
| | |(2047) |Note: Register value must be an odd number. |
|0x05 |Horizontal Blanking |0x008E |Number of extra blanking clocks in row. Min = x0015(21). (Bits 10~0) |
| | |(142) |Horizontal Blanking = 390 clocks + (Regx05 - 21) |
|0x06 |Vertical Blanking |0x0019 |Number of rows + 1 in vertical blanking. Min = x0003 (3). (Bits 10~0) |
| | |(25) |Typically used to slow down frame rate and allow time for register updates between images. |
|Frame Timing |
|[pic] |
|[pic] |
Note: Typically, the value of Expsoure (Reg0x09) is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as needed, and thereby reduce the effective frame rates.
Exposure Time (Regx08, x09, x0c)
The exposure time is set by adjusting the number of row times in the exposure register (Reg09) and up to the number of rows in the frame. For long exposures, Reg08 will count in increments of 65536 rows. The user can also program sub-row integration time for fine exposure control using Regx0C.
|Register |Name |Default |Description |
|0x09 |Exposure Rows |0x0619 |Number of rows of integration (exposure time). Min = x0001 (Bits 15~0) |
| | |(1561) |Exposure = Row_Time x Reg0x09. Row_Time = Width + 390 + Reg0x05 |
| | | |Min_Row_Time = 647 clocks |
|0x08 |Long Exposure |0x000 |The MSB of Exposure Reg0x09. (Bits 15~0) |
| | |(0) |Long Exposure = (Reg8 x 65536) + Reg9 |
|0x0C |Shutter Delay |0x0000 |Number of master clocks times four that the sensor waits before asserting the reset |
| |(Short Exposure) |(0) |for a given row. Used for Sub-row exposure times |
The exposure is estimated by:
Row_Time = [Width + 390 ] * Clock_Rate
Exposure_Time = Exposure_Rows (Reg09) * Row_Time
Reg04 sets the image width. The minimum blanking period is 390 clocks and can be extended by setting Reg05. The exposure is set in number of row times. The minimum # of columns that are internally clocked is 257, even if the image width is smaller. Therefore, the minimum row time = 257 + 390 = 647 clocks.
Typically, the value of Reg0x09 (Exposure Rows) is limited to the number of rows per frame (which includes vertical blanking rows) such that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the camera will automatically increase vertical blanking (Reg05) as needed, and thereby reduce the effective frame rates.
Example: What is the row_time and exposure time at 48MHz clock rate for an image size of 2048 width and no additional horizontal blanking?
Row_Time = 2048 + 390 / 48MHz
Exposure_Time = 2438 * 20.8 nsec = 59.4 usec/row
1/ 60 sec = 280 rows * 59.4 usec/row = 16.7 msec (Reg09 = x0118)
1/ 120 sec = 140 rows * 59.4 usec/row = 8.3 msec (Reg09 = x008c)
1/ 240 sec = 70 rows * 59.4 usec/row = 4.1 msec (Reg09 = x0046)
The following table shows a sample set of values for Reg9 and the exposure time at clock rates 20MHz and 40MHz:
|Width |Row_count |Row_Time@ 20MHz(50ns)|Row_Time@ |Reg09 |Exposure Time |Exposure Time |
| |(Width+390) | |40MHz(25ns) |(Exposure Rows) |20MHz |40MHz |
|2048 |2438 |122 us |61 usec |x0089 (137) |16.7ms 1/60 |8.3ms 1/120 |
|2048 |2438 |122 us |61 usec |x00a4 (164) |20 ms 1/50 |10.0ms 1/100 |
|2048 |2438 |122 us |61 usec |x0112 (274) |33 ms 1/30 |16.7ms 1/60 |
|2048 |2438 |122 us |61 usec |x0224 (548) |66 ms 1/15 |33.0ms 1/30 |
|2048 |2438 |122 us |61 usec |x066c (1644)* |200ms 1/5 |100 ms 1/10 |
|2048 |2438 |122 us |61 usec |X2004 (8196)* |1 sec |0.5 sec |
* Note: These high row exposure counts will extend the frame time, slowing down the effective max frame rate. At a 1 second exposure, the maximum frame rate is 1 frame/sec. For even longer exposure, use Reg08.
The full formula for calculating the pixel integration time is:
T_INT = ((65536 x Reg0x08 + Reg0x09) * Row_Clocks - P1 + 132 - Reg0x0C) * Clock_rate
Row_Clocks = Width + P1 +P2 +P3
P1 = Frame Start Blanking #1 (Row Binning)
331 if Reg0x22[5-4] = 0, normal
673 if Reg0x22[5-4] = 1, Bin 2x
999. if Reg0x22[5-4] = 2, Bin 3x
P2 = Frame Start Blanking #2 (Column Binning)
38 if Reg0x23[5-4] = 0, normal
22 if Reg0x23[5-4] = 1, Bin 2x
14 if Reg0x23[5-4] = 2, Bin 3x
P3 = Horizontal_Blanking set by Reg0x05 (min value = 21)
Note: P1 + P2 + P3 = 331 + 38 + 21 = 390 for min values and no binning
Flickerless Operation
While the user can adjust the integration time to the desired value according to the aforementioned formula, not all integration times may be desired under certain lighting conditions. If the light source has a flicker component, then the integration time needs to be set properly to avoid banding in the image. Under 60Hz flicker, the integration time must be a multiple of 1/120 of a second to avoid flicker. Under 50Hz flicker, the integration time must be a multiple of 1/100 of a second to avoid flicker.
Short Exposure ( Less than 1 Row Time)
To set the SI-3300 to an integration time less than 1 row, the shutter width register 0x09 must first be set to 1. Shorter integration times are controlled by the Shutter Delay register 0x0C.
T_INT = (Reg0x09 * Row_Clocks) - P1 + 132 - Reg0x0C * Clock_rate
For an image width of 2048, no binning, Reg9 set to 1, the sub-row short exposure time is calculated as follows:
T_INT = (1 * Row_Clocks) – P1 + 132 - Reg0C
Row_Clocks = width + P1 +P2 +P3
= Width + 390
P1 = 331 (673 = Bin2x, 999, Bin 3x)
Reg0C = 21 (minimum value)
T_INT = Row_Clocks – 331 + 132 – Reg0x0C * clock_rate
= (Width + 390) – 199 – Reg0x0C * clock_rate
= Width + 191 – Reg0x0C * clock_rate
|Width |Row_cntr |Reg09 |Reg0C |Exposure Clocks |Exposure_Time |Exposure_Time |
|(Reg4 + 1) |(Width + 191) |(1 Row) |(short exposure) |Row_Cntr - Reg0c |20MHz (50ns) |40MHz (25ns) |
|2048 |2239 |x0001 |x085b (2139) |100 |5.0 usec |2.5 usec |
|2048 |2239 |x0001 |x07f7 (2039) |200 |10 usec |5.0 usec |
|2048 |2239 |x0001 |x06cb (1739) |500 |25 usec |12.5 usec |
|2048 |2239 |x0001 |x04d7 (1239) |1000 |50 usec |25 usec |
Window Programming – Image Size & Position
|Register |Name |Default |Description |
|0x01 |Row Start |0x0014 |First row to be read out + 20. (Bits 10~0) |
| | |(20) |Note: Register value must be an even number. |
|0x02 |Column Start |0x0020 |First column to be read out + 32. (Bits 11~0) |
| | |(32) |Note: Register value must be an even number. If column bin is enabled, the value|
| | | |must be a multiple of Reg0x23 [5-4] + 1. |
|0x03 |Height |0x05FF |Number of rows – 1. Min = 0x0001. (Bits 10~0) |
| | |(1535) |Note: Register value must be an odd number. |
|0x04 |Width |0x07FF |Number of columns – 1. Min = 0x0001. (Bits 10~0) |
| | |(2047) |Note: Register value must be an odd number. |
The minimum value for Reg0x03 is 0x0001; for Reg0x04, 0x0001. Thus, the smallest window size is two columns by two rows (2H x 2V). The value of Reg0x03 and Reg0x04 must be an odd number (there can only be even number of columns).
The user can program the window size to be any format desired. To place a 1280 x 1024 window at a start position of 640, 480, use the following commands:
ly 04 xxxx Set WIDTH to (1280 - 1) = 1279 (0x04ff)
ly 03 xxxx Set HEIGHT to (1024 -1) = 1023 (0x03ff)
ly 02 xxxx Set COLUMN_START to 640+32=672 (0x02a0)
ly 01 xxxx Set ROW_START to 480+20=500 (0x01f4)
As shown in the adjacent picture, Registers 4 and 3 set the size of the display window. Register 2 sets the column start location and registers 1 set the row start location.
Note: Other custom commands can be used to move the window at high speeds – please consult the factory.
The following table shows examples of register settings to achieve various resolutions and frame rates based on a nominal 48MHz clock rate.
[pic]
[pic]
For tables above, the settings for Reg0x05 (horizontal blanking) and Reg0x06 (vertical blanking) are 21 and
15 respectively, while all of the registers are set to default.
Subsampling Skip & Bin Modes
Row and column skip modes use subsampling to reduce the output resolution without reducing field-of- view. The SI-3300 also has row and column binning modes, which can reduce the impact of aliasing introduced by the use of skip modes. This is achieved by the averaging of two or three adjacent rows and columns (adjacent same-color pixels). Both 2x and 3x binning modes are supported. Rows and columns can be binned independently.
| | |Row Skip |Column Skip |Row Skip + Bin |Column Skip + Bin |
|Skip/Bin |Resolution |ly22 00xx |ly23 00xx |ly22 00xx |ly23 00xx |
|None |2048 x 1536 |00 |00 |00 |00 |
|2x |1024 x 768 |01 |01 |11 |11 |
|3x |682 x 512 |02 |02 |22 |22 |
|4x |512 x 384 |03 |03 |23 |23 |
|8x |256 x 192 |07 |07 |27 |27 |
The following table shows examples of register settings to achieve various resolutions and frame rates based on a nominal 48MHz clock rate, such as 1920x1440 with a 3x bin & skip to achieve a 640x480 output at 48fps:
[pic]
Bin 2-to-1: 2,048H x 1,536V (QXGA) to 1,024H x 768V (XGA)
[pic]
NOTE:
Grs = binning of 4 Gr[s] in a 4 x 4 window; Gbs = binning of 4 Gb[s] in a 4 x 4 window.
Rs = binning of 4 R[s] in a 4 x 4 window; Bs = binning of 4 B[s] in a 4 x 4 window.
Bin 3-to-1: 2,048H x 1,536V (QXGA) to 640H x 480V (VGA)
[pic]
NOTE:
Grs = binning of 9 Gr[s] in a 6 x 6 window; Gbs = binning of 9 Gb[s] in a 6 x 6 window.
Rs = binning of 9 R[s] in a 6 x 6 window; Bs = binning of 9 B[s] in a 6 x 6 window.
Column Skip 2x; Row Skip 2x Enabled
[pic]
Column Skip 3x; Row Skip 3x Enabled
[pic]
Column Skip 4x; Row Skip 4x Enabled
[pic]
Column Skip 8x; Row Skip 8x Enabled
[pic]
GAIN CONTROL (Registers: 2B, 2C, 2D, 2E, 35)
The SI-3300 contains manual Analog and Digital gain controls for each color channel (G1, G2, R, B). Analog Gain values may be set using the following registers: G1 = 0x2B [6..0], G2 = 0x2E [6..0], R = 0x2D [6..0], and B = 0x2C [6..0]. In addition, the SI3300 contains a global gain register, 0x35 [6..0], that applies the gain value to all gain channels (G1, G2, R ,B ). Digital Gains are set using Bits{14~8] of each of the registers. The total gain = analog gain x digital gain. When the global gain register (Reg35) is read, it returns only the gain setting from the Green 1 channel register 0x2B.
|0x2B |Green1 Gain |0x0008 (8) | |
| | |1x gain. | |
| | | |Gain Increments Settings : |
| | | |1.000 to 4.000 0.125 0x0008 to 0x0020 |
| | | |4.25 to 8.00 0.25 0x0051 to 0x0060 |
| | | |9.0 to 18.0 1.0 0x0160 to 0x7860 |
| | | | |
| | | |Bits 6~0 : Analog Gain = (Bit[6] + 1) x Bit[5-0] x 0.125) |
| | | |Bits 14~8: Digital Gain = 1 + Bit[14-8] / 8 |
| | | |Total Gain = Analog x Digital Gain |
|0x2C |Blue Gain |0x0008 (8) | |
| | |1x gain. | |
|0x2D |Red Gain |0x0008 (8) 1x gain.| |
|0x2E |Green2 Gain |0x0008 (8) 1x gain.| |
|0x35 |Global Gain |0x0008 (8) |This register can be used to set all four gains at once. When read, it will return |
| | |1x gain. |the value stored in Reg0x2B. |
[pic]
The table below shows recommended gain register settings and corresponding gain values:
|Register Setting (0x2B, 0x2C, 0x2D, | | |Register Setting (0x2B, 0x2C, | |
|0x2E, 0x35) |Gain | |0x2D, 0x2E, 0x35) |Gain |
|Decimal |Hex |Gain |Gain [dB] |
|0x62 |Auto Black Level Control |X0000 |0 0= Auto Black Calc, 1= Use Manual Black Levels (x60, x61, x63, x64) |
| | | |1 0 = Enable Correction, 1 = Disable Correction Voltage |
|0x60, 0x61 |Manual Black Offsets | 0x0020 |Two's compliment representation of analog offset correction value. |
|0x63, 0x64 |Green1, Green2, Red, Blue | |Bit[8] =1 causes the analog offset correction to be negative. Bit[7-0] = value |
| | | |Green1 (x60), Green2 (x61), Red (x63), Blue (x64) |
|0x5D |Auto Black |0x2D13 |6-0 Low Coarse Threshold. Max =less than High Target Threshold. |
| |Coarse Thresholds | | |
| | | |14-8 High Coarse Threshold. Min = greater than Low Target Threshold. |
| | | |If the average black value for a color is higher than this value or lower than Low|
| | | |Coarse Threshold, the coarse mode will be activated (if enabled). |
| | | |Once the black level is in range the fine method will be used. |
| 0x5F |Auto Black |0x231D |6-0 Thresh_lo: default = 29 Lower threshold for black level in ADC LSBs |
| |Fine Thresholds | | |
| | | |14-8 Thresh_hi: default = 35. Upper threshold for black level in ADC LSB. When |
| | | |the black value is within these thresholds, it is considered on target. |
|0x49 |Black Level Target |0x00A8 |Target Black Level (Bits 15~0). Digital offset will be applied such that the |
| | | |average black level of a frame in a resulting image equals the value of this |
| | | |register. This adjustment happens after black level calibration. |
Auto Black Level Thresholds (Registers: 0x5D & 0x5F)
The digitized black level of the camera will potentially vary with temperature or gain setting changes. The SI-3300 allows the user the flexibility of automatic black level calibration or manual black level control. In automatic mode, the black level will be adjusted to be within the high and low thresholds set in Reg5D and 5F. The final black level digital output can be further adjusted by Reg49.
Auto Black Level Calibration (Registers: 0x62)
The automatic black level calibration measures the average value of 256 pixels from two dark rows of the imager for each of the four colors. The pixels are averaged as if they were light-sensitive and passed through the appropriate color gain. This average is then digitally filtered over many frames. For each color, the new filtered average is compared to minimum and a maximum acceptable level. If the average is lower than the minimum acceptable level, the offset correction voltage for that color is increased. If it is above the maximum level, the level is decreased. The upper threshold is automatically adjusted upwards whenever an upward shift in the black level from below the minimum results in a new black level above the maximum. This prevents black level oscillation from below the minimum to above the maximum. The lower threshold is increased with the maximum gain setting (out of all four colors), according to Register settings. This prevents clipping of the black level. After changes to the sensor configuration, large shifts in the black level calibration can result. To quickly adapt to this shift, a rapid sweep of the black level during the dark-row readout is performed on the first frame after certain changes to the sensor registers.
Manual Black Level (Registers: 0x60, 0x61,0x63 & 0x64)
The programmable analog offset stage corrects for analog offset that might be present in the analog signal. The user would need to program Reg0x62 to enable the manual analog offset correction. The analog offset settings can be independently adjusted for the colors of Green1, Green2, Red and Blue and are programmed through Reg0x60, Reg0x61, Reg0x63 and Reg0x64 respectively.
Bit[8] of Reg0x60, Reg0x61, Reg0x63 and Reg0x64 determines the sign of the analog offset(these registers have two’s complement representation). Bit[8] = 1 makes the analog correction negative instead of positive.
The lower 8 bits (Bit[7–0]) determine the absolute value of the analog offset to be corrected and Bit[8] determines the sign of the correction. When Bit[8] is “1”, the sign of the correction is negative and vice versa. The analog value of the correction relative to the analog gain stage can be determined from the following formula:
Analog offset = Bit[8–0] x 1 LSB
Note that the 1 LSB value in the formula is an estimate amount. It will deviate from 1 LSB with process variation.
Black Level Digital Control (Register: 0x49)
Digital offset will be applied such that the average black level of a frame in a resulting image equals the value of this register. This adjustment happens after black level calibration.
READOUT MODES
There are three operating modes for the SI-3300 cameras: Continuous, Frame Snapshot and Genlock modes. Each has its own characteristics shown below
|“c” |Continuous Electronic Rolling Shutter Operation. Return to ERS after an “f” or “g” |
|“f” |Arm single frame capture. Trigger frame capture & readout if already armed. |
| |In Frame snapshop there are 2 methods of Readout |
| |Rolling Shutter Readout - Reg21 = x0000 |
| |Global Reset Readout - Reg21 = x0003 (-T Model) |
|“g” |Enter Genlock Mode. Use “c” to return to continuous (supported by -H model) |
Continuous, Electronic Rolling Shutter (ERS) – “c” Mode
Continuous, rolling shutter mode is the default mode of operation of the camera. The exposure is determined by the delay between two scans of the pixel array and controlled with the shutter width registers, Reg0x08 and Reg0x09. The shutter width is measured in row times. The first scan (shutter) resets each row of pixels in turn, starting the exposure. The second scan (read) stops the exposure by transferring the accumulated charge from each row of pixels to sample/hold capacitors at the foot of the columns and reads the (digitized) values out. When each scan reaches the bottom of the array there follows a blanking period (controlled by the user) after which the scan automatically restarts at the top of the array. Read out is therefore continuous.
Frame Snapshot Mode, with ERS – “f” Mode with ERS
The snapshot mode allows capture of a single frame initiated by an external trigger using CC-1, TTL-Trigger (-T option) or software command (‘f )’, with the capability of controlling a flash using the Strobe_Out signal. Each of the rows in the shutter will be reset, as shown in Figure. Just as for continuous mode the exposure is determined by the delay between the scans. However, before the start of the frame, the sensor waits for a trigger before starting the scan. The first (shutter) scan does not start until a rising edge on the TRIGGER signal is seen. The second scan then follows after the shutter width delay. After the end of the frame, the sensor waits for another trigger before restarting the scan. The maximum snapshot rate is limited to half the continuous readout rate. Note that the exposure (shutter width) is still determined electronically.
[pic]
To return to Continuous ERS Readout mode, send a ‘c’ command.
Frame Snapshot Mode with Global Reset - “f” mode (with Reg21 = x0003) - T Model
|0x21 |Global Reset or ERS Readout Mode |0x0000 (ERS) |Set to x0003 for Global Reset Snaphsot mode - Release all pixels from reset |
| | |or |simultaneously (use with flash & mechanical shutter. x0000: for ERS. |
| | |0x0003 (GR) |Default Mode is conitunous ERS |
| | | |Note: Global reset requires model SI3300–T with external trigger cable. |
A further enhancement to the snapshot capability is a global reset mode that enables all pixels to start exposure to the scene simultaneously. Global reset mode is selected by Reg0x21 to x0003 (x0000 is Rolling Shutter).
Global reset mode has to operate with a mechanical shutter to terminate the exposure time or with a strobe with minimum ambient light. Using the global reset feature changes the behavior of the row reset controls. Instead of pulsing, the resets are held on. As the shutter pointer moves through the rows the resets are turned on one by one. When all of the rows have been reset, the exposure is started by releasing them all together. Exposure is terminated when an external mechanical shutter cuts off the light. Row read out is performed after the exposure is terminated. The strobe can be used to control flash and/or a mechanical shutter to end the exposure of the array prior to readout.
[pic]
To enter Snaphshot mode with global Reset:
ly210003 Global Reset Mode
f Frame Snapshot Mode
The snapshot is initiated with the CC-1 Trigger, TTL-Trigger (-T option) signal or “f’ frame request command, as in ERS snapshot mode. The array is reset row by row before the sensor waits for the trigger. All of the rows are held in reset until a rising edge is detected on the TRIGGER input, whereupon they are all released at once. At this point every row in the array starts to integrate at the same time. Integration is terminated and the readout started when the internal shutter counter is equal to the shutter width register ([Reg0x08, Reg0x09]). The first active row is read out after the preamble (5 rows), the calibration rows (18 rows) and the dark rows (24 rows), allowing 47 row times for the mechanical shutter to be closed. (Default values).
To return to Continuous ERS, set Reg21 to ERS Readout (x0000) and a “c’
ly210000 Rolling Shutter Mode
c Continuous Readout
Genlock Mode for Stereo Capture – ‘g’ command (-H Model)
For stereo and synchronized multi-camera applications the SI-3300-H models supports a Genlock feature.
In normal Frame Snapshot mode, an image can be captured for two cameras simultaneously by triggering the cameras at the same time. However, this method limits the maximum frame rate to half speed as the exposure and readout do not overlap and require two frame times per image captured. The first frame time is for Reset and begin exposure. The second frame time for Readout and completion of exposure. The Genlock mode provides the highest frame rate synchronization possible by allowing overlapping exposure and readout, just like continuous ERS, while being synchronized to a triggering timebase.
Sending a ‘g’ command arms the camera for Genlock Mode. Each CC-1 trigger causes the camera to initiate a frame readout. The camera is left in an armed state, continuing exposure and can be re-triggered at anytime. New CC-1 triggers can occur immediately after the completion of the current frame readout cycle. Note: The first frame is improperly exposed and should not be used.
The exposure time should be set to the full frame time for consistent exposures throughout the image. However, variable exposure times can be used if the Genlock trigger rate matches the normal Frame_Time set by image height and Vertical Blanking.
The mode is exited by sending a ‘c’ command.
Response Codes
|000:XXXX |Sensor Chip ID. This is sent at boot time, and also when the status command is issued. |
|0XX:XXXXXX... |Sensor registers. This message gives the address and contents of a chip register. 16 bytes of |
| |register data will be sent on each line. |
|100: Booted |This is the first string sent when the Camera boots. It will later be augmented with a firmware |
| |version number. |
|102: Default loaded |A message sent a boot time after the sensor and clock have been programmed. |
|104: Sensor updated |A response that follows the "ly..." command. |
|106: Preset updated |A response that follows the "le..." command. |
|108: CameraLink SI-3300 2.12.30 |Output by the ‘s’ status command. |
| |Identifies the camera model, interface and firmware version |
|110: XXXXXX Clock |Output by the ‘s’ status command. It gives the current clock setting. |
|114: Clock updated |A response that follows the "lc..." command. |
|120: XXXX Sensor Tag |Output by the ‘s’ status command. It provides the factory serial number. |
|152: serial to 57.6kbaud |Response to an ‘h’ command |
|159: serial rate fault |A serial framing error occurred in high-speed serial mode. Camera will return to default 9600 baud. |
|190: XXXX Configuration Code |Output by the ‘s’ status command. It gives the current configuration. |
|501: Unrecognized Command |The first character of the command line input is unrecognized. |
|503: Invalid Input |There are multiple forms of the 503 message code. They represent invalid input other then the command |
| |specifier, such as "ly..." commands which include to many characters of input, or not enough to fill |
| |the specified data byte count. |
|505: busy |Further input was given while the camera was still processing the previous input |
|601: Loaded preset #1 |A response to “1” command. Preset #1 was loaded. |
|605: help menu |All of the lines of the help menu begin with code 605. |
|702: Single frame |This message is sent after the camera enters single frame mode, and again after each frame is sent. |
|703: Leave single frame |This message is sent after the camera exits single frame mode and enters continuous frame mode. |
Binary to Hex (ASCII) Table
|Binary |Hex in ASCII |
|0000 |0 |
|0001 |1 |
|0010 |2 |
|0011 |3 |
|0100 |4 |
|0101 |5 |
|0110 |6 |
|0111 |7 |
|1000 |8 |
|1001 |9 |
|1010 |a |
|1011 |b |
|1100 |c |
|1101 |d |
|1110 |e |
|1111 |f |
SI-3300
CameraLink Frame Grabber
Hardware Interface Notes
1. Data Configuration – 12bits x Single-Tap
The 12bit data is duplicated on both A & B outputs, to simplify Frame Grabber testing and integration.
2. LVDS Serial Interface
The standard data rate is 9600 baud. (Faster rates, up to 57kbps can be programmed).
3. CC-1 Trigger Interface
The camera is armed for capture modes via serial command. The CC-1 trigger is used to start the snap exposure or live video output.
4. PCI Bandwidth
The camera can operate at 80 Million Pixels per second. In 8-bit mode, this equates to 80MB/sec a sustained data rate. In 12-bit mode, where 2 bytes per pixel are typically used, the maximum rate is 160MB/sec and may require the use of a 66MHz PCI system. The data rate can be adjusted thru the on-board clock synthesizer.
CameraLink Connection
MegaCamera to Frame Grabber Interface
[pic]
|SIGNAL NAME |PAIR |26-PIN CONNECTOR |26-PIN CONNECTOR |
| | |FROM |FRAME GRABBER |
| | |CAMERA | |
|X0- |1- |2 |25 |
|X0+ |1+ |15 |12 |
|X1- |2- |3 |24 |
|X1+ |2+ |16 |11 |
|X2- |3- |4 |23 |
|X2+ |3+ |17 |10 |
|X3- |5- |6 |21 |
|X3+ |5+ |19 |8 |
|Xclk- |4- |5 |22 |
|Xclk+ |4+ |18 |9 |
|SerTC- |6- |20 |7 |
|SertTC+ |6+ |7 |20 |
|SerTFG- |7- |8 |19 |
|SerTFG+ |7+ |21 |6 |
|CC1- |8- |9 |18 |
|CC1+ |8+ |22 |5 |
|CC2- |9- |23 |4 |
|CC2+ |9+ |10 |17 |
|CC3- |10- |11 |16 |
|CC3+ |10+ |24 |3 |
|CC4- |11- |25 |2 |
|CC4+ |11+ |12 |15 |
|Gnd |Gnd |1 |1 |
|Gnd |Gnd |13 |13 |
|Gnd |Gnd |14 |14 |
|Gnd |Gnd |26 |26 |
MDR-26 Connector
The camera uses the standard 3M MDR-26 connector specified in CameraLink specifications.
12-Bit CameraLink
Base Configuration Bit Assignment
| | |
| |National |
|CameraLink |DS90CR285MTD |
|Port Assignements |Signal |
| |Name |
| |Camera |
| |Data Bit |
|PORT/BIT |Channel Link |
|12-bit x 2Ch |Pin |
|Bit | |
|Name |RX-00 |
| |DO-00 |
|A0 |27 |
|A0 | |
|DO-0 |RX-01 |
| |DO-01 |
|A1 |29 |
|A1 | |
|DO-1 |RX-02 |
| |DO-02 |
|A2 |30 |
|A2 | |
|DO-2 |RX-03 |
| |DO-03 |
|A3 |32 |
|A3 | |
|DO-3 |RX-04 |
| |DO-04 |
|A4 |33 |
|A4 | |
|DO-4 |RX-05 |
| |DO-07 |
|A5 |34 |
|A5 | |
|DO-5 |RX-06 |
| |DO-05 |
|A6 |35 |
|A6 | |
|DO-6 |RX-07 |
| |DO-08 |
|A7 |37 |
|A7 | |
|DO-7 |RX-08 |
| |DO-09 |
|B0 |38 |
|A8 | |
|DO-8 |RX-09 |
| |DO-10 |
|B1 |39 |
|A9 | |
|DO-9 |RX-10 |
| |DE-10 |
|B2 |41 |
|A10 | |
|DO-10 |RX-11 |
| |DE-11 |
|B3 |42 |
|A11 | |
|DO-11 |RX-12 |
| |D-11 |
|B4 |43 |
|B8 | |
|DE-8 |RX-13 |
| |DE-08 |
|B5 |45 |
|B9 | |
|DE-9 |RX-14 |
| |DE-09 |
|B6 |46 |
|B10 | |
|DE-10 |RX-15 |
| |DE-00 |
|B7 |47 |
|B11 | |
|DE-11 |RX-16 |
| |DE-06 |
|C0 |49 |
|B0 | |
|DE-0 |RX-17 |
| |DE-07 |
|C1 |50 |
|B1 | |
|DE-1 |RX-18 |
| |DE-01 |
|C2 |51 |
|B2 | |
|DE-2 |RX-19 |
| |DE-02 |
|C3 |53 |
|B3 | |
|DE-3 |RX-20 |
| |DE-03 |
|C4 |54 |
|B4 | |
|DE-4 |RX-21 |
| |DE-04 |
|C5 |55 |
|B5 | |
|DE-5 |RX-22 |
| |DE-05 |
|C6 |1 |
|B6 | |
|DE-6 |RX-23 |
| |SPARE |
|C7 |2 |
|B7 | |
|DE-7 |RX-24 |
| |LVAL |
| |3 |
|DE = Even Pixels DO = Odd Pixels | |
|The ODD and EVEN Outputs |RX-25 |
|are identical on the SI-3300. |FVAL |
| |5 |
| | |
| |RX-26 |
| |DVAL |
| |6 |
| | |
| |RX-27 |
| |DO-06 |
| |7 |
| | |
| |RX-CLK |
| |RX-CLK |
| |26 |
| | |
| | |
| |The following are the pin numbers for the 28 signals output from the |
| |National Semiconductor Channel Link chip on the Frame Grabber: |
Channel Link Interface
[pic]
CameraLink Cable
[pic]
CameraLink Cable Ordering
[pic]
FRONT VIEW REAR VIEW
[pic] [pic]
SENSOR PACKAGING
[pic]
SI-3300-CL ENCLOSURE DIMENSIONS
[pic]
SI-3300 Spectral Response Curve
[pic]
SI-3300-RGB Cover Glass Filter Response (IRC-30)
[pic]
SI-3300 SENSOR PCB DIMENSIONS
[pic]
Revision Updates
|Rev 1.1 |Added “g” mode descriptions for Genlock operation (-H models) |
|7/31/04 |Added -T camera option for External TTL trigger and Global Reset operation |
Contact Information
Silicon Imaging, Inc.
sales@
Ordering Information
|SI-3300M-CL |3.2 Megapixel MegaCamera, Monochrome, 20~40MHz Cameralink Camera |
|SI-3300RGB-CL |3.2 Megapixel MegaCamera, Color, Cameralink Camera |
|SI-3300M-S |3.2 Megapixel, Monochrome, Cameralink Frame Grabber, Power Supply & Cables |
|SI-3300RGB-S |3.2 Megapixel, Color Cameralink Frame Grabber, Power Supply & Cables |
|-T |External TTL-Trigger trigger input, Power/Trigger Cable & Global Reset Mode |
|-H |High Speed version, 20~80MHz operation |
|PS-5 |5VDC Power Supply |
|PC-2 |Power Cable, 2-Meter |
|CBL-3PT |Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug |
Legal Disclaimer
Silicon Imaging reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. No license, express or implied to any intellectual property rights is granted by this document.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SILICON IMAGING PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SILICON IMAGING PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
The Product described in this datasheet may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available upon request.
Copyright: Silicon Imaging, Inc., 2004
070804-Rev 1.0
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