SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY



SRI RAMAKRISHNA INSTITUTE OF TECHNOLOGY

COIMBATORE-10

(Approved by AICTE, New Delhi & Affiliated to Anna University)

DEPARTMENT OF INFORMATIOM TECHNOLOGY

|Course Code & Title|CS6201 & DIGITAL PRINCIPLES AND SYSTEM DESIGN |L P T C |

| | |3 0 1 3 |

|Class |B.Tech (INFORMATIOM TECHNOLOGY) |Semester |II |

|Regulation |Anna University, Chennai , R2013 |

|Course Prerequisite|Fundamentals of computer programming, Physics -I |

|Programme |PEO 1: To produce high quality graduates who can face the challenges in the developing field of |

|Educational |Information Technology and also pursue higher studies in India and Abroad by acquiring |

|Objectives |sound knowledge in Engineering, Computing and Mathematics. |

| |PEO 2: The Information Technology graduates shall be able to design the computing systems with |

| |highest standard to satisfy the needs of the society with reasonable cost. |

| |PEO 3: The graduates shall have Ethical Attitude and shall satisfy the needs of the industries |

| |and research institutions in India and Abroad. |

| |To learn how to design digital circuits, by simplifying the Boolean functions. |

|Course |To give an idea about designs using PLDs |

|Objectives |To write codes for designing larger digital systems. |

|Course Outcomes |At the end of the course the students will be able to , |

| | |

| |CO1 .Implement different methods used for the simplification of Boolean functions. |

| |CO2. Design and implement combinational circuits. |

| |CO3. Analyze and design Synchronous sequential circuits. |

| |CO4. Analyze and design Asynchronous sequential circuits. |

| |CO5. Understand the operation of state-of-the-art components to design and build complex digital systems, such as memories, PLA, PALs and |

| |programmable logic devices. |

|Programme Outcomes | PO 1:  Ability to apply knowledge of Computing, Mathematics, Science and Engineering |

| |fundamentals appropriate to Information Technology. |

| |PO 2:  Ability to analyze a problem, and identify and formulate the computing requirements |

| |appropriate to its solution. |

| |PO 3:  Ability to design, implement, and evaluate a computer-based system, process, component, |

| |or programme to meet desired needs with appropriate consideration for public health and |

| |safety, cultural, societal and environmental considerations. |

| |PO 4:  Ability to design and conduct experiments, as well as to analyze and interpret data. |

| |PO 5:  Ability to use current techniques, skills, and modern tools necessary for computing practice. |

| |PO 6:  Commitment in work with professional, ethical, legal, security and social issues and |

| |responsibilities. |

| |PO 7:  Ability to function effectively individually and on teams, including diverse and |

| |multidisciplinary approaches, to accomplish a common goal. |

| |PO 8:  Ability to communicate effectively with a range of audiences. |

| |PO 9:  Recognition of the need for and ability to engage in continuing professional development. |

| |PO 10: Understanding of Engineering and Management principles and apply those to one’s own |

| |work, as a member and leader in a team to manage projects. |

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|Mapping |Course Outcomes (COs) |

| |Cognitive Level |

| |Program Outcomes (POs) |

| | |

| | |

| | |

| | |

| | |

| | |

| |PO1 |

| |PO2 |

| |PO3 |

| |PO4 |

| |PO5 |

| |PO6 |

| |PO7 |

| |PO8 |

| |PO9 |

| |PO10 |

| | |

| |CO1. Implement different methods used for the simplification of Boolean functions. |

| |Knowledge |

| |Π |

| | |

| | |

| |Π |

| |Π |

| | |

| | |

| | |

| | |

| | |

| | |

| |CO2. Design and implement combinational circuits. |

| |Comprehension |

| |Π |

| |Π |

| |Π |

| |Π |

| |Π |

| | |

| | |

| | |

| | |

| | |

| | |

| |CO3.Analyze and design Synchronous sequential circuits. |

| |Analysis& Synthesis |

| | |

| |Π |

| |Π |

| |Π |

| |Π |

| | |

| | |

| | |

| | |

| | |

| | |

| |CO4. Analyze and design Asynchronous sequential circuits. |

| |Analysis& Synthesis |

| | |

| |Π |

| |Π |

| |Π |

| |Π |

| | |

| | |

| | |

| | |

| | |

| | |

| |CO5.Understand the operation of state-of-the-art components to design and build complex digital systems, such as memories, PLA, |

| |PALs and programmable logic devices. |

| |Evaluation |

| | |

| | |

| |Π |

| |Π |

| |Π |

| | |

| | |

| | |

| | |

| | |

| | |

|References |TEXT BOOK: |

| |1. Morris Mano M. and Michael D. Ciletti, “Digital Design”, IV Edition, Pearson Education, 2008. |

| |REFERENCES: |

| |1. John F. Wakerly, “Digital Design Principles and Practices”, Fourth Edition, Pearson Education, 2007. |

| |Charles H. Roth Jr, “Fundamentals of Logic Design”, Fifth Edition – Jaico Publishing House, Mumbai, 2003. |

| |3. Donald D. Givone, “Digital Principles and Design”, Tata Mcgraw Hill, 2003. |

| |4. Kharate G. K., “Digital Electronics”, Oxford University Press, 2010. |

| |e-Learning Resources : |

| | contents/IIScBANG/DigitalSystems/DigitalSystems.pdf |

| | |

|Mode of Evaluation |1. Internal Assessment(20 Marks) |

| |Internal assessment Test 1 will be conducted for 50 marks(5*2=10 & 2*20=40) |

| |Internal assessment Test 2 will be conducted for 50 marks(5*2=10 & 2*20=40) |

| |Internal assessment Test 3 will be conducted for 50 marks(5*2=10 & 2*20=40) |

| |(All the three test marks will be considered for assessment out of 20 marks) |

| |Tests will be conducted as per the schedule given by the university. |

| |2.External Assessment(80 Marks) |

| |University will conduct end semester examination for 100 marks (10*2=20 & 5*16=80) |

| |Performance will be considered for assessment out of 80 marks |

|Faculty |Ms.P.Narmadhadevi,AP/ECE |

LECTURE PLAN

|Unit |Topics to be covered as per curriculum |Reference |Period |

|I |BOOLEAN ALGEBRA AND LOGIC GATES | | |

| |Review of Number Systems |T1:3-14 |1 |

| |Arithmetic Operations |T1:15-16 |1 |

| |Binary Codes |T1: 17-24 |1 |

| |Boolean Algebra and Theorems -Boolean Functions |T1:34-46 |2 |

| |Simplification of Boolean Functions using Karnaugh Map and Tabulation Methods |T1:46-55,67-87,112-120 |3 |

| |Logic Gates- NAND and NOR Implementations |T1:55-60, T1:87-94 |1 |

| | | |9 |

| |Total | | |

| |COMBINATIONAL LOGIC | | |

|II | | | |

| |Combinational Circuits Analysis and Design Procedures |T1:135-142 |3 |

| |Circuits for Arithmetic Operations, |T1:143-159 |2 |

| |Code Conversion |R3:24-27 |1 |

| |Decoders and Encoders – |T1:162-174 |1 |

| |Multiplexers and Demultiplexers | | |

| |Introduction to HDL – |T1:120-129,174-189 |2 |

| |HDL Models of Combinational circuits. | | |

| |Total | |9 |

|III |SYNCHRONOUS SEQUENTIAL LOGIC | | |

| |Sequential Circuits , Latches and Flip Flops |T1:197-199, T1:199-210 |1 |

| |Analysis and Design Procedures |T1:210-220,238-246 |2 |

| |State Reduction |T1:233-238 |2 |

| |and State Assignment | | |

| |Shift Registers –Counters |T1:255-293 |2 |

| |HDL for Sequential Logic Circuits. |T1:293-298 |2 |

| |Total | |9 |

|IV |ASYNCHRONOUS SEQUENTIAL LOGIC | | |

| |Analysis and Design of Asynchronous Sequential Circuits |T1:436-444,451-457 |3 |

| |Reduction of State and Flow Tables |T1:457-464 |3 |

| |Race-free State Assignment –Hazards |T1:464-474 |3 |

| |Total | |9 |

|V |MEMORY AND PROGRAMMABLE LOGIC | | |

| |RAM and ROM |T1:308-314,322-328 |1 |

| |Memory Decoding –Error Detection and Correction |T1:314-322 |2 |

| |Programmable Logic Array –Programmable Array Logic |T1:328-336 |2 |

| |Sequential Programmable Devices |T1:336-351 |2 |

| |Application Specific Integrated |R1:786-794 |2 |

| |Circuits | | |

| |Total | |9 |

Total Hours: 45

|Contents beyond syllabus |Instruction Sequencing, Processor Design, Deal with testing of complex systems |

|Description |Helps student to execute an instruction sequentially, to design a processor and to test a complex system. |

COURSE INSTRUCTOR HOD PRINCIPAL

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