Hypervisor*Verificaon *and* Theory*of*Mul/core*Systems* - ACSAC
Hypervisor
Verifica/on
and
Theory
of
Mul/core
Systems
W.
Paul
Saarland
University
Orlando,
December
3,
2012
joint
work
with
E.
Cohen,
S.
Schmaltz....
What
is
a
kernel
?
tape(1,leS)
s_1
tape(1,right)
tape(2,leS)
s_2
tape(2,right)
tape(3,leS)
s_3
tape(3,right)
? The
Classic:
Turing
machine
kernel
? Simula/ng
k
one
tape
Turing
machines
by
1
one
tape
Turing
machine
? Tracks:
address
transla/on
? Head
posi/on
and
state:
process
control
block
? Round
robin:
scheduling
What
is
an
M--kernel
?
tape(1,leS)
s_1
tape(1,right)
tape(2,leS)
s_2
tape(2,right)
tape(3,leS)
s_3
tape(3,right)
? process
virtualiza/on:
?
simula/ng
k
machines
of
type
M
by
1
one
tape
machine
of
type
M
? +
sytem
calls
?
for
inter
process
communica/on...
? M:
? MIPS,
ARM,
Power,
x64...
What
is
a
hypervisor
?
? guests
can
be
opera/ng
systems,
i.e.
in
system
mode
? 2
levels
of
transla/on
? hypervisor
page
tables
? guest
page
tables
? ,subdivide
tracks`
? hardware
support
? nested
page
tables
? no
hardware
support:
? composi/on
of
transla/ons
is
transla/on
? maintain
,shadow
page
tables`
(SPT)
for
combined
transla/o
? redirect
memory
management
unit
(mmu)
to
SPTs
Background
? 2007--2010:
effort
to
formally
verify
MS
HyperV
? part
of
German
VerisoS--XT
project
(Paul,
Broy,
Podelski,
Rybalchenko...),
13
Mio
? MS
Windows
+
Research
(Cohen,
Moskal,
Leino,...)
? We
failed
2010
? tool
development
(VCC)
successful
? crucial
por/ons
of
code
verified
? tool
documenta/on
and
soundness
argument
less
than
perfect
? paper
and
pencil
theory
incomplete
in
2010
? We
did
not
know
(exactly
enough)
what
to
prove
................
................
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