NEGATIVE BIAS TEMPERATURE INSTABILITY

A Project Report on

NEGATIVE BIAS TEMPERATURE INSTABILITY

EE311 Term Paper

Prashant Khokhar Shiv Prakash

Shouvik Ganguly Rakesh Meena

Kundan Kanwaria Asutosh Tiwari

Y9427 Y9551 Y9558 Y9474 Y9300 Y9152

1.Introduction

Negative Bias Temperature Instability (NBTI) is a key reliability issue in MOSFETs. It is of immediate concern in p-channel MOs devices, since they almost always operate with negative gateto-source voltage; however, the very same mechanism affects also n-MOS transistors when biased in the accumulation regime, i.e. with a negative bias applied to the gate too. NBTI manifests as an increase in the threshold voltage, a degradation of the mobility, drain current and trans-conductance.

This instability in MOSFETs has been known since 1996. It is become a reliability issue in silicon integrated circuits, because gate electric field have increased as a result of scaling, increased chip operating temperature, surface p-channel MOSFETs have replaced buried channel devices, and nitrogen is routinely added to thermally grown SiO2.

A brief history on NBTI shows that reliability issue in MOSFETs is a serious issue:

Experiments in late 1960s by Deal and Grove at Fairchild Role of Si-H bonds and BTI vs. NBTI story (J. Electrochem Soc. 1973;114:266) Came out naturally as PMOS was dominant Important in FAMOS and p-MOS EEPROMS (Solid State Circuits 1971;6:301)

Theory in late 1970s by Jeppson (JAP, 1977; 48:2004) Generalized Reaction-Diffusion Model Discusses the role of relaxation, bulk traps Comprehensive study of available experiments Early 1980s Issue disappears with NMOS technology and buried channel PMOS

Early 1980s Issue disappears with NMOS technology and buried channel PMOS

Late 1980s and Early 1990s Begins to become an issue with dual poly gate, but HCI dominates device reliability

Late 1990s/Early 2000 (Kimizuka, IRPS97; 282. Yamamoto, TED99; 46:921. Mitani, IEDM02; 509) Voltage scaling reduces HCI and TDDB, but increasing field & temperature reintroduce NBTI concerns for both analogue and digital circuits. Numerical solution is extensively used for theoretical modeling of NBTI

What is NBTI?

NBTI is an increase in the absolute threshold voltage, a degradation of the mobility, drain current, and transconductance of p-channel MOSFETs. These typesof effects are generally found in pMOSFETs. When a PMOS transistor is biased in inversion, the dissociation of Si-H bonds along the silicon-oxide interface causes the generation of interface traps. The rate of generation of these traps is accelerated by temperature, and the time of applied stress. These traps cause an increase in the threshold voltage (Vth) of the PMOS transistors. An increase in Vth causes the circuit delay to degrade, and when this degradation exceeds a certain magnitude, the circuit may fail to meet its timing specifications. This effect is known as the Negative Bias Temperature Instability (NBTI). Mechanism of NBTI is the degradation of Si-H bonds broken by the chemical reaction with high energy holes on SiO2/Si surface. In PMOS voltage between gate and the source is negative (Vgs = -Vdd), causes the interface traps and when (Vgs = 0) causes the reduction in the interface traps. Thus the effect of NBTI on the PMOS depends on the time the device has been stressed, and relaxed.

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It is commonly accepted that two kinds of trap contribute to NBTI: When Vgs is negative, interface traps are generated. Those traps cannot be recovered over a reasonable time of operation i.e. Vgs= 0. It is believed that the electric field is able to break Si-H bonds located at the Silicon-oxide interface. H is released in the substrate where it migrates. The remaining dangling bonds (Si-Pb center) contribute to the threshold voltage degradation. On top of the interface states generation some pre-existing traps located in the bulk of the dielectric (and supposedly nitrogen related), are filled with holes coming from the channel of p-MOS. Those traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over time. NBTI Models Many models have been discussed on the NBTI. Here we discuss some model on which NBTI affects, which include Reaction Diffusion model, Models of Source Drain bias. Model of Source Drain Bias In this experimental model following devices were used: surface channel P+poly-silicon gate pMOSFETs fabricated with silicon oxynitride (SiON) gate dielectric using a 90 nm nodeCMOS technology, with channel width of 10?m, andvarious channel lengths. The gate dielectrics withequivalent oxide thickness (EOT) = 1.9 nm were grownby thermal oxidation followed by plasma nitridation and post-deposition thermal annealing. In this experiment, negative voltage was applied to the gate and drain, source and substrate grounded. The stress circuit diagram is given here:

Fig 1.1: Stress Circuit Diagram The experimental result of source drain bias shows the effect of Vds on Vth (Vth shift). The graph given below shows the effect of source drain bias in threshold shift of pMOSFET for different channel lengths.

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Fig 1.2: Vth vs Vds for different channel lengths

From the graph, we observe that for L = 0.1m, when |Vds| changes from 0 to 0.5V then Vth does not change much but further increasing |Vds| increases NBTI degradation. For L = 0.3m the NBTI degradation is initially reduced but increases after |Vds| = 1.5V. We also observe that minimum degradation occurs around |Vds| =1.5 V. This degradation leads to the generation of non-uniform neutral hydrogen. Generation of more interface traps leads to the diffusion of hydrogen from the source to the drain. The following figure shows the diffusion of hydrogen.

Fig 1.3: Hydrogen Diffusion

When there is S/D bias the interface traps density (Nit) at the drain canbe reduced and the Vth shift will be less. In above figure it is also observed that devices are more stressed in the linear region since |Vgs| > |Vth| and |Vds| < |Vgs|. The drain current, which is linearly dependent on the Vds, can be expressed as

Id

=

C(Vgs

?

Vth)Vds

where w is the channel length in cm, is the carrier mobility in cm2/(V-sec), and C is oxide capacitance inF/cm2. The drain current can also be expressed in terms of carrier velocity as

Id =qpvA where p is carrier density in cm-3, vis carrier velocity incm/sec and A is the cross-section area in cm2.

A = W.H where H is the inversion layer thickness in cm.

From the above equations we can find the carrier velocity as

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v= C(Vgs -Vth ) Vds

qH

L

In the linear region, the carrier density (p) can beexpressed as the oxide charge (Qin Coulomb/cm2)divided by the inversion layer thickness (H) and the unitcharge (q):

p=

Q = C(Vgs ? Vth)

Then

v = . Vds L

The average energy of hole is

E

=mpv2

=

mp

?

2

Vds 2 L2

So, the larger is Vds, larger will be the hole velocity and higher the hole energy. Generally, the energy

required to break the Si-H bond is around 0.3eV. So, energy higher than this enhances the NBTI and

this enhanced NBTI leads to more Si-H bond breakdowns. Fig. 1.4 shows the variation of average hole energy with the S/D bias i.e. Vds.

Fig 1.4: Average Energy vs S/D bias

The main contribution to the Vth shift is the energetic hole which induces higher NBTI degradation with higher S/D bias.

2. Reaction-Diffusion model

This analytical model captures the effect of stress and relaxation. These types of R-D model limited to a single stress cycle and a single relaxation cycle.This analytical model includes stress and relaxation phase as well as frequency independent property of NBTI.In this model interface traps are occurred at the SiO2/Si interface and this reaction release the Hydrogen and this reaction also depend linearly on

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