Stratix_10_GX_MX_SX_Schematic_Review_Worksheet

Plane/Signal Schematic Name Connection Guidelines Comments / Issues TCK Dedicated JTAG test clock input pin. This pin can also be used to access the SDM and HPS JTAG chains. Connect this pin through a 1-kΩ pull-down resistor to GND. This pin has an internal 25-kΩ pull-down. Do not drive voltage higher than the VCCIO_SDM supply for the TCK pin. ................
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