Self Biased Folded Cascode Operational Amplifier
Low Current Electrochemical Measurement for Biotechnology
Applications
Qualifying Report
Arizona State University
Kevin W. Glass
Advisor: Dr. Allee
Co-Adviser Dr. Song
Introduction
Electrochemical measurements have a wide range of applicability, in areas as wide ranging as corrosion analysis, analysis of water purity, to biomedical and biotechnology applications. There is a high level of motivation for the development of small form factor, low power, and low cost measurement systems. Key to the implementation of these new systems will be the development of integrated circuits to implement the high precision analog measurement electronics. This is the focus of our development project at ASU. We are taking a very cost effective, mature semiconductor technology, and using it to implement these circuits. The focus of this paper is to present an overview electrochemistry, the review current state of the art of single chip measurements systems, and review the initial design work that has been done on the project.
Overview of Electrochemical Reactions [1]
An electrochemical reaction is a chemical reaction involving the transfer of charge as a part of the reaction [1]. Typical electrochemical reactions are metal dissolution and
Oxygen reduction:
In contrast, the precipitation of a metal hydroxide is an illustration of a chemical (1) reaction that does not involve charge transfer:
[pic] (2)
Faraday's Law relates the quantity of charge involved in an electrochemical reaction with the number of moles of reactant, and number of electrons required for the reaction.
[pic]
= q* Avogadro’s number, NA (3)
Faradic processes are processes that follow Faraday's Law. Non-Faradic processes also occur. These are processes such as adsorption that do not involve a complete transfer of charge from the solution to the metal. An electrochemical half cell is an electrochemical reaction that results in a net surplus or deficit of electrons, and it corresponds to the smallest complete reaction sequence. While it may proceed as a sequence of simpler reactions, these intermediate stages are not stable. Oxidation or anodic reactions are those that result in a surplus of electrons. These typically correspond to the various metal dissolution reactions, such as:
[pic] (4)
Reduction or cathodic reactions result in the consumption of electrons. These typically correspond to the oxygen reduction or hydrogen evolution reactions:
[pic] (5)
The above reactions have been shown going only in one direction. The reverse reactions are perfectly possible. The reverse of an anodic reaction is a cathodic reaction and vice versa. A reaction is said to be reversible if it can proceed easily in either direction as conditions change. Usually, as the electrochemical potential is changed. Chemical reversibility relates to the chemical feasibility of the reaction. A chemically irreversible reaction is one in which the reverse reaction is prevented by the occurrence of competing reactions. A thermodynamically reversible reaction is a chemically reversible reaction for which the reaction will change direction as a result of an infinitesimal change in potential. A practically reversible reaction is a thermodynamically reversible reaction that occurs at a significant rate with small overpotentials. Thermodynamically reversible reactions will adopt an equilibrium potential which is described by the Nernst equation:
[pic] (6)
R = molar gas constant(J/(mol*K)=Boltzman’s Constant,k,
Multiplied by NA, Avogadro’s number
Reference electrodes are needed to convert from the charge carriers in the metal (electrons) to the charge carriers in solution (ions) in a reproducible fashion. They must be practically reversible. The Normal Hydrogen Electrode (NHE) is used as the (arbitrary) standard. This consists of hydrogen at unit activity (i.e. solution in equilibrium with hydrogen gas at 1 atmosphere) in equilibrium with unit activity of hydrogen ions in solution (1.19 M HCl solution). The equilibrium potential is detected with a platinum electrode that is coated with platinum black (finely divided platinum) to enlarge the effective surface area. The NHE for many applications is inconvenient use. Examples of other secondary reference electrodes that have been developed are as follows: Saturated Calomel Electrode (SCE), Calomel, Mercurous Sulphate, Mercurous Oxide, Silver Chloride, Copper Sulphate, Zinc/Seawater.
There is a tendency for charged species to be attracted or repelled from the metal-solution interface. This gives rise to a separation of charge. A layer of solution develops with a different composition from the bulk solution. This is known as the electrochemical double layer. There are a number of theoretical descriptions of the structure of this layer. These include the Helmholtz model, the GouyChapman model and the GouyChapmanStern model. The variation of the charge separation with the applied potential causes the electrochemical double layer to have an apparent capacitance, known as the double layer capacitance.
Applying the Hermholtz model, shown in Figure 1., there are two groups of oriented molecules [2], comprising three conceptual layers of space charge: the hydration sheath (one layer of oriented water molecules); the inner Helmholtz plane (IHP), which is the location of the oxygen atoms in the hydration sheath; and the outer Helmholtz plane (OHP), which is the first layer of hydration ions, and the outer layer of the double layer formed with the electrode. If it is assumed that the ions are formed into a “sheet” at the outer Helmholtz plane, and that the voltage drop through the dielectric is linear along a parallel plane, the Helmholtz capacitance can be estimated by:
CH=ε0εrA/x, where εr is the relative permittivity of the medium between the two plane (usually water), A the surface area of the electrode, x the distance to the outer Helmholtz plane.
[pic]
Figure 1. Illustration of Helmholtz Model for Double Layer region around electrode in an electrochemical cell [2].
An activation controlled reaction is one for which the rate of reaction is controlled solely by the rate of the electrochemical charge transfer process. This is in turn an activation-controlled process with kinetics described by the ButlerVolmer equation [1]:
[pic] (7)
The Butler-Volmer equation is valid over the full potential range. It is analogous to two diodes in anti-parallel [2]. It is interesting to point out that there is a direct electrochemical equivalent to the thermal voltage from semiconductor electronics:
VT=kT/q=RT/F (8)
Simpler approximate solutions over restricted ranges of potential can be derived [1]: For irreversible reactions with large overpotentials, the Tafel equations apply:
[pic] (9)
Or, more generally
[pic] (10)
For small overpotentials, with [pic]A = [pic]C = 0.5:
[pic] (11)
Then
[pic] (12)
In terms of the anodic and cathodic Tafel slopes, ba and bc, (13)
[pic]
Where bc is strictly negative.
Mass transport control implies fast kinetics, hence the surface reaction is reversible and the potential is given by the Nernst equation applied to the surface concentrations:
(14)
[pic]
This analysis leads to a limiting current density: (15)
[pic]
When multiple reactions are possible, the resultant kinetics is described by the mixed potential theory. This simply says that the total current in an external circuit is the sum of all of the currents due to the individual reactions (with anodic currents being positive and cathodic current negative).
Real electrochemical reactions tend to occur as a sequence of very simple steps. For example, even a very simple reaction such as hydrogen evolution occurs as two steps, with two alternatives for the second step: (16)
[pic]
The rate of the overall reaction is controlled by the rate of the slowest reaction, and this is known as the rate controlling step. This may be an electrochemical reaction, such as Step 1, or a chemical reaction such as Step 2a. Different rate controlling steps will typically give a different Tafel slope for the reaction and a different dependence on concentration of reactants. Electrochemical measurements can be used to determine the reaction mechanism and the rate-controlling step.
Overview of Electrochemical Measurement [3]
The basic electrochemical cell used for measurement applications has three terminals or electrodes. These are the Working Electrode, the Reference Electrode, and the Counter (or auxiliary) Electrode.
The Working Electrode is the electrode where the potential is controlled and where the current is measured. For many electrochemical experiments, the Working Electrode is an "inert" material such as gold, platinum, or glassy carbon. For these applications, the Working Electrode serves as a surface on which the electrochemical reaction takes place. In other applications, such as corrosion testing, the working electrode is a sample of the corroding metal. The working electrode can be bare metal or coated.
For battery measurements, the current is measured directly from the anode or cathode of the battery.
The Reference Electrode is used in measuring the working electrode potential. A reference electrode should have a constant electrochemical potential with no current flowing through it. The most common lab reference electrodes are the Saturated Calomel Electrode (SCE) and the Silver/Silver Chloride (Ag/AgCl) electrodes. Field probes sometimes employ a pseudo-reference, and use a piece of the working electrode material.
The Counter (Auxiliary) Electrode is a conductor that completes the cell circuit.
The Counter Electrode in laboratory cells is usually an inert conductor like platinum or graphite. In field probes, it is usually another piece of the Working Electrode material. The current that flows into the solution via the Working Electrode leaves the solution via the Counter Electrode. The electrodes are immersed in an electrolyte (an electrically conductive solution).
The electrodes, the solution, and the container holding the solution are referred to as an electrochemical cell.
[pic]Figure 1. Three Terminal Electrochemical Cell with potentiostat for current measurement [3].
Figure 1. show a block diagram of an electrochemical cell and the usual measurement circuit employed, the potentiostat. A potentiostat is an electronic circuit that controls the voltage difference between the working electrode and the reference electrode. The potentiostat implements this control by sourcing current into the cell through the counter electrode. In almost all applications, the potentiostat measures the current flow between the working and counter electrodes. The controlled variable in a potentiostat is the cell potential and the measured variable is the cell current.
The circuit consists of four main blocks. Unity gain differential amplifiers are designed with an X1. The output voltage of this circuit is the difference between the inputs from the working electrode and reference electrode. The blocks labeled Voltage and Current*Rm are the voltage and current signals that are sent to the system A/D converter for digitization.
The electrometer circuit measures the voltage difference between the reference and working electrodes. Its output has two major functions: it is the feedback signal in the potentiostat circuit and it is the signal that is measured whenever the cell voltage is needed. An ideal electrometer has zero input current and infinite input impedance. This is necessary since any current flow through the reference electrode can change its voltage. All modern electrometers have input currents low enough that they do not create loading on the reference electrode. Two important electrometer characteristics are its bandwidth and its input capacitance. The electrometer bandwidth characterizes the AC frequencies the electrometer can measure when it is driven from a low impedance source. The electrometer bandwidth must be higher than the bandwidth of the other electronic components in the potentiostat. The electrometer input capacitance and the reference electrode resistance form an RC filter. If this filter’s time constant is too large, it can limit the effective bandwidth of the electrometer and cause system instabilities. Smaller input capacitance translates into more stable operation and greater tolerance for high impedance reference electrodes. The Current to Voltage (I/E) converter in the simplified schematic measures the cell current. It forces the cell current to flow through a current measurement resistor, Rm. The voltage drop across Rm is a measure of the cell current. To measure current over a wide dynamic range, different values of Rm need to be switched in. In actual implementation, having to have multiple resistors and switches can have implementation issues at very low currents. The I/E converter bandwidth depends strongly on its sensitivity. Measurement of small currents requires large Rm values. Stray (unwanted) capacitance in the I/E converter forms an RC filter with Rm, limiting the I/E bandwidth. There are other circuit approaches that can be applied to the current measurement problem that do not have some of these drawbacks. These will be discussed later.
The control amplifier is a servo amplifier that compares the measured cell voltage with the desired voltage, and drives current into the cell to force the voltages to be the same. The measured voltage is fed to the negative input of the control amplifier. A positive perturbation in the measured voltage creates a negative control amplifier output. This negative output counteracts the initial perturbation, and forms a negative feedback control loop. Under normal conditions, the cell voltage is controlled to be identical to the signal source voltage. The control amplifier has a finite limit to the output voltage it can swing and current it can source. These limitations put constraints on cell and electrode implementation, and the types of cells that can be measured.
The circuit that sources the signal input is usually a digitally controlled voltage source. It is generally the output of a Digital to Analog (D/A) converter that converts digitally generated number sequences into voltage waveforms. Waveforms typically generated include DC voltages, voltage ramps, and sine waves.
The Potentiostat circuit can be connected to the electrochemical cell in a different arrangement to create a galvanostat, also known as a ZRA (Zero Resistance Ammeter). The potentiostat in Figure 1., becomes a galvanostat when the feedback is switched from a cell voltage control amplifier input signal, to a working electrode cell current input signal. The instrument then controls the cell current rather than the cell voltage. The electrometer output can still be used to measure the cell voltage. A ZRA allows you to force a potential difference of zero volts between two electrodes. The cell current flowing between the electrodes can be measured.
Coulometry is the complete electrolysis of a solution at an electrode and the measure of the total Coulombs of change produced under Faraday’s Law.
Overview of Electrodes
An additional resistive effect to the current expressed by ButlerVolmer equation results from the spreading resistance of the bulk electrolyte [2]. It is geometric specific and can be derived or estimated by numerical integration of the electrolyte volume surrounding the electrode. The Warburg impedance is another effect that is related to diffusion waves of ions near an electrode under sinusoidal drive. It is often represented in models as a parallel RC circuit, but physically it is neither capacitive nor resistive, with a nearly constant phase shift of 45o. The electrode effects described so far can be approximated as an AC small signal electrical model. This model is quite useful and important since it models the behavior of the electrochemical cell and electrodes to support the development of the surrounding measurement circuitry. This model is shown in Figure 2. In practice, empirical measurements are almost always required to accurately model real world electrodes.
[pic]
Figure 2. AC small signal model of electrode solution interface [2].
The basic transducer is a small metal electrode insulated everywhere except at a specific location for the chemical reaction to take place. Many examples have been demonstrated of micro-machined electrodes and have been used for electrochemical experiments, and as sensors for industrial and medical applications. Due to their small size they offer significantly improved performance over macroscopic implementations. Microelectrodes can have hemispherical diffusion gradients, as opposed to planar gradients for macroscopic implementations. This allows more rapid access to ions in the solution. Arrays of microelectrodes can be connected in parallel, yet be diffussionally isolated if their spacing is large enough. Microelectronic and semiconductor fabrication techniques make these arrays feasible. Electrodes can be modified for improved selectivity by functionalizing the surface chemically. The required processing is often compatible with CMOS process technology and circuits.
With the application of advanced semiconductor lithography, Ultramicroelectrode (UME) Arrays can be fabricated. These new UME arrays have been applied to a wide range of analytical problems involving biotechnology, biomedical, environmental analysis, even remote electroanalysis on Mars. Reference [4] gives an excellent overview of recent silicon process technology employed, and examples of UME Arrays developed.
[pic] Figure 3. Example of process cross-section of a typical UME array device [4].
[pic]
Figure 3. SEM images of typical micro-fabricated array designs. Left) A “honeycomb” pattern of 564 10um diameter UMEs. Center) A “ring” design with 40 10um diameter UMEs. Outer and inner rings are on-chip counter and reference electrodes, respectively. Right) A “bicycle” design of 20 10um diameter UMEs, each surrounded by a ring counter/reference electrode [4].
An example process cross-section of a representative UME array silicon process is shown in Figure 3. Deposition of metals such as Iridium, Gold, Platinum or Carbon are added to the standard Silicon process for their electrochemical properties. Figure 3. shows some examples of UME arrays. Different geometries are used to improve performance and measurement accuracy.
Overview of Single Chip Electrochemical Measurement Systems
[pic]
Figure 4. Conceptual Schematic of Electrochemical Potentiostat Chip from Technical University of Denmark [5]
Technical University of Denmark designed an integrating data converter that had a measurement sensitivity of 1pA to 5nA [5]. It was implemented in 0.7um CMOS. It had an integrating capacitor value of greater than 100pF. Problem areas for the design were listed as: 1. the input offset voltage of the comparator and integrator, 2. Speed of the comparator, 3. charge injection from the switches, 4. noise. The dynamic range of the integrator was 1V, and the dual slope A/D had a resolution of 11 bits.
[pic]
Figure 5. Potentiostat Chip Architecture from Johns Hopkins University [6].
Johns Hopkins University developed a neurochemical sensor system to spatially sense and process neurotransmitters [7]. It is a VLSI implementation of a multichannel potentiostat that interfaces to a nitric-oxide sensor array. Pico-ampere to micro-ampere input currents are range normalized with programmable gain amplifiers, and digitized with 12 bit current mode sigma-delta A/D converters. First order noise shaping and 4096 times over-sampling with a 1MHz clock is used in the A/D converter for a conversion rate of 250Hz. Each potentiostat channel uses one working electrode maintained at virtual ground, with a potential applied to the reference electrode. A shift register scans the buffered decimated data and outputs it as a asynchronous serial data stream. The chip is fabricated in 0.5um CMOS and an 8 channel chip consumes 0.5mW of power. The device is used for neurological research and implantable neural prostheses. Each potentiostat channel uses one working electrode maintained at virtual ground, with a potential applied to the reference electrode.
[pic]
Figure 6. Simplified schematic for the input stage consisting of the current conveyor and programmable gain amplifier for the Multichannel Potentiostat Chip from Johns Hopkins University [7].
[pic]
Figure 7. Simplified schematic for the 12 bit current mode sigma delta A/D converter from the Multichannel Potentiostat Chip from Johns Hopkins University [7].
University of Michigan had a very interesting paper where they describe a new potentiostat architecture that is differential, rather than single ended (Figures 8.-10.). The device is fabricated in TSMC 0.18um CMOS, with a maximum supply voltage of 1.8V. The voltage swing required for an electrochemical reaction is set by the electrode metals and the electrolyte being used, and does not scale with electrode size. The motivation for this new design, is to be able maintain voltage swing while scaling the supply voltage to take advantage of newer technologies. An extra benefit is realized in improved power supply rejection.
[pic]
Figure 8. Standard single ended potentiostat circuit, fabricated with the new differential design in TSMC 0.18um. Designed at University of Michigan [8].
[pic]
Figure 9. New low voltage differential potentiostat circuit, fabricated in TSMC 0.18um. Designed at University of Michigan [8].
[pic]
Figure 10. Differential opamp used in new low voltage potentiostat circuit, fabricated in TSMC 0.18um. Constant gm biasing not shown. Device sizes in um. Designed at University of Michigan [8].
A very interesting low power and low noise amplifier was developed at University of Utah for neural recording applications (Figure 11.) [9]. This circuit is not directly useful for our application, since it is AC coupled with a capacitor, where the potentiostat application requires measurement of currents at DC.
The circuit has very good performance in terms of power dissipation versus input referred noise. It uses AMIs 1.6um process, the same as this project, and achieves 40dB gain, with 16uA supply current, and 2.2uVrms input referred noise voltage. DC biasing is achieved through diode connected p and n channel transistors, which allow the inputs to be AC couples with very low cutoff frequency. These devices alternately operate in the sub-threshold region or as lateral bipolar transistors, depending on the voltages across them. The net effect is that these diode connected transistor pairs function as extremely high value resistors.
Noise versus power dissipation is optimized for each transistor in the relatively standard OTA opamp that is employed in the design. Another factor that improves noise performance is that gain is set by reactive capacitive elements, with very low current running the diode connected bias transistors. A major contributor to the excellent noise performance is that the highly resistive bias transistors serve as a DC leakage path to eliminate the time accumulation of 1/f noise. In fact, measured results show the amplifier noise is dominated by channel thermal noise, not 1/f noise, as is usually the case with CMOS opamps.
[pic][pic]
Figure 11. Low noise neural recording amplifier developed at the University of Utah. Left schematic shows the top level. Right schematic shows the OTA opamp used in the design. Device is fabricated in AMI 1.6um technology [9].
[pic] [pic]
Figure 12. Left - Top level systems diagram of the electrochemical analysis system [11]. Right – More detailed top level diagram of the potentiostat [12].
The reference that was drawn on very heavily in the course of this work is the PhD Thesis from Richard Reay at Stanford University entitled “Microfabricated Electrochemical Analysis Systems” [10]. This work describes the design of a one electrochemical analysis system based on a potentiostat, A/D and D/A converters, and digital control. Figure 12. shows the top level diagram of the chip. The Potentiostat can measure 100fA to 40mA at a maximum sample rate of 2.5kHz. Power dissipation is 5mW.
[pic] [pic]
Figure 13. Switch implementation approaches. Left – Conventional nMOS transfer gate switch [10]. Right – Low junction leakage alternative. pMOS used with n well tied to reference supply (Gnd) to Vcc/Vss. Inputs to be measured are maintained very close to Gnd, so the voltage from p+ source/drain to n well is ~0V with negligible leakage [10].
Key to implementing the switched capacitor circuits of the potentiostat, and being able to measure such low currents without being swamped out by leakage, is the low leakage switch approach developed. The input to the dual slope A/D converter integrator is held at virtual ground – which is very close to the supply reference ground of the chip. By biasing the n wells that the low leakage p channel switches are in to reference ground, the bias voltage across the source drain junctions is very close to 0V, meaning very low leakage. Figure 13. shows the cross section of the switches used.
[pic]
Figure 14. Block Diagram of A/D converter integrator. Switches with dashes are low junction leakage p channels with n wells connected to gnd [10].
Figure 14. shows the design of the integrator section of the dual slope A/D. During phi 1, the integration capacitor is reset [10]. The difference between the falling edges of phi 1 and phi 2 is the first integration time. Phi 3 is the second integration time that lasts until Vout crosses zero. The offset voltage due to charge injection of the switches is compensated for with a calibration cycle. An A/D conversion is done with the input current set to 0. The resulting output is digitally subtracted from the subsequent actual conversion cycle to correct the measurement. The signal phiaz , identifies a calibration cycle. A second switch is added in series with the low leakage feed back switch that is in the grounded n well, to avoid forward biasing the source diffusion or this transistor. The advantage of this circuit topology is that the positive terminal of the opamp stays at a constant voltage.
[pic][pic]
Figure 14. Left – Top level conceptual schematic of offset cancellation for dual input opamp [10]. Right – Circuit implementation of dual input opamp with dedicated offset cancellation input [11].
Figure 14. shows the opamp developed for the project the has an extra differential input for offset cancellation. The primary inputs to the opamp are grounded, and the output offset voltage stored on C1. This voltage is then analog subtracted from the input offset at the primary inputs to the opamp. This circuit is used in the control amplifier that drives the counter electrode.
A/D Converter Selection for this Project
The candidate A/D converter approaches for this project could be narrowed quite quickly. Our desired ultimate goal was to have a converter with 16 bits resolution. This is quite aggressive based on the previous work reviewed. The application frequency range is very low, so conversion speed is not an issue. Low noise is a major issue since our goal is to measure currents possibly as low as 1pA, and if possible, 0.1pA. Typical resistive ladder, ratioed capacitor, or cyclic converters did not meet the requirements because of resolution limitations from component matching, and noise issues.
Sigma-Delta converters were a possibility, and were employed in some of the prior work reviewed. Resolution of these types of converters can be very high with large over sampling ratios. This is obviously possible since the frequencies involved for this application are so low. The application of Sigma-Delta converters, however, can have issues for DC measurements - a main application for this project. For signals that are not varying with time, they can develop output tones or instabilities. The proper converter architecture and algorithms will have to be developed for this specialized application. A low noise front end amplifier and low pass filter are still required. The low noise amplifier is necessary to set the noise floor, and will most likely be an opamp that can be used as an active filter low pass filter. Low pass filtering is necessary to limit the noise power layered on top of the desired signal to be measure. The more narrow this bandwidth the lower the noise. The low pass filter is also necessary for anti-aliasing, although the noise requirement will set the lower limit.
[pic]
Figure 15. Burr Brown Precision Switched Integrator Transimpedance Amplifier. This can be used as a building block for an integrating A/D converter [13]
Historically, integrating A/D converters have been used for precision current measurement instruments, in particular, the dual slope A/D converter. This is the primary approach that was decided on for this project. This converter employs a low noise operational amplifier in an inverting configuration with a capacitor feeding from the output to the inverting input to form a miller integrator (Figure 15.). A resistor is inserted from the input to the inverting opamp terminal for voltage measurements. For current measurements, the resistor is eliminated. A switched current in discrete time effectively functions as a resistor, so in both the voltage and current measurement case, the integrator in combination with the input signal forms a low pass filter, band limiting and attenuating higher frequency noise. Besides the filtering effect, the opamp integrator has another advantage. To adjust for different voltage or current ranges, the integration time can be varied. The lower the current range measured, the longer the integration time. This allows the measurement range of the converter can be varied without switching in any different components (e.g. If resistors were used for the opamp feedback, different resistor values would need to be switched in). For current measurement the integrating opamp forms a transimpedance amplifier (TIA), meaning for a given current input the output is translated to and proportional in voltage.
The converter becomes dual slope if the input to the integrator is switched between first integrating the current of interest, Iin, over time T1 and then integrating a reference current Iref, over time T2 . The current is then:
Iin = (T2 / T1 ) Iref (17)
Modifications can be made to the dual slope technique to account for opamp offset, switch charge injection and other non-idealities. Representative of these techniques is reference [14]. Many papers exist outlining new integration and timing techniques for the dual slope converter, the most general of which is reference [15]. The paper puts forward a generalized approach of performing two complete dual slope integration cycles, T1, T2, T3, and T4, alternately switching between one or more reference voltages. A 24 entry table is included in the paper that shows all the possible combinations and permutations.
The white noise behavior of the integrating A/D converter is analogous to the integrate and dump matched filter from communications theory. The DC current being detected is the signal. As the integration time is increased, the energy of the detected signal also increases (in this case it’s a DC current, not a pulse). The noise, however, is random. The integrator averages the noise over the integration period. The signal to noise ratio of the measured DC signal would be:
SNR=CV2 /N0 (18)
where N0 is the additive white noise power spectral density.
To reduce the effects of integrator offsets and 1/f noise, a technique called Auto Zero can be applied [16]. This was employed digitally by the reference [10] dual slope A/D. Conceptually the technique works as follows: The 2 inputs to the integrator or opamp are shorted together, and the output stored in a sample and hold circuit. This stored output contains both the offset of the opamp, and a sampling of the instantaneous 1/f, and thermal noise. The input signal is then evaluated along with the offset and noise from the previous cycle being subtracted off. It is of necessity that the integrator be clocked at a frequency below the bandwidth of the opamp or integrator. This is because the opamp would not have enough time to settle between successive measurements or samples. This has a number of effects on the input referred noise of the integrator. Since this is a pure integrator, there is a pole at DC and all 1/f noise at 0Hz is blocked out. The AZ sample of 1/f noise has a slowly decaying autocorrelation function with respect to the current 1/f noise at the input. This means that there is some 1/f noise cancellation provided by the AZ sample. The white thermal noise has a very fast decaying autocorrelation function, meaning there is virtually no correlation between the AZ sample stored and the current noise at the input. This means that the thermal noise will add. In fact, this is an under sampled system, and the thermal noise spectrum over the integrator bandwidth will fold over by multiples of the under sampling ratio.
The new noise power spectral density is approximated by:
NN≈2*Bopamp *N0 (19)
Figure 16. Illustrates the noise effects of the auto zero process.
[pic] [pic] a.) b.)
Figure 16. a.) Basic Auto Zero (AZ) amplifier block diagram [16]. b.) The effect of the AZ process on a first order low-pass filtered 1/f noise having a bandwidth 5 times larger than the sampling frequency [16].
Correlated Double Sampling (CDS) is another offset cancellation technique that is closely aligned with AZ. With the AZ technique the integrator outputs are invalid for the clock phase while the offset is being sample. The CDS circuit takes the basic AZ topology shown in Figure 16. a. and adds another sample and hold circuit to the output. This second sample and hold acts as a type of analog latch, to hold the previous integrator output while its offset is being sampled.
[pic] Figure 17. High Level Block Diagram of Electrochemical Measurement System under development at ASU.
Figure 17. shows the top level system block diagram of the system this research group is developing. As was stated, a dual slope A/D converter is employed. All control and DSP functions are provided by a programmable logic device. The first pieces of the system to be designed were the operational amplifiers. These were key technology items, since the counter electrode required very high drive capability, and the low noise opamp was critical to measuring low currents. The activity covered by this paper is the low noise opamp design.
The process used for this project is AMIs 1.5 um CMOS technology (SCN15). The threshold voltage of the n channel transistors is 0.6 V and the p channel transistors is -0.9 V, K’nmos=(μnCo)/2=36.3uA/V2, K’pmos=(μpCo)/2=-12.3uA/V2, Sheet resistance, poly: 25 Ohms/Square, N well: 1638 Ohms/Square. Technology Data can be found at:
The general design requirements for the opamp design for this project were as follows: Supply +/-2.5V, Power Dissipation as low as reasonable, >80dB gain throughout the amplifier output voltage swing, output voltage swing of +/- 1.5V, Phase Margin >60o, CM voltage range of 3.5V, CMRR and PSRR as high as possible, input referred noise voltage as low as possible.
A large number of alternatives were reviewed for the low noise opamp design. The typical two stage opamp with active loaded input differential pair was considered. It was not pursued because of the noise contribution of the active loads on the inputs, and the requirement of having to compensate the second stage. The OTA type of opamp architecture, shown in Figure 11., was also considered. This opamp also has the draw back of noise contribution from the diode connected transistor loads on the inputs, and the low gain of the differential input stage. Telescopic opamps were also considered [17] along with gain boosting [18]. For the integrating converter application, it is beneficial to have as large a voltage swing as possible, which the telescopic opamp does not afford. Gain boosting may be an option for the future, and may be investigated for further improvements in the future.
[pic] [pic]
Figure 18. Left – Schematic of CMOS opamp using lateral PNP transistors [19]. Right- Layout of the lateral bipolar PNP input transistor [19].
Using lateral bipolar transistors was investigated and discounted for this initial development. The reasons were the low beta causes high base currents for a given emitter current. This high current increases the base thermal noise significantly. Lateral bipolar devices have higher 1/f noise because of the surface states. The final reason is no device models existed for the process that was being used. Reference [19] shows an opamp that was developed in CMOS with lateral PNP devices (Figure 18.).
[pic]
Figure 19. Top – the chopper amplifier principal [16]. Bottom – Waveforms appearing along the chopper amplifier for a DC input and an amplifier bandwidth limited to twice the chopper frequency [16].
Chopper stabilized opamps were also investigated. The amplifier is sampled at a clock frequency and the analog input is amplified at each stage and moved along to the next stage. The chopper amplifier is really a form of correlated double sampling. The major advantage for low noise current measurement applications, is the 1/f noise spectrum is translated up in frequency, out of the frequency range of measurement interest. Figure 19. illustrates the chopper amplifier concept. For the initial designs for this project it was decided not use this amplifier approach because of its design complexity, but it may be employed in future designs. Crystal Semiconductor disclosed a chopper stabilized opamp with 150dB gain [20]. Its circuit architecture is shown in Figure 20.
[pic]
a.)
[pic]
b.)
Figure 20. Crystal Semiconductors Chopper Stabilized Opamp [20]. a.) Top level architecture b.) Amplifier input stage simplified schematic.
Self Biased Folded Cascode Operational Amplifier
For the first operational amplifier design, a folded cascode architecture was selected. The reasons for this choice is as follows: High gain in a single stage that is capacitive load compensated, maximum of 4 series transistors between supplies allowing low supply voltage operation, reasonably good common mode input voltage range and output voltage swing.
A representative survey of these types of opamps can be found in references [21]-[25]. Most of these opamps provide for rail to rail input common mode voltage swings by having both p and n channel transistors at the inputs. For our low noise application, it was elected to settle for a reduced common mode range with respect to Vcc, and eliminate the higher noise n channel transistors on the input, to improve the noise performance of the opamp.
One of the problematic areas in folded cascade opamps, is the bias circuitry. A circuit must be developed that keeps all amplifier transistors biased in saturation over supply voltage and process. This separate circuit usually uses a significant percentage of the total opamp current. This wasted current could be better put to use in increasing the gain or the bandwidth of the actual opamp.
For the folded cascode opamp designed for this project, a new and advanced self biased architecture was developed. This circuit approach not only eliminates the current overhead of a separate bias circuit, but also improves process and supply tracking, and adds a small amount of extra common mode input range, through a weak common mode feedback. Previous work on self biased folded cascode opamps can be found in references [26]-[28]. For this design, the work by Song, et al [26] has the closest in resemblance. Circuit ideas utilized were also from Gregorian [29], and Allen [30].
[pic]
Figure 21. Cadence schematic with device sizes and values for the self biased folded cascode opamp (selfbfcascode).
The Cadence schematic, for the first opamp design is shown in Figure 21. Considerable time was invested in developing an analytical expression for setting the bias point of this circuit in terms of devices sizes and values for R1, R2, R3, N1, N2, P2, P3, and P6. Upon inspection of the circuit, we can make observations and assumptions to write an expression. The first assumption is that all transistors are in saturation. Given this assumption, a second assumption can be made, that the current through P3, and N1, acting as the dominant current sources in the resistor stacked circuit, set the current. P6 and N2 serve to drop the drain voltage of P3 and N1, and establish a tracking bias voltage for output cascode transistors P5 and N3. The amount of voltage the drains of P3 and N1 are drooped below their respective Vgs, is set by the values of R1 and R3. Since P6, and N2 merely drop the drain voltages, P3 and N1 can be viewed as diode connected. Furthermore, the current from diff. pair current source, P2, can be view as sourcing half its current into the drain of N1, when vplus equals vminus. This current forces higher the drain and gate - source voltage on N1 to reach a bias point that accommodates it. This, in turn, reduces by a proportional amount the Vgs on P3, which in turn reduces the output current through output transistor P4. This reduction in current is in an amount equal to the amount of current that is sourced into the drain N4 by P2, to maintain the output vout at 0V. The assumption is that P3 - P4, and N1 – N4 are matched is size to each other.
Applying Kirchoff’s voltage law, we can write:
Vdd=I(R1+R2+R3)+(I/Kp)1/2 +Vtp + (NI/Kn)1/2 + Vtn (20)
Where Kn and Kp represent the DC transconductance, including device sizes, for the p and n channel transistors, N1 and P3, for this process. The multiplier N is determined by the size of P2 relative to P3. For the circuit designed, P2 is the identical size to P3, so an identical current, I, flows through both P2 and P3. Half the current from P2 flows through each side of the diff. pair and through N1. This gives a multiplier N of 3/2 for this design. If Rt=(R1+R2+R3), then:
[pic] (21)
Solving for I, with help from Mathcad, the following equation results: I= (22)
[pic]
No simplification through the elimination of terms that are small or not strongly affecting the result is obvious. A further simplification was attempted through the assumption Kp=Kn=K, and Vtp=Vtn=Vt. Giving the following equation:
[pic] (23)
Again applying Mathcad, yields the following equation: I= (24)
[pic]
Although, this equation is quite involved, we can look at it to validate some qualitative observations about the circuit. First of all, we can see that the variable that has the strongest influence on setting the current is Rt, the total resistance. It appears as a squared term in the denominator, and divides all terms in the square brackets. The term K is the weakest, dividing out in all but one term, where it has a square root dependency. Vt and Vdd appear in alternate terms, and have a direct or square root influence on the terms where they appear.
If the amplifier biasing is viewed qualitatively, it follows the characteristics described by equation (24). Rt effectively sets the current, with significant voltage dropped across it. Diode connected N1 and P3 have a drop across them of Vt + ∆V, where delta V is set by the current. It can be seen that this is a supply dependent bias scheme, where bias voltages for the transistors increase and decrease with the supply voltage, but are desensitized by Rt. The effect of the size and current ratio between P2 and P3 can also be evaluated. If P2 is small relative to P3, the current sourced into N1 and N4 will be small relative to their bias currents. The amplifier will bias up correctly, but the output voltage swing will be limited to less than rail to rail, and the small signal gain will also be small. If P2 is large relative to P3, we can see that, in the limit, as the current flowing into N1 becomes very large, the current flowing through, and the voltage across P3 gets very small, forcing it effectively off. The bias voltage across P3 is the Vgs voltage applied to P2, which will intern will also force P2 effectively off. Therefore, in the limit, as P2 becomes much larger than P3, the amplifier will not bias up properly.
This shows that the size of P2 and P3 needs to be maintained close in size to achieve proper bias of all the transistor is the amplifier, and to get rail to rail voltage swings at the output. An alternate way of looking at this is as a positive feedback loop. If the loop has a gain less than 1, the output of the loop will track the input. If the gain of the loop is greater than 1, the loop will “latch” to one extreme value or another. The ratio of P2 to P3 is the strongest variable determining the gain of the loop. Gain increases as P2 gets larger relative to P3. If we assume the other components in the path have unity gain (Kp=Kn), this would give an upper limit for the ratio of P2 to P3 of 2:1.
Another secondary function of the self bias circuitry, is to provide an extension to the common mode input voltage range of the opamp, extending the top end of the range by a small amount. This happens when the p channel input transistors, P0 and P1, begin to shut off from the reduced Vgs provided by the higher input voltage. As they begin to shut off, the current sourced into the drain of N1 reduces. This reduction in current increases the voltage across P3. This, in turn, increases the Vgs on P2, reducing the drain to source voltage drop across this transistor. This reduction in voltage drop increases the Vgs on transistors P0 and P1, keeping them turned on to a higher input voltage on vplus and vminus.
[pic] Figure 22. Cadence schematic with node voltages and device currents for the
self biased folded cascode opamp. IP2=83.4uA, and IP3=IP4=82.0uA, Vcc=2.5V,
nominal process and temperature.
Figure 23. shows the test fixture developed for the AC simulations. Systematic offsets in the opamp circuit design are cancelled by the feedback circuit which functions as follow: A very low pass filter consisting of a 1G ohm resistor and 1mF capacitor (values like these can be realized in simulation land) feeds back to the inverting input the DC voltage developed on the opamp output when both inputs are 0V. The output of the filter is buffered by an ideal differential voltage controlled voltage source (voltage opamp). The voltage developed on the negative terminal adjusts the opamp output voltage until effectively zero volts in achieved. The voltage that appears on the negative terminal of the opamp during DC circuit simulations, is the systematic input refer offset of the opamp.
[pic]
Figure 23. actest1a - AC test fixture with offset cancellation used for most of the AC simulations.
The AC small signal voltage gain, Av, for the self biased folded cascode opamp can be expressed as follow:
Av=gmP0*(roP0||r0N4)*roN3*gmN3||roP4*roP6*gmP6 (25)
Where gm is the small signal transconductance, and ro is the small signal output resistance for the indicated transistors. Figure 24. shows the small signal gain and phase for this opamp at different process corners. This opamp configuration is compensated by the output capacitive load which is shown by Figure 25.
[pic]
Figure 24. Gain/Phase simulations of selfbfcascode opamp using testbench actest1a. Overlaid plots of 7 corners: Nominal, 27oC (Vcc=2V, 2.5V,3V); Nominal, 27oC (R=+30%,-30%); Slow, 125oC; Fast -15oC. Cload=35pF, PM≈60o
[pic] Figure 25. Gain/Phase simulations of selfbfcascode opamp using testbench
actest1a. Overlaid plots of 3 capacitive output loads: C=25pF (PM=49o), C=35pF (PM=60o), and C=45pF (PM=72o). Nominal process, 27oC, Vcc=2.5V.
Nominal conditions are used in this simulation, and the output capacitive load changed is changed 3:1 from 15pF to 45pF. The self biased cascode opamp for this project was designed to drive a load of 30pF, to allow for a large integration capacitor, to be able to drive further circuitry on chip, and to be able to drive off chip for characterization and testing.
AC gain and phase margin vs. common mode DC input voltage, were simulated using the Figure 23 test bench. This was accomplished by changing the sign of the DC voltage value in voltage source V7. Successive simulations were run and are shown in Figure 26.
[pic] Figure 26. Gain/Phase simulations of selfbfcascode opamp using testbench
actest1a. Overlaid plots for 6 common mode input voltages: Vcm=-2.5V,-2.0V,
-1.0V, 0V, 1V, 1.5V. Nominal process, 27oC, Vcc=2.5V, Cload=35pF, PM=60o.
Since the primary end application for this opamp is in a low current integrator, the requirement was set for an output voltage swing of +/-1.5V. When the output voltage changes on this opamp, the operating point on the I/V curve of P3-P6, and N1-N4 also changes. This change in operating point changes the small signal output resistance, ro, for these transistors, which in turn affects the small signal opamp gain, Av , expressed by equation 25. In the limit, one of the transistors in the cascoded P or N output goes out of saturation, and the gain falls off substantially.
[pic]Figure 27. Gain/Phase simulations of selfbfcascode opamp using testbench actest1a. Simulation of Gain and DC output voltage for 8 inputs from -100uV to +100uV differential. Nominal process, 27oC, Vcc=2.5V, Cload=35pF, PM=60o.
This change in gain and phase vs. output voltage, was simulated for this opamp using the test bench in Figure 23, with the offset cancellation low pass filter disconnected, and the simulation library opamp inputs both connected to gnd (0V). Differential voltages from -100uV to +100uV were introduced at the inputs of the opamp through the voltage sources. The results of the successive Cadence AC simulations are shown in Figure 27. The gain at both +/-1.5V at the output is 88dB, while a phase margin of 60o is maintained.
[pic] Figure 28. Input referred noise voltage for selfbfcascode opamp using test
bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11,
Nominal process, 27oC, Vcc=2.5V, Cload=35pF, PM=60o.
Figures 28. and 29. show the input referred noise spectrum for the self biased folded cascode opamp. MOS transistors for this technology, have 3 primary noise sources: thermal gate noise, thermal channel noise, and 1/f noise. Thermal noise from gate resistance can be made negligible with proper layout [31]. The relationship for channel thermal noise for the process used is as follows:
Veq2 =4kT((2/3)/gm)∆f, where k is the Boltzman Constant. (26)
The relationship for 1/f noise for the process used is as follows:
Veq2 =(Kf /C0ZL)(1/f )∆f , where Kf is the flicker noise coefficient for either p or n channel transistors. (27)
[pic] Figure 29. Input referred noise voltage squared for selfbfcascode opamp using
testbench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=35pF, PM=60o.
Referring back to Figure 21, each of the transistors in the opamp can viewed as having channel thermal noise, and 1/f noise. The noise sources can be modeled as a voltage source in series with the gate of each transistor. Looking at the circuit topology,
We can identify which transistor noise sources are significant, and which ones we can neglect. The input transistors P0, and P1 have the most significant effect [29]. P2 has minimal effect because it is common mode. P5, P6, and N2, N3, are all in a common gate (cascode) configuration in the circuit. Any noise on the gate of these transistors will undergo minimal amplification, and so can be ignored. The bias resistors, similarly, have no gain and also can be ignored. P3, P4, and N1, N4 are in a common source configuration, and therefore provide gain to noise on their gates. Recall equation, 25. It can be rewritten as
Av=gmP0* Ra, Ra=(roP0||r0N4)*roN3*gmN3||roP4*roP6*gmP6 (28)
Each of these transistors effectively sees a load of Ra on its drain, giving a gain of gmxRa for each. The significant noise sources from all these transistors can be summed, and divided by the input gain to compute a total input referred noise voltage. Since each of these voltage sources is a random variable a sum of squares must be used. The equation is as follows:
v2total= v2P0+v2P1+(gmp3Ra vP3 /gmP0Ra)2+(gmp4RavP4 /gmP1Ra)2+
(gmN1RavN1 /gmP0Ra)2+(gmn4RavN4 /gmP1Ra)2 (29)
Simplifying:
v2total= v2P0+v2P1+(gmP3vP3 /gmP0)2+(gmP4vP4 /gmP1)2+(gmN1vN1 /gmP0)2+(gmn4vN4 /gmP1)2 (30)
Simplifying further for the design under analysis, where ID is the same for all transistors, and device sizes are equal for N1, N4, and P3, P4, and P0, P1:
v2total= 2v2P1+2((Z/L)P3 /(Z/L)P1))v2P3 +2(μn(Z/L)N1 / μp(Z/L)P1))v2N1 (31)
Substituting values for the particular device sizes, and assuming, μn≈3μp:
v2total= 2v2P1+(3/2)v2P3 +(3/2)v2N1 (32)
Substituting equation (26) into (32) we get and expression for the total input referred thermal noise:
VeqT2 =4kT[(4/3)/gmP1 + 1/ gmP3 + 1/ gmN1]∆f (33)
Substituting equation (27) into (32) we get and expression for the total input referred 1/f noise:
Veq1/f2 =[(KfP/6000u2C0) + (KfP/6000u2C0) + (3KfN/6000u2C0)] (1/f )∆f (34)
Veq1/f2 = (1/6000u2C0) (2KfP+3KfN) (1/f )∆f (35)
Combining (33) and (35) an expression is obtained for the total input referred noise for the self biased cascode opamp.
v2total={4kT[(4/3)/gmP1)+1/gmP3+1/gmN1]+[(2KfP+3KfN)/6000u2C0](1/f )}∆f (36)
Examining equation 30, gmP0,1, the small signal transconductance of the differential input transistors, has the strongest influence on the input referred noise of the opamp. Increasing the W/L ratio of the input transistors, or the current through these transistors will improve the noise performance of the opamp. One area that could be investigated further to improve the self bias cascode noise performance is increasing the W/L ratio of these transistors. Examining equation 34, the 1/f noise can be improved by increasing the gate area, W*L, of any of any of the key noise transistors.
Returning to equation 32, this equation illustrates one of the primary disadvantages to the folded cascode opamp architecture for low noise applications. Besides the noise from the differential input transistors, the noise from 4 additional transistors appears at the input to the opamp [32]. This contrasts to the differential pair with active load having the noise from 2 additional transistors appear at the input, or the resistor loaded differential stage, where only the resistor thermal noise divided by the gain appears at the input. Another drawback cited for using this opamp architecture for low noise, is the wide bandwidth it has for a given gain.
Referring back to Figure 29, the total integrated input referred RMS noise voltage can be calculated [33].
v2itrms= v2thermalfloor[(f2-f1)+fcornerln(f2/f1) (37) f2 is the amplifier noise bandwidth(1.57*3dB Bandwidth), f1 is 1/(maximum observation time), fcorner is the 1/f noise corner, v2thermalfloor is the magnitude of the thermal noise at and above the noise corner frequency. Substituting values from Figure 29:
v2itrms=(10)-16[(314Hz-1Hz)+10MHz*ln(314Hz/1Hz)] (38)
vitrms=100uV
The relationship for input referred offset can also be derived. Referring back to Figure 21., current Iss is supplied by current source transistor P2. If P0 and P1 are identically matched, they have current as follows [34]:
Iss=Id1+Id2 (39)
Id1=(Iss/2){1+[(βV2id/ Iss)- (β2V4id/4I2ss)]1/2} (40)
Id2=(Iss/2){1-[(βV2id/ Iss)- (β2V4id/4I2ss)]1/2} (41)
Where β=μC0Z/2L. We can use these expressions to calculate the input referred offset voltage when there is a mismatch in the β of the input differential transistors, P0, P1. For the offset to be canceled, the second terms in (40) and (41) must be equal. In (40) and (41) an offset, ∆, can be introduced and the following equations written:
[(βV2id/ Iss)- (β2V4id/4I2ss)]1/2 = [(∆βV2id/ Iss)- (∆2β2V4id/4I2ss)]1/2 (42)
Solving for Vid
[(∆2-1)/ (∆-1)] (β2V4id/4I2ss)=βV2id/ Iss (43)
Vid =2[Iss/β(∆+1)]1/2 (44)
If there is a mismatch in the drain current of P0 and P1, for instance, because of a mismatch in current source transistors N1 and N4, the following equation for the offset can be derived:
Vid =Vgs1-Vgs2=(2Id1/β)1/2 - (2Id2/β)1/2 (45)
Vid =(2Id1/β)1/2 - (2∆Id1/β)1/2 (46)
Vid =(Iss/β)1/2 (1-√∆) (47)
From equations (44) and (47) it can be seen the main circuit parameters that can influence offsets. The larger the Z/L ratio of the differential input transistors, the lower the input referred offset. As the current of the input differential pair is increased, the input referred offset is increased for a given device or current mismatch. Furthermore, it can be seen that the input offset is more sensitive to the device matching of the input transistors, than the current matching at the drains of the input transistors. This is because in the second scenario we have available the current gain of the input transistors to cancel the offset, as opposed to seeing the offset directly at the input to the amplifier.
The simulated systematic input referred offset for the self biased folded cascode opamp, using the test bench in Figure 23, was 470nV, for nominal process, voltage, and temperature. Equation 44 shows that the opamp is most sensitive to input device matching. To get a feel for this sensitivity a simulation was performed, where the input devices, P0 and P1, were mismatched by 5% in width. The result of the simulation, again using nominal conditions, showed an input referred offset of 10.2mV. In practice, such a large mismatch in identically sized, large geometry, devices would never exist. Further steps that will be used to minimize mismatch in the layout is to lay the devices out in the same orientation, same number of fingers, common centroid layout - where equal numbers of fingers of each device are laid out in 2 or 4 sections and cross connected – and use of dummy transistors at the edges.
Common mode rejection ratio (CMRR), and power supply rejection ratio (PSRR) were also simulated with matched, and 5% mismatched input devices. Figures 30 and 31 show
[pic] Figure 30. CMRR reference curve simulations of selfbfcascode opamp using
testbench actest1a. Top Curve: Differential AC Gain; Middle Curve: Common
mode AC gain with input transistor gross mismatch of 5%; Bottom Curve:
Common mode AC gain with input transistors matched. CMRR=85dB@1Hz,
130dB@100KHz for mismatched, CMRR=125dB@1Hz, 140dB@100KHz
Nominal process, 27oC, Vdd=2.5V.
[pic] a.)
[pic] b.)
Figure 31. PSRR reference curve simulations of selfbfcascode opamp. Test bench
similar to actest1a. Nominal process, 27oC, Vcc=2.5V. a.) AC gain of Vss Top Curve:
Input transistors matched. Bottom Curve: Input transistor gross mismatched by 5%.
PSRRVss=91dB@1Hz, 130dB@10KHz for matched, PSRRVss=95dB@1Hz, 95dB@10KHz for
mismatched. b.) AC gain of Vcc Top Curve: Input transistors matched. Bottom Curve:
Input transistor gross mismatched by 5%. PSRRVcc=100dB@1Hz, 150dB@100KHz for
matched, PSRRVcc=120dB@1Hz, 120dB@10KHz for mismatched.
[pic]
Figure 32. trantest1 – Test bench used for transient simulations.
the results of these simulations. For the CMRR simulation, the test bench in Figure 23. was used. The polarity was reversed of one the AC input voltage sources to make it common mode. A test bench similar to Figure 23 was used for PSRR, where the Vcc and Vss, voltage sources were alternately made both DC and AC sources. CMRR was shown to be a minimum of 85dB with extreme mismatches that would never be encounter on chip, PSRR wrt Vss was minimum of 91dB, and PSRR wrt Vcc was minimum of 100dB.
Transient simulations were performed for the self biased cascode opamp using the test bench in Figure 32. The opamp was connected in voltage follower configuration, and a transient pulse train applied with 1us rise and fall times. The simulations show no over shoot – consistent with the AC simulations showing a 60o phase margin. Figures 33 and 34 show the results of the transient simulations.
[pic] Figure 33. Transient simulation of selfbfcascode opamp using trantest1
test bench. +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC,
Vcc=2.5V.
[pic] a.)
[pic] b.)
Figure 34. Transient simulation close-ups from Figure 33. a.)High to Low input/output b.)Low to High input/output
[pic]
Figure 35. Cadence schematic with device sizes and values for the low noise self biased folded cascode opamp (lnselfbfcascode).
Low Noise Self Bias Folded Cascode Operational Amplifier
The self biased folded cascode opamp, as previously pointed out by equation 32, has the drawback of having significant input referred noise contributions from 6 transistors. The lowest noise configuration (as well as the lowest input offset) for a differential amplifier is to use resistor loads. A second opamp was developed that employed this type of input as a first stage, and used the self biased folded cascode opamp as the second stage. Figure 35. shows the cadence schematic for this amplifier. P0, P1, P2, and R1, R2 form the input differential amplifier. P20-P24, and N20-N23 form an active loaded differential amplifier, used to miller effect multiply capacitors C1 and C2 to compensate the input stage. P3, P10, R10, and N12 form as supply dependent
[pic]
Figure 36. Cadence schematic with device sizes and node voltages for the input diff. pair, input compensation, and bias section of the low noise self biased folded cascode opamp. IP24=216uA, and IP3=105uA, IP2=212uA. Nominal process, temperature, and Vcc=2.5V.
biasing circuit that replicates elements of both the input differential pair, and the compensation amplifier. The voltage drops across the diode connected transistors in this circuit track with process and supply variations to keep all the amplifier transistors biased in saturation. The differential input stage does not require any type of common mode feedback. Both circuits it outputs to - the compensation amplifier and the self biased folded cascode opamp – have their own internal common mode feedback.
Figure 37. shows the schematic for the self biased folded cascode opamp to be used as the second gain stage. It is identical in topology, device sizes and values to the first opamp circuit reviewed (Figure 21.), with the one addition of p channel transistor
P20. This transistor is used as a capacitor to compensate this amplifier for use as a
[pic]
Figure 37. Cadence schematic with device sizes and node voltages and for the
self biased folded cascode opamp with compensation (selfbfcascodecmp).
This is the output of lnselfbfcascode. This opamp is identical to selfbfcascode in Figure 21, with the addition of P20 (100u/20u*60) for a comp. cap. IP2=83.4uA, and IP3=IP4=82.0uA, nominal process and temperature, Vcc=2.5V.
.
second gain stage in the new opamp.
The gain for the new amplifier can be expressed as the gain of the resistive loaded differential pair times the gain of the self biased folded cascoded opamp, expressed in equation (25). The relationship is as follows:
Av=gmP0LNR{gmP0*[(roP0||r0N4)*roN3*gmN3||roP4*roP6*gmP6]} (48)
Figures 38.-40. show the gain/phase plots for this opamp at different process corners and simulation conditions. Compensation for this amplifier is considerably different than the miller effect pole splitting approach used in most opamps [33]. Unlike most operational amplifiers,
[pic]
Figure 38. Gain/Phase simulations of lnselfbfcascode opamp using testbench actest1a. Overlaid plots of 7 corners: Nominal, 27oC (Vcc=2V, 2.5V, 3V); Nominal, 27oC (R=+30%,-30%); Slow, 125oC; Fast -15oC. Cload=30pF, PM≈75o
the input stage used does not perform a differential to single ended conversion, so both sides of the amplifier need to be compensated. There is no symmetric point to connect two pole splitting capacitors on each side of the input stage, so the input and output stages have to be compensated independently. This means that the output pole, of which the dominant component is the load capacitance, is not pushed up in frequency.
The input stage is compensated by adding capacitance at the resistor loaded outputs. If passive grounded capacitors were used, the values required would be extremely large. A dedicated active loaded differential amplifier is added to each side to
[pic]
Figure 39. Gain/Phase simulations of lnselfbfcascode opamp using testbench
actest1a. Overlaid plots of 3 capacitive output loads: C=10pF (PM=80o), C=30pF (PM=75o), and C=50pF (PM=70o). Nominal process, 27oC, Vcc=2.5V.
use the miller effect to multiply the capacitors, and drastically decrease the values required. The small signal gain for this miller effect amplifier can be written as:
Avcmp=gmP20roN20||roP20 or Avcmp=gmP22roN22||roP22 (49)
This gives a pole for the input stage of
P1=1/R AvcmpC1 or P1=1/R AvcmpC2 (50)
The output stage pole is formed by the parallel combination of the opamp output impedance from equation (28) and the load capacitance.
P2=1/CloadRa Ra=(roP0||r0N4)*roN3*gmN3||roP4*roP6*gmP6 (51)
[pic]
Figure 40. Gain/Phase simulations of lnselfbfcascode opamp using testbench
actest1a. Overlaid plots for 6 common mode input voltages: Vcm=-2.25V,-2.0V,
-1.0V, 0V, 1V, 1.5V. Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=75o.
Simulations showed the unity gain bandwidth for the self biased folded cascode opamp to be 4.4MHz. This gives it a bandwidth larger than the compensated input stage. An issue with the output stage, that affects the opamp stability, is the existence of an AC path from vinvplus to vout and vinvminus to vout. This ac path forms a zero that degrades the phase margin at high frequency. The expression for these zeros is as follows:
Zvinvplus=gmP0/CgdP0 (51) Zvinvminus=(gmP0/CgdP0)||(1/CgdN3) (52)
A compensation capacitor needs to be added to the cascode transistor bias node to negate the effect of the zero. The effective capacitance that appears on node vbias becomes:
Cceff=CP20gmP4Ra where Ra=(roP0||r0N4)*roN3*gmN3||roP4*roP6*gmP6 (53)
This creates a new pole on the vbias node of :
Pvbias=[(1/gmP3)+(1/gmP5)]||[R1+R2+R3+(1/gmN2)+(1/gmN1)]Cceff (54)
Reference [35] shows an opamp with similar compensation problems to this one, and the solutions that were developed for it.
Figure 41. shows the AC gain of the opamp vs. the output voltage. The gain is maintained at 100dB from +1.5V to -1.5V.
[pic]
Figure 41. Gain/Phase simulations of lnselfbfcascode opamp using testbench actest1a. Simulation of Gain and DC output voltage for 6 inputs from -4uV to +5uV differential. Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=75o.
[pic]
Figure 42. Input referred noise voltage for lnselfbfcascode opamp - test bench
actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal
process, 27oC, Vcc=2.5V, Cload=30pF, PM=75o.
Figures 42. and 43. show the input referred noise spectrum for the lnselfbfcascode opamp. The resistively loaded input should significantly reduce the input referred noise. The only noise contributors in this first stage, are the 2 input transistors and the 2 resistors. The noise of this stage, again summing random variables, can be written as:
v2total= v2P0LN+v2P1LN+(vR1/gmP0LNR1)2+(vR1/gmP1LNR2)2 (55)
[pic]
Figure 43. Input referred noise voltage squared for lnselfbfcascode opamp using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=75o.
Combining the above equation with equation (29), the following relationship results:
v2total=v2P0LN+v2P1LN+(vR1/gmP0LNR1)2+(vR1/gmP1LNR2)2+(vP0/gmP1LNR2)2+(vP1/gmP0LNR1)2+
(gmp3RavP3 /gmP1LNR2gmP0Ra)2+(gmp4RavP4 / gmP0LNR1 gmP1Ra)2
+(gmN1RavN1/gmP1LNR2gmP0Ra)2+(gmn4RavN4 /gmP0LNR1 gmP1Ra)2 (56)
Simplifying, noting device sizes are equal for P0LN, P1LN; N1, N4; P3, P4; and P0, P1:
v2total=2v2P0LN+2(vR1/gmP0LNR1)2+2(vP0/gmP0LNR1)2+2(gmp3vP3 /gmP0LNR1gmP0)2+ 2(gmN1vN1/gmP0LNR1gmP0)2 (57)
Simplifying further for the design under analysis, where ID is the same for transistors, N1, N4, and P3, P4, and P0, P1, and IDLN=nID, where n=1.3 for this design:
v2total= 2v2P0LN +(1/g2mP0LNR12) [2vR12+2v2P0+2((Z/L)P3 /(Z/L)P1))v2P3 +
2(μn(Z/L)N1 / μp(Z/L)P1))v2N1 ] (58)
Substituting values for the particular device sizes, and assuming, μn≈3μp:
v2total= 2v2P0LN +(1/g2mP0LNR12) [2vR12+2v2P0+(3/2)v2P3 +(3/2)v2N1] (59)
Substituting equation (26) into (59) we get and expression for the total input referred thermal noise:
VeqT2 =4kT{(4/3)/gmP0LN+(1/g2mP0LNR1)+(1/g2mP0LNR12)[(4/3)/gmP1+1/ gmP3+1/ gmN1]}∆f (60)
Substituting equation (27) into (59) we get and expression for the total input referred 1/f noise:
Veq1/f2 = (KfP/20000u2C0) (1/g2mP0LNR12) [(2KfP+3KfN)/6000u2C0](1/f )∆f (61)
As a note, the 1/f noise for the resistors can be neglected since the voltage across them (~1V) is so low [36],[37].
Combining (60) and (61) an expression is obtained for the total input referred noise for the low noise self biased cascode opamp.
v2total=[4kT{(4/3/gmP0LN)+(1/g2mP0LNR1)+(1/g2mP0LNR12)[(4/3)/gmP1+1/ gmP3+1/ gmN1]}+ (KfP/20000u2C0) (1/g2mP0LNR12) [(2KfP+3KfN)/6000u2C0](1/f)]∆f (62)
Examining equation 62, it can be seen that the gain of the input stage drastically reduces the influence of the circuits following by a factor of 1/g2mP0LNR12. If the gain of the input stage is moderate, Equation (62) can then be accurately approximated as:
v2total={4kT[(4/3/gmP0LN)+(1/g2mP0LNR1)]+(KfP/20000u2C0)(1/f)}∆f (63)
As was discovered before, the signal transconductance of the differential input transistors has the strongest influence on the input referred noise of the opamp. Increasing the W/L ratio of the input transistors, or the current through these transistors will improve the noise performance of the opamp. Also, increasing input device area improves the 1/f noise. It can be seen from equation (63) that only the noise of the 2 input transistors appears in any significance at the input. This contrasts with the previous opamp, where the noise of 6 transistors contributed. Since a differential amplifier can’t be built without 2 transistors, this opamp architecture is at the minimum.
Referring back to equation (37), the total integrated input referred RMS noise voltage can be calculated.
v2itrms=(10)-16[(160Hz-1Hz)+100KHz*ln(160Hz/1Hz)] (64)
vitrms=7.125uV
The input referred offset from device and drain current mismatches, can again be calculated employing the same analysis as was shown in Equations (39)-(47). The simulated systematic input referred offset for the lnselfbfcascode opamp, using the test bench in Figure 23, was 278nV, for nominal process, voltage, and temperature. This shows the improvement expected over the previous opamp design.
[pic]
Figure 44. CMRR reference curve simulations of lnselfbfcascode opamp using test bench actest1a. Top Curve: Differential AC Gain; Middle Curve: Common
mode AC gain with input transistor gross mismatch of 5%; Bottom Curve: Common mode AC gain with input transistors matched. CMRR=86dB@1Hz,
116dB@10KHz for mismatched, CMRR=170dB@1Hz, 200dB@10KHz for matched
Nominal process, 27oC, Vcc=2.5V.
[pic]
a.)
[pic]
b.) Figure 45. PSRR reference curve simulations of lnselfbfcascode opamp. Test bench similar to actest1a. Nominal process, 27oC, Vcc=2.5V. a.) AC gain of Vcc. Top Curve: Input transistors matched. Bottom Curve: Input transistor gross mismatched by 5%. PSRRVcc=156dB@1Hz, 120dB@100KHz for matched, PSRRVcc=118dB@1Hz, 116dB@100KHz for mismatched. b.) AC gain of Vss. Top Curve: Input transistors matched. Bottom Curve: Input transistor gross mismatched by 5%. PSRRVss=112dB@1Hz, 140dB@100KHz for matched, PSRRVss=116dB@1Hz, 116dB@10KHz for mismatched.
Common Mode Rejection Ratio, and Power Supply Rejection Ratio, was simulated for this opamp using the same methodology and test benches that were used for the previous design.
Simulations were done for both matched and 5% gross mismatched input devices. Results are shown in Figure 44. and Figure 45. a. and b.
Transient simulations were run using the same test bench and methodology as previously done for the selfbfcascode opamp. Results are shown in Figure 46. and Figure 47. a. and b. The internal nodes between the input differential pair and the output stage are also displayed on these simulations. The results show the transient behavior expected for a 75o phase margin, with no ringing.
[pic]
Figure 46. Transient simulation of lnselfbfcascode opamp using trantest1 test bench. +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC, Vcc=2.5V. Includes internal nodes-vinvplus and vinvminus–output of diff. pair.
[pic] a.)
[pic] b.)
Figure 47. Transient simulation close-ups from Figure 46. Includes internal nodes - vinvplus and vinvminus – output of diff. pair. a.)High to Low input/output. b.)Low to High input/output.
[pic]
Figure 48. Cadence schematic with device sizes, values and node voltages for the high gain - low noise, opamp (hglnopaa). P31 and P26 are used as compensation capacitors with sizes of (100u/20u*24) and (100u/20u*38) respectively.
High Gain Low Noise Operational Amplifier
The low noise self biased folded cascode opamp showed considerable improvement in noise performance over the self biased folded cascode opamp. A third low noise opamp architecture was developed to further improve performance. Figure 48. shows the schematic for this new design, called the high gain low noise opamp (hglnopaa), and Figure 49 shows the currents associated with each circuit component. This opamp makes use of the resistive loaded differential stage as the input, while
[pic]
Figure 49. Cadence schematic with currents and node voltages and for the high gain - low noise opamp (hglnopaa). IP4=48uA, and IP2=187uA, IN10=19uA, IP6=IP7=111uA, IP51=67uA. Nominal process, 27oC, and Vcc=2.5V.
eliminating the p channel input transistors from the folded cascode output stage. Instead, this amplifier employs a complementary cascoded common source
output stage, which also performs a differential to single ended conversion. Since this opamp uses the resistive loaded differential input stage, both sides of the diff. pair output have to be compensated. This is accomplished with a miller effect multiplied pole splitting capacitor. This capacitor is connected from gate to drain on each of the n channel common source transistors that the 2 sides of the input differential pair drive.
[pic]
Figure 50. Gain/Phase simulations of hglnoppa opamp using testbench actest1a. Overlaid plots of 9 corners: Nominal (-25oC, 27oC, 125oC), Vcc=2.5V; Nominal, 27oC, (Vcc=2V, 2.5V, 3V); Nominal, 27oC, (R=+30%,-30%); Slow, 27oC, Vcc=2.5V; Fast, 27oC, Vcc=2.5V. Cload=30pF, PM≈90o.
Key to this opamp architecture functioning is the common mode feedback circuit formed by transistors N6, N7, N8, N9, N10, and P4. It is necessary to maintain the proper Vgs on transistors N1 and N4 to keep vout biased at its quiescent value of 0V. Vgs must remain constant with common mode input voltage, and vary proportionally with power supply voltage Vcc/Vss..
Figures 50., 51. and 52., show the AC gain phase plots for the hglnoppa amplifier under numerous operating conditions. The AC small signal gain for this amplifier can be expressed as:
Av=gmP0R[(gmN0+gmP7)*(roN0*roN3*gmN3||roP7*roP6*gmP6)] (65)
The new pole and zero locations created by compensation capacitors CP31 and CP26
can be approximately calculated.
[pic]
Figure 51. Gain/Phase simulations of hglnopaa opamp using testbench
actest1a. Overlaid plots of 3 capacitive output loads: C=10pF (PM=96o), C=30pF (PM=90o), and C=50pF (PM=84o). Nominal process, 27oC, Vcc=2.5V.
The new compensated pole that appears on node vinvminus can be calculated as:
Pvinvminus≈1/{RgmN1[(1/gmP6)+(1/gmP8)]CP31} (66)
Looking at the above equation, CP31 under goes miller effect multiplication, although the gain is not large. This node does not go to the output, however, so large gain is not necessary to push the output pole up in frequency.
There exits an AC path from vinvminus through CP31 in series with the gate drain capacitance of P7 to Vout. This can be approximated as:
Zvinvminus≈ (gmN1/CP31)||(1/CgdP7) (67)
Transistor P52 is in series with this AC path and is used to cancel this zero.
The new compensated pole that appears on node vinvplus can be calculated as:
Pvinvplus≈1/{RgmN0(roN0*roN3*gmN3||roP7*roP6*gmP6)CP26} (68)
[pic]
Figure 52. Gain/Phase simulations of hglnopaa opamp using test bench
actest1a. Overlaid plots for 6 common mode input voltages: Vcm=-2.5V,-2.0V,
-1.0V, 0V, 1V, 1.3V. Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=90o.
Compensation capacitor, CP26, is buffered from Vout with source follower transistor P50, and current source P51, to eliminate the zero. Minimum gate length is used on P50, to minimize the resistance and capacitance that is in series with CP26.
The new compensated output pole location can be approximated as:
P2≈(gmN0+gmP7)/Cload (69)
The pole is moved up in frequency by a factor of (gmN0+gmP7), a benefit of the pole splitting compensation.
Figure 53. shows the opamp gain vs. output voltage. The opamp has a maximum gain of 117dB and a minimum of 80dB gain over an output swing of +1.5V to -1.5V. This curve is less flat than the previous 2 opamps. This can be adjusted with device sizing. If P4 is sized narrower, this will increase the current in the diff. pair, and increase the drop on the load resistors. This, in turn, will increase the Vgs on N0 and N1, which will increase their currents. This will force the Vds on N0 and N1 lower, keeping the
[pic]
Figure 53. Gain/Phase simulations of hglnopaa opamp using test bench actest1a. Simulation of Gain and DC output voltage for 6 inputs from -10uV to +10uV differential. Nominal process, 27oC, Vcc=2.5V. Cload=30pF, PM=90o.
cascode transistors N3 and P9 (the mirror of N3) in saturation to voltages closer to Vcc and Vss. Simulations have been run that demonstrated this.
As mentioned previously, a key element to the design of this opamp is the common mode feedback circuit comprised of transistors N6, N7, N8, N9, N10, and P4.
Since the input differential stage is not actively loaded, an external common mode feedback circuit needs to be supplied. These circuits historically were used in nMOS opamps and examples can be found on P.194 of [26] and P.200 of [38]. These circuits are usually comprised of 2 source followers whose gates are connected to the outputs of the differential pair. The source follower output connects to a resistor or diode connected transistor that directly connects to the gate of the diff. pair current source transistor. This provides for a high speed feedback network, that has unity gain, and no phase shift. The problem with this circuit in this application is that with power supply variations, it keeps the wrong voltage constant. Referring to Figure 49. the use of this circuit would keep the voltage from vinvplus and vinvminus constant with respect to Vcc, when the power supply voltages are varies. This circuit topology requires that the voltage from vinvplus and vinvminus, be kept constant or proportional with respect to Vss. This maintains a constant Vgs for transistors N0 and N1, and maintains the proper bias for the output stage.
A totally new common mode feedback circuit needed to be designed for this amplifier architecture. Numerous references exist and were consulted to find a tractable solution that met the design requirements and constraints, including reasonable complexity and low power. Representative of these references are [39] – [43]. No “silver bullet” was found, however, and it was necessary to derive a new approach.
Referring back to Figure 48., transistors N7 and N8 form current sources that are connected together at their drains to sum their currents (reference [39] alludes to an approach similar to this). Each of the two current sources has a current proportional to the voltage between vinvplus or vinvminus and Vss. The summed output of the current sources provides a current that is proportional to the common mode input voltage of the input differential pair.
Transistor N6 provides a load to the current sources to derive and output voltage on node vcmfb. N6, since it is connected as a source follower, provides a relatively low impedance load, and limits the voltage gain of N7 and N8. Transistor N9 has its gate connected to vcmfb, creating a drain current that is proportional to vcmfb. P4 is a diode connected load on N9 and forms a current mirror with P2. Since N9 has a size of 25u/10u and P4s size is 500u/10u, this gives transistor N9 a voltage gain much less than unity.
[pic]
Figure 54. System level diagram for common mode feedback circuit for hglnopaa opamp.
Figure 54., shows a system level diagram of the common mode feedback circuit.
The circuit has an inversion from vinvplus/vinvminus to vcmfb; an inversion from vcmfb to vdiffbias, and a third inversion from vdiffbias back to vinvplus/vinvminus. This arrangement can form a three inverter ring oscillator. To keep from having oscillations two mitigation approaches were incorporated in the design. First, if the loop gain is held to less than unity, no oscillation can result. Second, source follower N10 effectively “shorts” across two of the inversions, from vdiffbias to vcmfb, introducing no phase shift, and having one inversion in the path. Introducing these two design approaches eliminates oscillation for the common mode feedback circuit.
Figure 55. shows a magnitude plot for the common mode feedback circuit using a test bench similar to actest1a in Figure 23, to make a simulation relative to the plus amplifier input. This plot shows the gain of the loop does not exceed unity, and the bandwidth of the loop is larger than the bandwidth of the differential input stage it is controlling.
One initial problem encountered under transient simulations, was a high frequency oscillation. Re-examining Figure 55., it was found that the circuit had a high frequency zero at approximately 7MHz, where the gain of the loop blipped up greater than one. This zero was cause by the high pass response of source follower N10. P channel transistor P44 was added as a capacitor to attenuate this zero. The overlaid plot in Figure 55., of the loop magnitude response with the capacitor added shows the zero effectively “squashed” with the new magnitude significantly below unity.
[pic]
Figure 55. Opamp hglnopaa common mode feedback loop magnitude response. Overlaid plots with and without capacitor CP44. Simulations using test bench similar to actest1a. Top blue curve - opamp gain response for reference. Second from top red curve – Differential input stage gain response. Third from top – vcommon gain response. Bottom curve - vcmfb gain response. Nominal process, 27oC, Vcc=2.5V.
[pic]
a.)
[pic]
b.)
Figure 56. Input referred noise voltage for hglnopaa opamp using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=90o. a.) noise voltage/√Hz. b.) noise voltage squared/Hz.
Figures 56a. and b. show the input referred noise spectrum for the hglnopaa opamp. The resistively loaded input should again significantly reduce the input referred noise. The noise of this stage is the same as Equation (55) with different device subscripts:
v2total1= v2P0+v2P1+(vR1/gmP0R1)2+(vR1/gmP1R2)2 (70)
Calculating the total input referred noise in steps, the input referred noise to transistors
N0 and N1, recalling equation (65), can be represented as:
v2total2= v2N0+v2N1+(gmp6RavP6 /gmN1Ra)2+(gmp7RavP7 /gmN0Ra)2 (71)
Where Ra=(roN0*roN3*gmN3||roP7*roP6*gmP6), a sub-term in Equation (65) (72)
Comparing Equation (71) to Equation (29), the expression for the input referred noise for the self biased folded cascode opamp, it can be seen that there are 2 fewer noise terms present in Equation (71).
Combining (70) and (71), the total input referred noise is:
v2total=v2P0+v2P1+(vR1/gmP0R1)2+(vR2/gmP1R2)2+(vN1/gmP1R2)2+(vN0/gmP0R1)2+
(gmp6vP6 /gmP1R2gmN1)2+(gmp7vP7 /gmP0R1gmN0)2 (73)
Simplifying, noting device sizes and currents are equal for P0, P1; N0, N1; and P6, P7:
v2total=2v2P0+2(vR1/gmP0R1)2+2(vN0/gmP0R1)2+2(gmp7vP7 / gmP0R1gmN0)2 (74)
Simplifying further for the design under analysis, where ID is the same for transistors, N0, N1, and P6, P7, and for P0, P1, current, IDLN=nID where n=0.84 for this design:
v2total= 2v2P0+(1/g2mP0R12) [2v2R1+2v2N0+2(μp(Z/L)P7/μn(Z/L)N0))v2P7 (75)
Substituting values for the particular device sizes, and assuming, μn≈3μp:
v2total= 2v2P0 +(1/g2mP0R12) [2v2R1+2v2N0+2(4/3)v2P7 ] (76)
Substituting equation (26) into (76) we get and expression for the total input referred thermal noise:
VeqT2 =4kT{(4/3)/gmP0+(1/g2mP0R1)+(1/g2mP0R12)[(4/3)/gmN0+(16/9)/gmP7]}∆f (77)
Substituting equation (27) into (76) we get and expression for the total input referred 1/f noise:
Veq1/f2 = (KfP/10000u2C0) (1/g2mP0R12) [(KfP+3KfN)/5625u2C0](1/f )∆f (78)
Combining (60) and (61) an expression is obtained for the total input referred noise for the high gain low noise opamp:
v2total=[4kT{(4/3)/gmP0+(1/g2mP0R1)+(1/g2mP0R12)[(4/3)/gmN0+(16/9)/gmP7]}+ (KfP/10000u2C0) (1/g2mP0R12) [(KfP+3KfN)/5625u2C0](1/f )]∆f (79)
Examining Equation (79), it can be seen that the gain of the input stage drastically reduces the influence of the circuits following by a factor of 1/g2mP0LNR12. Equation (79) is in fact very similar to equation (62) for the previously analyzed opamp. Again, If the gain of the input stage is significant, Equation (79) can then be accurately approximated as:
v2total={4kT[(4/3/gmP0)+(1/g2mP0R1)]+(KfP/10000u2C0)(1/f)}∆f (80)
This equation is similar Equation (63) and this amplifier will also have the same parameters dominate its performance.
Referring back to Equation (37), the total integrated input referred RMS noise voltage can be calculated.
v2itrms=2(10)-15[(160Hz-1Hz)+20KHz*ln(160Hz/1Hz)] (81)
vitrms=14uV
This result is worse than the result that was obtained for Equation (64)
for the lnselfbfcascode opamp. Revisiting Equation (80), and comparing to (63) for the previous opamp there is a factor of 10000, rather than 20000 in the denominator of the flicker noise term. To improve the noise performance a variation of hglnopaa was design that had 2000u/10u input devices. It was designated hglnopaa2. This makes the total noise equation identical to Equation (63).
Figures 57. a. and b. show the input noise spectrum for this design variant. Figure 58. shows the schematic for the circuit. The only things changed are the input devices, and the size of the compensation source follower was increased by 50% to improve the phase margin. Gain of the modified design is 120dB, with a phase margin of 65%, using identical compensation capacitors
[pic]
a.)
[pic]
b.)
Figure 57. Input referred noise voltage for hglnopaa2 opamp (W=2000u input transistor) using test bench actest1a. Kf =6(10)-27 (pMOS), Kf =3(10)-25 (nMOS), Model Level=11, Nominal process, 27oC, Vcc=2.5V, Cload=30pF, PM=90o. a.) noise voltage/√Hz. b.) noise voltage squared/Hz.
[pic]
Figure 58. Cadence schematic with device sizes and values for high gain - low noise, opamp with W for P0 and P1 input transistors increased to 2000u. (hglnopaa2). Compensation source follower sizes increased 50% to W=150u for P50 and W=300u for P51. Associated current increased from 67uA to 100uA. P31 and P26 compensation capacitor sizes remain the same at (100u/20u*24) and (100u/20u*38) respectively.
Figure 59. shows overlaid gain/phase plots for hglnopaa2 at different operating corners.
Again referring back to equation (37), the total integrated input referred RMS noise voltage can be calculated for hglnopaa2, using parameters from Figure 57. b.
v2itrms=8(10)-16[(80Hz-1Hz)+10KHz*ln(80Hz/1Hz)] (82)
vitrms=6uV
[pic]
Figure 59. Gain/Phase simulations of hglnoppa2 opamp using test bench actest1a. Overlaid plots of 9 corners: Nominal, 27oC, (Vcc=2V, 2.5V, 3V), (R=+30%,-30%); Slow, 125oC, Vcc=2.5V; Fast, -25oC, Vcc=2.5V. Cload=30pF, PM≈65o.
Further noise improvement could also be made by running more current through the input stage. The lnselfbfcascode opamp is using 217uA, while both hglnopaa and hglnopaa2 use 187uA.
Input referred offsets from input device and drain current mismatch, can again be calculated using the same analysis as was shown in Equations (39)-(47). The simulated systematic input referred offset for the hglnopaa opamp, using the test bench in Figure 23, was 356nV, for nominal process, voltage, and temperature. The hglnopaa2 opamp showed a systematic input referred offset of 258nV. As would be expected, the hglnopaa2 opamp would have a better input referred offset because of the larger input devices. This is also comparable with the lnselfbfcascode opamp, which was 278uV.
[pic]
Figure 60. CMRR reference curve simulations of hglnopaa using test bench actest1a. Top Curve: Differential AC Gain; Middle Curve: Common mode AC gain with input transistor gross mismatch of 5%; Bottom Curve: Common mode AC gain with input transistors matched. CMRR=97dB@1Hz, 147dB@10KHz for mismatched, CMRR=147dB@1Hz, 150dB@10KHz for matched
Nominal process, 27oC, Vcc=2.5V.
Common Mode Rejection Ratio, and Power Supply Rejection Ratio, was again simulated using the same methodology and test benches that were used for the previous designs. Simulations were done for both matched and 5% gross mismatched input devices. Results are shown in Figure 60. and Figure 61. a. and b.
Transient simulations were run using the same test bench and methodology as previously done for the other 2 opamps. Results are shown in Figure 62. and Figure 63. a. and b. The internal nodes between the input differential pair and the output stage are displayed along with the internal nodes to the common mode feedback circuit. The results show the transient behavior expected for a 90o phase margin, with no overshoot. The common mode feedback circuit is also well behaved with no sign of any problems.
[pic]
a.)
[pic]
Figure 61. PSRR reference curve simulations of hglnopaa opamp. Test bench similar to actest1a. Nominal process, 27oC, Vcc=2.5V. a.) AC gain of Vcc. Curve coincident for transistors matched and gross mismatched by 5%. PSRRVcc=107dB@1Hz, 130dB@10KHz for matched/mismatched. b.) AC gain of Vss. Top Curve: Input transistors gross mismatched by 5%.. Bottom Curve: Input transistor matched. PSRRVss=110dB@1Hz, 118dB@10KHz for mismatched, PSRRVss=137dB@1Hz, 130dB@10KHz for matched.
[pic]
Figure 62. Transient simulation of hglnopaa opamp using trantest1 test bench. +/- 2.5V input, 1us rise and fall times. Nominal process, 27oC, Vcc=2.5V. Includes internal nodes-vinvplus and vinvminus–output of diff. pair.
Also includes internal nodes of common mode feedback circuit – vcmfb, vdiffbias, and vcommon.
[pic]
a.)
[pic]
Figure 63. Transient simulation close-ups from Figure 62. Includes internal nodes - vinvplus and vinvminus – outputs of diff. pair. Also includes internal nodes of common mode feedback circuit – vcmfb, vdiffbias, and vcommon. a.)High to Low input/output. b.)Low to High input/output.
Conclusions:
Three new operational amplifier architectures were developed and compared for their performance characteristics; a new self biased folded cascode opamp, a low noise self biased cascode opamp, and a high gain low noise opamp. The folded cascode opamp has considerable worse noise and offset performance than the more complicated two stage approaches, as would be expected. Compensation for both two stage opamps was quite involved. Performance of both two stage opamps was quite similar. The high gain low noise opamp may be a some what better approach, since it does not require a dedicated amplifier for compensation, which uses power and takes up area.
More work needs to be done with validating the simulation noise models. There was a significant difference between initial simulations done, and the ones done in the VLSI Lab at ASU. The current simulation seem to be some what high in noise. Some further nise optimizations could also be done to the input stages of the 2 stage opamp designs.
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