A Hierarchical Frequency-Domain



Three-Stage Multiphase-Switched-Capacitor

Boost DC-AC Inverter

By

Yuen-Haw Chang & Zih-Yao Luo

Department and Graduate Institute of

Computer Science and Information Engineering,

Chaoyang University of Technology, Taichung, Taiwan, R.O.C.

Address: 168 Gifeng E. Rd., Wufeng, Taichung County, Taiwan, R.O.C.

Post Code: 413

Tel No.: 886-4-2332-3000 Ext.4411

Fax No.: 886-4-2374-2375

E-mail: cyhfyc@cyut.edu.tw

Abstract: A closed-loop scheme of a 3-stage multiphase-switched-capacitor boost DC-AC inverter (MPSCI) is proposed by combining the multiphase operation and sinusoidal-pulse-width-modulation (SPWM) control for low-power step-up DC-AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H-bridge (rear). The MPSC booster is suggested for an inductor-less step-up DC-DC conversion, where 3 voltage doublers in series are controlled with multiphase operation for boosting voltage gain up to [pic] at most. The H-bridge is employed for DC-AC inversion, where 4 solid-state switches in H-connection are controlled with SPWM to obtain a sinusoidal AC output. In addition, SPWM is adopted for enhancing output regulation not only to compensate the dynamic error, but also to reinforce robustness to source/loading variation. The relevant theoretical analysis and design include: MPSCI model, steady-state/dynamic analysis, voltage conversion ratio, power efficiency, stability, capacitance selection, total harmonic distortion (THD), output filter, and closed-loop control design. Finally, the closed-loop MPSCI is simulated, and the hardware circuit is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme.

Keywords: multiphase-switched-capacitor (MPSC), boost DC-AC inverter, multiphase operation, sinusoidal-pulse-width-modulation (SPWM).

1. Introduction

In the application of portable electronic equipments, power modules are always asked for some features, such as small volume, light weight, high power density/power efficiency, and good output regulation. The switched-capacitor (SC) power converter, possessed of the power stage based on charge pump structure, is one of the good solutions to low-power DC-DC conversion because it has only semiconductor switches and capacitors. Unlike traditional ones, SC converter needs no magnetic element, e.g. inductor and transformer, so such an inductor-less converter always has light weight, small volume, and low EMI.

A charge pump SC converter is usually designed to obtain an output higher than supply voltage or a reverse-polarity voltage. Such a step-up/reverse function is suitable to many applications, e.g. power-transistor, op-amp, flash EEPROM, white LED, fluorescent lamp, and LCD drivers [1]. In fact, the SC idea has existed over half a century. In 1932, Cockroft and Walton implemented a capacitor-diode voltage multiplier in the particle accelerator of the nuclear reaction. In 1971, Brugler suggested SC voltage multiplier [2], and then Lin and Chua presented the relevant topological analysis [3]. Recently, many applications are expanding as: transformerless large-conversion-ratio converter [4], bidirectional SC converter [5], and pseudo-continuous SC voltage doubler [6]. Up to now, the various SC types have been suggested for power conversion, and some well-known topologies are (i) Dickson charge pump, (ii) Ioinovici SC converter, (iii) Ueno charge pump, and (iv) Makowski charge pump. In 1976, Dickson charge pump was proposed based on a diode-chain structure with two-phase operation via pumping capacitors [7]. It provides voltage gain proportional to the stage number of pumping capacitors, and its dynamic model and efficiency analysis were discussed [8-9]. But, its drawbacks include the fixed voltage gain and larger device area. In 1993, Ioinovici et al. suggested a voltage-mode SC converter with two symmetrical capacitor cells working complementarily, and used PWM for the flexible voltage gain [10-11]. In 1994, Ngo et al. first proposed a current control of SC converters by using a saturated transistor as a controllable current source [12]. In 1997, Zhu et al. performed a comprehensive and accurate steady-state analysis of step-up SC converter [13]. In 1998, Mak et al. proposed a SC inverter with high power density and enhanced regulation capability [14]. Following this, Chang proposed an integrated scheme of SC step-up/down DC-DC/DC-AC converter [15-16]. Recently, Axelrod et al. suggested a hybrid switched-capacitor/ inductor converter [17], and Tan et al. proposed a low-EMI SC by interleaving control [18]. However, Ioinovici SC provides voltage gain proportional to the number of pumping capacitors.

In 1991, Ueno proposed lots of the new known structures: series-parallel, Fibonacci, etc. The 4-stage SC transformer idea was proposed for step-up ratio of Fibonacci series to realize an emergency power supply [19], and a low ripple-noise SC converter was presented [20]. However, their converters suffered from a limited line regulation capability. In 1997, Makowski suggested a canonical structure of multiplier charge pump with two-phase cascaded voltage doublers [21]. An n-stage Makowski charge pump can obtain voltage gain limited by the (n+1)-th Fibonacci number. Its relevant steady-state analysis, voltage/power loss were discussed, and it had been proved just to require the least number of pumping capacitors in two-phase SC [22-23]. In 2001, Starzyk proposed a new scheme of multiphase voltage doubler by using multiphase operation different from previous two-phase operation [24]. Further, the relevant performance limits were discussed, and the relationship (voltage gain and phase number) was presented by generalized Fibonacci number [25-26]. An n-stage Starzyk charge pump can boost voltage gain up to 2n at most, i.e. the number of pumping capacitors in Starzyk is required fewer than that in Makowski for the same voltage gain. Nevertheless, some improved spaces still exist, and the SC development for DC-AC is still not enough. Here, our paper targets some points as follows. (i) By using multiphase operation from Starzyk’s idea, MPSC booster is presented as the inductor-less front stage of the inverter to obtain the higher voltage gain with the less (or least) number of pumping capacitors. Most importantly, the realization of timing-control circuit for multiphase operation must be simple. (ii) Since the source voltage is decreasing with the running time of batteries, or varying due to bad-quality ones, perhaps lots of source noises occur. Also, the loading variation often results from the unexpected load failure or adding/removing the load. But, Starzyk circuit is fixed, so output regulation/robustness capability is limited. Here, by using SPWM control, the closed-loop MPSC-based DC-AC inverter is realized to enhanced output regulation for different desired output, as well as robustness against source/loading variation.

2. Configuration of MPSCI

Fig. 1 shows the closed-loop MPSCI. It contains two major units: “power unit” and “control unit”, as shown in the upper and lower half of Fig. 1. The power unit: MPSC-based inverter is composed of MPSC booster (front) and H-bridge (rear), connected in series for step-up DC-AC conversion. The control unit: SPWM controller is mainly composed of SWPM block and phase generator, working in charge of duty-cycle control and timing control of multiphase operation.

Firstly, let’s consider the MPSC booster. As shown in Fig. 1, the 3-stage MPSC booster is presented based on Starzyk charge pump [24], and composed of 3 cascaded voltage doublers in series connection between source [pic] and buffer capacitor voltage [pic]. Its main function is to boost [pic] up to [pic] times the voltage of [pic] at most. For more details, it includes 3 pumping capacitors [pic], buffer capacitor [pic], and 12 MOSFET switches [pic], where each capacitor has the same capacitance [pic] ([pic][pic]) with equivalent series resistance (ESR) [pic], the buffer capacitor has the larger capacitance [pic], and [pic] are operated as switches with the on-state resistance [pic]. Fig. 2 shows the theoretical waveforms of multiphase operation in MPSC booster, where [pic] is MPSC cycle ([pic], [pic]: MPSC frequency). Here, assume that one [pic] contains 8 phases (Phase I,II,III,…,VIII, phase number is [pic]), and each phase has the same phase cycle [pic] ([pic]). Let’s discuss Phase I-VIII operations. (i) Phase I: turn on [pic],[pic]. Then, the Phase I topology is shown in Fig. 3(a): capacitor voltage [pic] across [pic] is charged up to [pic], and [pic] is discharged to supply load [pic] in the H-bridge. (ii) Phase II: turn on [pic],[pic],[pic],[pic]. The Phase II topology is in Fig. 3(b): [pic] across [pic] is charged by [pic],[pic] in series, and [pic] is discharged to supply [pic]. (iii) Phase III: it repeats the Phase I operation. (iv) Phase IV: turn on [pic],[pic],[pic],[pic],[pic],[pic]. The Phase IV topology is in Fig. 3(c): [pic] across [pic] is charged by [pic],[pic],[pic] in series, and [pic] is still discharged to supply [pic]. (v)-(vii) Phase V-VII: the operations in Phase V/VI/VII are identical to those in Phase I/II/III, respectively. (viii) Phase VIII: turn on [pic],[pic],[pic],[pic],[pic],[pic]. The Phase VIII topology is shown in Fig. 3(d): [pic] is charged under the series connection of [pic],[pic],[pic],[pic], and simultaneously discharged to supply [pic]. Since [pic]/[pic]/[pic] is charged toward the goal value of [pic]/[pic]/[pic], [pic] can be boosted up to 8 times the voltage of [pic] at most. Thus, this MPSC booster is capable of supplying [pic] to H-bridge at most. Next, let’s look at H-bridge. As shown in Fig. 1, the structure of H-bridge is a full-wave bridge connection between [pic] and [pic], and the main function is to convert [pic] (DC) into alternating output [pic] (AC). For more details, it includes 4 MOSFETs [pic] connected with 4 diodes in parallel (assume that all the on-state resistances are [pic] as above). With the help of SPWM controller, the driver signals of [pic] are generated to keep [pic] on following the desired sinusoidal reference [pic]. In addition, there is a power-usage band-stop filter (BSF) connected with the output terminal in parallel, including filter inductor [pic] and capacitor [pic]. The main function is to obtain a harmonic trap so as to eliminate some harmonics of [pic] for the better THD.

Secondly, the control unit: SPWM controller is shown in the lower half of Fig. 1, which is composed of low-pass filter (LPF), SPWM block and phase generator. First, the phase generator is designed with digital programmable chip/ frequency divider (FD) as a timing-control circuit for multiphase operation, and it is required to generate the driver signals [pic] as shown the waveforms in Fig. 2. At the same time, from the view of signal flow, [pic] is fedback into LPF for high-frequency noise rejection. And then, the filtered [pic] is compared with [pic] in the SPWM block so as to obtain the tracking error signal [pic], as well as the control signal [pic] via a gain compensator. Next, by comparing [pic] with [pic] (saw-toothed ramp), the driver signal [pic] is obtained in A-arm, and its duty cycle is denoted by [pic] ([pic]). By inverting [pic], the driver signal [pic] is obtained and its duty cycle is [pic]. Similarly, by comparing [pic] (opposite of [pic]) with [pic], [pic]/[pic] can be obtained as the duty cycle of [pic]/[pic] in B-arm ([pic]). Fig. 4 shows the theoretical waveforms of SPWM in H-bridge. Obviously, because the A-arm and B-arm are controlled via a set of complementary control signals ([pic],[pic]), the relationship ([pic],[pic]) is easily obtained as: [pic]. When [pic],[pic] ([pic],[pic]) are on simultaneously, the effective positive (negative) output of [pic] is expectable. For the good of explanation, we take AND-logic combination of [pic],[pic] to obtain [pic] as in Fig. 4, where [pic] is the duty cycle of [pic] to handle the effective positive output, and [pic] ([pic]) can be presented as: (i) [pic], [pic]; (ii) [pic], [pic]. Similarly, [pic] is obtained by AND-logic of [pic],[pic] as in Fig. 4, and its duty cycle [pic] is in charge of the effective negative output with the relationship as: (i) [pic], [pic]; (ii) [pic], [pic]. Let’s summarize the above descriptions together in Fig. 5. In this figure, the upper 2 sub-graphs show the relationships about [pic]-[pic] and [pic]-[pic], where [pic],[pic] are the practical signals produced by the SPWM block, and [pic],[pic] are the analytic variables for the convenience of theoretical analysis and design. Thus, the positive (negative) half-cycle output of [pic] is regulated relative to how long [pic] ([pic]) is, where [pic] is the SPWM cycle ([pic], [pic]: SPWM frequency). In general, MPSC frequency [pic] is suggested to be taken at 10 times or higher value of [pic] for step-up performance of MPSC booster.

An additional remark is given here about phase number. The sufficient phase number is [pic] for the maximum voltage gain being 8 [25]. In our paper, the phase number is taken by [pic], and it seems to be a little redundant in time execution. We have some reasons to keep the redundancy as follows. (i) The timing-control circuit (phase generator) is made easier. As shown in Fig. 2, we need 3 sets of symmetrical driver signals as: [[pic],[pic] and [pic],[pic]], [[pic],[pic] and [pic],[pic]], [[pic],[pic] and [pic],[pic]] for multiphase operation. It is noticeable that these waveforms are symmetrical. In one [pic] ([pic]), [[pic],[pic]] is leading [pic] ahead of [[pic],[pic]], [[pic],[pic]] is leading [pic] ahead of [[pic],[pic]], and [[pic],[pic]] is leading [pic] ahead of [[pic],[pic]]. So, such a symmetrical regularity makes the realization of phase generator much easier. (ii) When the phase number is [pic] ([pic] has 4 phases), [pic] across [pic] is charged once (Phase I) per 4 phases. In our paper, the phase number is [pic] ([pic] has 8 phases), [pic] across [pic] is charged four times (Phase I,III,V,VII) per 8 phases. According to charge distribution, charging four times per 8 phases is more helpful to boosting response, even though the switching cycle of [pic] is 1/2 cycle longer than that of [pic]. Of course, we need a larger buffer capacitor [pic] for [pic], but not very large. If [pic], [pic] has to stand up alone for 3/4 cycle to supply the load. In our paper ([pic]), [pic] has to supply the load alone for 7/8 cycle. By comparing the two cases, our buffer capacitor [pic] is needed just 7/6 times the capacitance value of [pic] of [pic].

3. Formulation of MPSCI

In the beginning, we start with the Thevenin equivalent model of MPSC booster. And then, based on this equivalent model, the overall description of MPSC-based DC-AC inverter is derived, and it will be helpful to the theoretical analysis and control design later.

3.1 Formulation of MPSC Booster:

Let’s discuss the Thevenin equivalent model of MPSC booster. First, we remove H-bridge from the power unit, and set the circuit open temporarily. Within one [pic], there are 8 phase operations to be considered as follows. In Phase I, let [pic],[pic] be on, and the topology is in Fig. 3(a). According to this topology, the dynamic equation for Phase I can be described as

[pic], [Phase I,III,V,VII] (1)

where [pic] is the parasitic resistance of 3-stage MPSC booster. In Phase II, let [pic],[pic],[pic],[pic] be on, and the topology is in Fig. 3(b). The dynamic equation for Phase II is described as

[pic]. [Phase II,VI] (2)

In Phase III, it repeats the Phase I operation. So, the dynamic equation for Phase III is identical to (1). In Phase IV, let [pic],[pic],[pic],[pic],[pic],[pic] be on, and the topology is in Fig. 3(c). The dynamic equation for Phase IV is derived as

[pic]. [Phase IV] (3)

Next, the operations in Phase V/VI/VII are identical to those in Phase I/II/III, so the dynamic equations for Phase V/VI/VII are completely identical to (1)/(2)/(1). Finally, in Phase VIII, let [pic],[pic],[pic],[pic],[pic],[pic] be on. The Phase VIII topology is in Fig. 3(d). So, the dynamic equation for Phase VIII is derived as

[pic]. [Phase VIII] (4)

Based on (1)-(4), the open-circuit dynamic equation of MPSC booster can be derived by state-space average technique [11, 14], [pic], to be formulated as:

[pic], [pic], (5a,b)

where

[pic], (6a)

[pic],[pic],[pic]. (6b,c,d)

According to (5), the first-order equivalent model of MPSC booster will be derived. In the first-order model, there are two parameters to be determined as: boosting gain and dominant pole. Firstly, let’s look at boosting gain. For

DC analysis, by substituting [pic] of (5), the steady-state buffer capacitor voltage [pic]can be

[pic]. (7)

Obviously, [pic] can be boosted up to 8 times voltage of [pic], i.e. the boosting gain is 8. In fact, this is an open-circuit result. When the load is added in, the boosting gain will be lower than 8. Secondly, the dominant pole of MPSC booster is discussed here. Based on (6b), [pic] is divided into 4 sub-matrixes [pic]~[pic], and then [pic] can be decomposed as (8a), where the diagonal sub-matrix [pic] is presented as shown in (8b).

[pic], (8a)

[pic]. (8b)

Here, the value of [pic] is computed at about 112 ([pic]) when [pic]. Since the main goal of MPSC booster is to realize step-up DC-DC conversion and supply, [pic] must be chosen larger for the better DC quality. Here, we assume that [pic] is taken by 100 times (or larger) value of [pic]. Base on this assumption, it is obvious that the value of [pic] in [pic] is much larger than [pic] in [pic] ([pic]). So, [pic] of (8b) is the dominant pole of MPSC booster. By combining (7) and (8b), the first-order approximated model of MPSC booster can be

[pic]. (9)

Based on (9), the Thevenin equivalent model of MPSC booster can be presented as shown in Fig. 6. The equivalent circuit will be useful to the formulation of MPSCI.

3.2 Formulation of MPSC-Based Inverter:

As shown in Fig. 4, the A-arm/B-arm of H-bridge are practically controlled by [pic]/[pic], obtained by comparing [pic]/[pic] and [pic]. As the above descriptions, the effective positive/negative output of [pic] can be regulated by [pic]/[pic], and the relationships ([pic]-[pic],[pic]-[pic]) are shown in upper 2 sub-graphs of Fig. 5. According to Fig. 4 and 5, it is concluded that H-bridge contains 4 different modes (Mode I,II,III,IV) listed as follow:

(i) Mode I ([pic]): [pic], for [pic]; (ii) Mode II ([pic]): [pic], for [pic];

(iii) Mode III ([pic]): [pic], for [pic]; (iv) Mode IV ([pic]): [pic], for [pic].

Next, according to the 4 modes, the formulation of MPSCI is derived as follows. In Mode I ([pic]): [pic],[pic] are on for the period of [pic]. By combining the equivalent circuit of MPSC booster, the topology is obtained as in Fig. 7(a). According to this topology, the dynamic equation for Mode I can be described as

[pic], (10a)

[pic], [Mode I] (10b)

where [pic]/[pic] represents the filter inductor current/capacitor voltage of BSF, and [pic] is the supply-terminal current. In Mode II ([pic]): [pic],[pic] or [pic],[pic] are on for the period of [pic]. Also, the topology is obtained as shown in Fig. 7(b), and then the dynamic equation for Mode II can be

[pic], (11a)

[pic]. [Mode II] (11b)

Based on (10)-(11), the dynamic equation of MPSCI for [pic] can be derived by state-space average technique, i.e. [pic], to be formulated as:

[pic], (12a)

[pic], for [pic]. (12b)

Similarly, Fig. 7(c)/7(d) deals with the Mode III/IV topology for the period of [pic]/[pic] . According to the topologies, their dynamic equations for Mode III and IV can be formed. And then, by using the average technique, the dynamic equation of MPSCI for [pic] is derived as:

[pic], (13a)

[pic], for [pic]. (13b)

Here, for convenience to explain full-wave control, we take a new variable of integrated duty cycle [pic] with the definition as follows: (i) positive half-cycle: [pic] for [pic], (ii) negative half-cycle: [pic] for [pic]. Based on this definition, the waveform of [pic] can be obtained as in the bottom of Fig. 4, and its duty cycle is just [pic] with the range of [pic]. Fig. 5 shows the whole relationships among [pic], [pic], and[pic]. When [pic], it means that the positive half-cycle of [pic] is running. When [pic], the negative half-cycle of [pic] is working. Thus, the full-wave output of [pic] can be controlled by this integrated duty cycle [pic] ([pic]). Finally, based on (12)-(13), in terms of the new [pic], the state-space description of MPSCI can be derived as:

[pic], (14a)

[pic], (14b)

where

[pic],[pic],[pic], (15a,b,c)

[pic],[pic],[pic]. (15d,e,f)

4. Analysis and Design of MPSCI

4.1 Steady-State and Dynamic Analysis:

For steady-state and dynamic analysis, all variables of (14) are considered with static and dynamic signals as: [pic],[pic],[pic],[pic],[pic],[pic], where [pic],[pic],[pic],[pic],[pic],[pic] are the static operating signals, and [pic],[pic],[pic],[pic],[pic],[pic] represent the dynamic small-signal signals. First, let’s look at the steady-state analysis. By substituting [pic] of (14), the steady-state output voltage [pic], output current [pic], and supply-terminal current [pic] can be

[pic], [pic], (16a,b)

[pic], (16c)

where sub-matrix [pic]/[pic] is the 1st/2nd row of [pic]. From (16a), it is obvious that [pic] is a function of [pic] ([pic]). In other words, the value of [pic] is regulated by [pic], and even the polarity of [pic] can be also changed because of [pic]. In addition, as shown in (16c), [pic] equals the absolute value of [pic] ([pic]). This is a reasonable result because [pic] has no negative current at supply terminal.

Next, let’s consider dynamic analysis of MPSCI. Based on (14), by using small-signal analysis (around one static duty cycle [pic]), the dynamic transfer function between [pic] and [pic] can be derived as

[pic]. (17)

Here, [pic] is formed by the product of [pic] and [pic]. The 1st term: [pic] results from the power-usage output filter, which is a second-order BSF including [pic] and [pic]. This BSF is just like a harmonic trap to eliminate some harmonics of [pic]. The 2nd term: [pic] comes from MPSC booster plus loading effect, and its maximum output is really close to [pic] when [pic]. The small-signal model of (17) will be helpful to control design later.

4.2 Conversion Ratio and Power Efficiency:

According to (16a), the voltage conversion ratio [pic] can be suggested as

[pic]. (18)

If [pic], then [pic]. If [pic] ([pic]), then the maximum (minimum) of [pic] will be close to [pic]8 ([pic]8) when [pic],[pic]. In other words, [pic] can be converted into the voltage range of [pic]. For nominal conditions, the maximum attainable output [pic] is [pic]voltage drops in the charging and discharging circuits. So, [pic] is asked much larger than the parasitic [pic],[pic] for the better conversion ratio. In fact, [pic] is about in [pic]-level, and [pic],[pic] is about in [pic]-level.

Next, the power efficiency is discussed. Assume that we have two types of desired outputs to consider as follows.

(i) The duty cycle is operating at a positive constant ([pic],[pic]), i.e. [pic] is desired at a positive DC output ([pic]). Based on (16), the steady-state input power [pic] and output power [pic] are computed as (19). Then, by using (19), the DC-DC power efficiency [pic] can be derived as (20).

[pic], [pic], (19a,b)

[pic]. (20)

(ii) The duty cycle is assumed sinusoidal ([pic], [pic]), i.e. [pic] is desired at a sinusoidal AC output ([pic]), where [pic] is the output frequency. Thus, [pic] and [pic] are computed as shown in (21), and then the DC-AC power efficiency [pic] can be derived as (22).

[pic], [pic], (21a,b)

[pic]. (22)

According to (20) and (22), if [pic] and [pic],[pic] are small enough to be neglected, then the maximum values of [pic],[pic] can reach to 100%, 78.5% theoretically. Obviously, [pic],[pic] become higher when the maximum output value [pic] is chosen closer to [pic]. But, when [pic] is much lower than [pic], the efficiencies will be quite bad. So, it is good for the efficiency to choose [pic] be close to [pic] as much as possible. If not realized, we will change [pic] or reduce the stage number [pic] (from 3 to 2 or 1) to fit [pic] for [pic] as close as possible.

4.3 Stability and Capacitance Selection:

First, let’s discuss the open-loop stability of MPSCI. Based on [pic] of (15d), the characteristic equation can be

[pic], (23)

where the 1stt fractional term is relative to MPSC booster, and the 2nd term is relative to the output filter in the H-bridge. Based on (23), the characteristic roots are obtained as:

[pic], [pic], when [pic]. (24a,b)

As shown in (24a), it is obvious that MPSC booster is stable because [pic] is in the left half of s-plane no matter what [pic] is set on ([pic]). Based on (24b), it is also clear that H-bridge plus output filter is stable because the real parts of [pic] are negative when [pic]. So, the proposed MPSCI has an inherent good stability.

Next, let’s discuss the capacitance selection of [pic],[pic]. According to the topology in Fig. 3(a) (Phase I,III,V,VII), the phase time constant [pic] ([pic]) must be smaller than phase cycle [pic] for the faster boosting response. As above, [pic] is equal to one eighth of switching cycle [pic] ([pic]). According to Fig. 3(a)-(c) (Phase I-VII), it is found that [pic] stands alone to discharge and supply [pic] for 7/8 cycle of [pic]. So, the discharging time constant [pic] must be asked larger than [pic]. Now, let’s summarize these relationships, and then the time inequality is obtained as:

[pic]. (25)

Based on (25), [pic] should be chosen larger for the better DC quality of [pic], and [pic] should be chosen smaller for the faster boosting response. In other words, (25) provides for the capacitance selection of [pic],[pic]. In addition, as above explanation, [pic] is much larger than [pic],[pic] ([pic],[pic]) for the better conversion ratio. That is also helpful to satisfy (25).

4.4 THD and Filter Design:

Let’s consider THD and output filter design. As above descriptions, this integrated duty cycle [pic] ([pic]) is defined as: (i) [pic], [pic], (ii) [pic], [pic], and its relative waveform [pic] can be obtained as shown in Fig. 4. Here, Fig. 8 shows the detailed waveform of [pic] within one output cycle [pic], where [pic] is the inverse of output frequency [pic] ([pic][pic]). Now, assume that the output filter has not been added in yet, and based on the operation of [pic] within one [pic], [pic] can be expressed as:

[pic], (26)

where [pic] is the number of [pic] within one [pic] (i.e. [pic]), and [pic] is a pulse function between [pic] and [pic], defined as [pic], [pic] with the discrete sinusoidal duty cycle [pic], [pic]. Because [pic] of (26) is an odd function, the Fourier series of [pic] can be expressed as (27), where the Fourier coefficients [pic] are shown in (28) with [pic],[pic] (variable change:[pic]).

[pic], (27)

[pic] (28)

According to (28), [pic] can be computed and arranged in Fig. 9 ([pic],[pic]), and the THD is obtained as: [pic]46.85%. Clearly, this THD is not good because the output filter has not been added in. In Fig. 9, it is observed that the harmonics occur at about [pic], i.e. they are always around the frequencies of [pic],[pic],[pic]… ([pic],[pic],[pic]…). Obviously, the harmonics around [pic] affect the THD value most. Here, let’s add a band-stop filter connected with [pic] in parallel, and it is treated as a harmonic trap to eliminate the harmonics around [pic]. As shown in (17), [pic] is a second-order transfer function of BSF including [pic] and [pic]. Let [pic] be rewritten by a standard form of band-stop filter as:

[pic], (29)

and then the stop-band center frequency [pic] and the quality factor [pic] can be obtained as:

[pic], [pic]. (30a,b)

In order to eliminate the harmonics around [pic], [pic] is taken by [pic] as shown in (31a). By combining (30b) and the assumption of (24b), it is found that [pic] is equivalent to [pic] as (31b).

[pic], [pic]. (31a,b)

Based on (31), the filter inductor [pic] and capacitor [pic] can be designed as:

[pic], [pic]. (32a,b)

In fact, for a smooth frequency response, [pic] should not be too big. In general, [pic] is chosen smaller than 1, i.e. [pic]. Thus, [pic] is not suitable to exceed twice the value of [pic] . Similarly, other output filters can be designed for trapping other harmonics around [pic],[pic]… . Based on filter design of (32), the harmonics around [pic] are eliminated, and the THD can be improved to [pic]. If adding the design of [pic], then the THD can be reduced to [pic]. Also, for the better THD, it is practicable that we can add a small bypass capacitor [pic] in parallel connection with [pic] to bypass the high-order harmonics around [pic],[pic]… .

4.5 Control Design of MPSCI:

Let’s consider control design of MPSCI. As shown in Fig. 1, [pic] is sent into LPF for high-frequency noise rejection. In the LPF, there is a parameter of cut-off frequency [pic] chosen according to what range the possible high-frequency noises occur at. Certainly, in order to avoid affecting the response of MPSCI, [pic] is generally taken at the value higher than output frequency [pic] ([pic]). Next, via the SPWM block, the filtered [pic] is compared with [pic] to produce duty cycle [pic]. The main goal is to keep [pic] on following [pic] by duty-cycle adjustment. Fig. 10(a) shows the control diagram of closed-loop 3-stage MPSCI, where a proportional gain [pic] is included to compensate error, rise or settling time. If [pic] or [pic] is decreasing (source/loading variation), based on (16a), [pic] will be going down. Thus, the error e between [pic] and [pic] is rising quickly. The bigger error e makes a larger duty cycle [pic] via gain [pic], and then the larger [pic] can drive [pic] to keep following [pic]. So, the output regulation (line/load regularity) can be improved.

Now, let’s discuss the design of [pic]. Assume that the MPSCI is running around one operating point of duty cycle [pic] for some desired [pic]. In other words, the steady-state output [pic] is supposed to equal [pic] under this duty cycle [pic] right now. By combining (17) and Fig. 10(a), a small-signal closed-loop diagram of MPSCI can be presented in Fig. 10(b), and then the closed-loop characteristic equation is obtained as

[pic]. (33)

When we consider the dynamic response at the frequency lower than cut-off [pic] in LPF, plus [pic],

the characteristic equation of (33) can be approximated as

[pic]. (34)

Based on (34), the closed-loop settling time [pic] within a settling error of [pic] is obtained as

[pic]. (35)

So, the minimum gain of [pic] can be designed for keeping [pic] shorter than a desired settling time [pic] as:

[pic]. (36)

Next, let’s consider the maximum gain of [pic] for some phase margin [pic]. Now, let the phase margin be higher than the desired [pic] as: [pic], where [pic] is the gain-crossover frequency of [pic] with [pic]. So, [pic] can be obtained as:

[pic]. (37)

By substituting (37) into the inequality of [pic], the maximum gain of [pic] for the desired [pic] can be derived as:

[pic]. (38)

5. Experiment of MPSCI

In this section, a closed-loop 3-stage MPSCI with SPWM control is simulated by OrCAD tool (PSPICE), and the hardware circuit is implemented and tested. All the results are illustrated to verify the efficacy of the proposed scheme. First of all, according to Fig. 1, the closed-loop MPSCI is designed by PSPICE for circuit simulation. In the front of the inverter, the MPSC booster is presented via multiphase operation for boosting [pic] up to 8 times the voltage of supply [pic] at most ([pic]). In the rear of the inverter, the H-bridge is employed via SPWM control for DC-AC conversion to supply the load [pic] ([pic]). Other parameters are listed as follows: [pic], [pic],[pic],[pic],[pic],[pic]. Here, the type of capacitors we suggested is a radial low-ESR aluminum electrolytic capacitor. Because its electrolyte film is made thin, the large capacitance can be realized in the small volume. Thus, the low-ESR capacitors can be used for the better performance. In the SPWM controller, cut-off [pic] is taken by about [pic] for high-frequency noise rejection. By using (36) and (38), the gain [pic] is designed at 0.05 for the desired [pic] and [pic]. According to (32), the filter inductor and capacitor can be chosen as: [pic],[pic] for the output frequency [pic] ([pic]). Besides, for the better THD, a very small bypass capacitor [pic] is added in parallel connection with [pic] to bypass the harmonics around [pic],[pic]… . Next, several cases are simulated as including (i) steady-state response, (ii) source variation, and (iii) loading variation. In the end of section, the MPSCI hardware is implemented, and tested similarly for the 3 cases of (i) steady-state response, (ii) source variation, and (iii) loading variation.

(i) Firstly, let’s discuss the steady-state response. The closed-loop 3-stage MPSCI is simulated for the different sinusoidal references [pic] and load resistances [pic] ([pic][pic]/[pic],[pic][pic]/[pic],[pic][pic]/[pic]), and then the waveform results of output [pic] are shown in Fig. 11. In these figures, it is observed that the MPSCI is at the stable work on step-up DC-AC conversion, and steady-state [pic] are really following [pic] under the different peak values [pic] and output frequencies [pic]. Also, it is observed that the settling time [pic] is really shorter than [pic]. In addition, the power efficiencies and THD are obtained as: [pic][pic],[pic],[pic],[pic], and [pic][pic],[pic],[pic],[pic]. Thus, the results show that the MPSCI has a good steady-state performance of step-up DC-AC conversion/regulation.

(ii) Secondly, let’s discuss the case of source disturbances. Since source voltage is decreasing with time, or varying due to bad-quality source, the robustness to source disturbances must be considered. Here, we have 2 cases of source variations (exponential and sinusoidal) as follows. (A): [pic] is assumed at [pic] plus an exponential drop from [pic] to [pic] after [pic], as shown in the upper half of Fig. 12(a). Then, for the desired [pic] ([pic][pic], [pic][pic]), [pic] is shown in the lower half of Fig. 12(a). Obviously, [pic] is firmly following [pic], even though [pic] has decreased to [pic]. (B): Assume [pic] is [pic] plus sinusoidal disturbance with peak-to-peak voltage of [pic] after [pic], as shown in the upper half of Fig. 12(b). Similarly, [pic] is obtained as in the lower half of Fig. 12(b) ([pic][pic],[pic][pic]). Clearly, [pic] is still following [pic] in spite of source sinusoidal disturbance. Thus, the results show that the MPSCI has good output robustness to source disturbances.

(iii) Thirdly, the case of loading variation is discussed. Due to long-time running, perhaps the rising temperature causes short-circuit failure in the load unexpectedly. It results in a big loading variation. Here, we have 2 cases to discuss as follows. (A): [pic] is assumed at [pic] normally, and it changes from [pic] to [pic] at [pic] due to short-circuit failure. After a short period, the load recovers from the failure, and [pic] changes from [pic] to [pic] at [pic]. Fig. 13(a) shows the waveforms of error [pic] and [pic] at the moment of loading variations ([pic]=[pic] [pic]). The upper half of Fig. 13(a) shows that error [pic] really becomes bigger during the short-circuit failure ([pic]~[pic]). But, the MPSCI still keeps [pic] on following [pic] ([pic][pic],[pic][pic]) as shown in lower half of Fig. 13(a). (B): Assume that the other load of [pic] is added in parallel with [pic] at [pic], and then the added load is removed away at [pic]. In other words, the total resistance of [pic] is varying as: [pic][pic] [pic]. Fig. 13(b) shows the waveforms of [pic] and [pic], and it is found that [pic] is still following [pic] ([pic][pic],[pic][pic]) in spite of loading variation. These results show that the closed-loop MPSCI has a good

regulation capability for loading variation.

Finally, according to the above design and analysis, the hardware of the closed-loop MPSCI is realized and implemented as shown in the photo of Fig. 14. In the figure, there are two parts including: (i) Left side: three-stage MPSC booster (layout circuit:[pic], capacitor bank:[pic]), (ii) Right side: H-bridge and SPWM controller (bread board:[pic]). Next, the closed-loop MPSCI hardware circuit is tested practically for the cases of steady-state response, source/loading variation ([pic][pic],[pic][pic], Agilent Infiniium 54830B oscilloscope, signal attenuation rate: 4.7 times). (i) Firstly, the steady-state response is tested. Fig. 15 shows the waveforms of output [pic] for the desired [pic] ([pic][pic]/[pic],[pic][pic]/[pic]). In Fig. 15(a), the output peak-to-peak value [pic] is measured at [pic], i.e. the practical peak value of [pic] is [pic] ([pic]), and the practical frequency is [pic][pic]. In Fig. 15(b), [pic] is [pic], i.e. the practical ac peak of [pic] is [pic] ([pic]), and the practical frequency is [pic][pic]. Obviously, the MPSCI circuit is not only at the stable step-up DC-AC conversion, but also the steady-state results of [pic] are really following the desired [pic]. In addition, the power efficiency and THD are measured as: [pic][pic]/[pic], [pic][pic]/[pic]. These results can be verified by the conclusions in Section 4-2 and 4-4. So, these results show that the MPSCI has a good steady-state performance. (ii) Secondly, let’s consider 2 cases of source variation. (A): For the different sources [pic][pic]/[pic], the waveforms of [pic] are measured as shown in Fig. 15(a)/16(a) for the desired [pic] ([pic][pic], [pic][pic]). In Fig. 15(a), [pic] is [pic] when [pic][pic], i.e. the peak of [pic] is [pic] ([pic]). In Fig. 16(a), [pic] is [pic] when [pic] has decreased to [pic], i.e. the practical ac peak of [pic] is [pic] ([pic]). By comparing the two results, it is found that [pic] is firmly following [pic], even though [pic] has decreased to [pic]. ([pic][pic][pic]). (B): Assume [pic] is [pic] plus sinusoidal disturbance with peak-to-peak voltage of [pic], as shown in the upper half of Fig. 16(b). For the desired [pic] ([pic][pic],[pic][pic]), [pic] is measured as shown in the lower half of Fig. 16(b). In Fig. 16(b), [pic] is [pic], i.e. the peak of [pic] is [pic] ([pic]). Clearly, [pic] is still following [pic] in spite of source sinusoidal disturbance. (iii) Thirdly, the MPSCI circuit is tested for loading variation. Assume that Fig. 15(a) shows the normal output waveform of [pic] for the standard load of [pic] ([pic][pic][pic],[pic][pic]). (A): When we increase the loading to be triple ([pic]), the waveforms of [pic] and [pic] are obtained as in Fig. 17(a). In this figure, the peak-to-peak value [pic] is [pic], i.e. the peak of [pic] is [pic] ([pic]), and the practical frequency is [pic][pic]. Obviously, the MPSCI still keeps [pic] on following [pic], even though the loading is added. (B): When a half of the loading is reduced ([pic]), the waveforms of [pic] and [pic] are obtained as shown in Fig. 17(b). In the figure, the peak-to-peak value [pic] is measured at [pic], i.e. the peak of [pic] is [pic] ([pic]), and the practical frequency is [pic][pic]. So, [pic] is still following [pic] in spite of reducing the loading.

6. Conclusions

A closed-loop 3-stage MPSCI is proposed by combining multiphase operation and SPWM control for low-power step-up DC-AC conversion and regulation. In this MPSCI, the power unit contains two parts: MPSC booster (front) and H-bridge (rear). The 3-stage MPSC booster is operated with multiphase operation to realize the inductor-less step-up DC-DC conversion for boosting voltage gain up to [pic] at most. The H-bridge is employed with SPWM control to realize the DC-AC conversion for obtaining a sinusoidal AC output. Some relevant theoretical analysis and design are included. Finally, the closed-loop MPSCI is simulated, and then the hardware is implemented and tested. All the results are illustrated to show the efficacy of the proposed scheme. The advantages of this proposed scheme are involved as follows. (i) The SC-based MPSCI scheme needs no large power-usage magnetic element, so I.C. fabrication will be promising. (ii) This MPSC booster can obtain the high voltage gain by the less number of pumping capacitors, so it will save device area more. (iii) For the better output regulation, the SPWM technique is adopted not only to compensate the dynamic error, but also to reinforce the output robustness against source/loading variation. (v) From the stability analysis, all poles are located in the left half of s-plane, so the open-loop MPSCI is stable. Thus, the MPSCI scheme has an inherent good stability. In the future, based on this scheme presented here, it will be an attractive direction to develop the generalized structure of multistage MPSCI.

Acknowledgment

The research of converter circuit theory and application of Yuen-Haw Chang is financially supported by the National Science Council of Taiwan, R.O.C., under Grant NSC 98-2221-E-324-024 and NSC 99-2221-E-324-014.

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[pic]

Fig. 1. Configuration of MPSC-based boost DC-AC inverter.

[pic]

Fig. 2. Theoretical waveforms of multiphase operation in MPSC booster.

[pic]

(a). Phase I, III, V, VII.

[pic]

(b). Phase II, VI.

[pic]

(c). Phase IV.

[pic]

(d). Phase VIII.

Fig. 3. Topologies of 3-stage MPSC booster.

[pic]

Fig. 4. Theoretical waveforms of SPWM in H-bridge.

[pic]

Fig. 5. duty cycle relationship.

[pic]

Fig. 6. Thevenin equivalent circuit of MPSC booster.

[pic]

(a). Mode I topology of MPSCI.

[pic]

(b). Mode II topology of MPSCI.

[pic]

(c). Mode III topology of MPSCI.

[pic]

(d). Mode IV topology of MPSCI.

Fig. 7. SPWM-based H-bridge topologies.

[pic]

Fig. 8. The detailed waveform of [pic].

[pic]

Fig. 9. Fourier coefficients [pic] for [pic],[pic].

[pic]

Fig. 10(a). Control diagram of closed-loop MPSCI.

[pic]

Fig. 10(b). Small-signal closed-loop MPSCI.

[pic]

Fig. 11(a). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 11(b). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 11(c). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 11(d). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 12(a). [pic] with exponential disturbance and [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 12(b). [pic] with sinusoidal disturbance and [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 13(a). Error [pic] and [pic] ([pic][pic],[pic][pic],[pic]).

[pic]

Fig. 13(b). Error [pic] and [pic] ([pic][pic],[pic][pic],[pic]).

[pic]

Fig. 14. Hardware implementation of closed-loop MPSCI.

[pic]

Fig. 15(a). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 15(b). Output voltage [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 16(a). [pic] and [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 16(b). [pic] and [pic] ([pic][pic],[pic][pic],[pic][pic]).

[pic]

Fig. 17(a). [pic] and [pic] ([pic][pic],[pic][pic]) for [pic][pic] (triple loading).

[pic]

Fig. 17(b). [pic] and [pic] ([pic][pic],[pic][pic]) for [pic][pic] (half loading).

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