Mentor Graphics Tutorial: Schematic Capture, Simulation ...

Mentor Graphics Tutorial: Schematic Capture, Simulation, & Placement/Routing

1.0 Introduction

This tutorial demonstrates a simple VLSI circuit design process from concept to chip layout of an 8-bit Modified Booth Multiplier on a 0.5?m process using software from Mentor Graphics Corp. The topics covered in this tutorial include schematic capture & design, simulation, and placement & routing.

2.0 Schematic Capture & Design

The specification for the design calls for an 8-bit unsigned multiplier that accepts two 8bit unsigned inputs and produces a 16-bit unsigned output as a result. Three additional control signals are required, including a DONE, START, and CLOCK signal. The implementation presented in this tutorial consists of these baseline requirements, in addition to a RESET control signal. Also, the multiplier accepts signed inputs and therefore performs signed multiplication. We use Booth's Modified Algorithm as the underlying architecture for the design due to its ability to produce a result quickly and reliably. In an effort to better understand the derivation of the design, a brief description of Booth's Modified Algorithm follows.

2.1 Booth's Modified Algorithm

On average Booth's Modified Algorithm can produce results in approximately half the time that the traditional "add and shift" multiplier can. This is because Booth's Modified Algorithm "looks" at strings of three bits simultaneously with a one-bit overlap in each successive comparison in order to decide what to do next. Since one bit of each string of three bits overlaps with the previous triplet, two new bits are effectively considered during each clock cycle. In the case of an 8-bit multiplier, this means that calculations can optimally be performed in 4 clock cycles, excluding additional control states. The following is a more formal definition of the Modified Booth Algorithm. Let x be the multiplier and m be the multiplicand. Let two bits of x plus the last bit from the previous two bits represent the triplet xL. Assume x and m are n-bit signed binary numbers. The triplet xL can be represented by the following vector:

x L = x 2 y +1 , x 2 y , x 2 y -1

(1)

where

y = 0,1,2,..., n ; 2

x2y+1 is the first bit of the triplet, x2y is the second bit of the triplet,

and x2y-1 is the overlapped bit from the previous triplet. Letting xi be the ith bit of x and

let x-1 = 0, the two's complement of x can be written as

( ) n-2

x = -xn-1 2n-1 + xi 2i

(2)

i=0

 ( ( )) n2-1

= 22 y - 2 x2 y+1 + x2 y + x2 y-1

(3)

y=0

The product p(m, x) can be expressed as

( ( )) ( ) n2-1

p m, x = m22y -2 x2y+1 + x2y + x2y-1 (4)

y=0

( ) n2-1

= 22y xy,m

(5)

y=0

( ) where xy ,m represents the Modified Booth recoding function and is defined by the

piecewise function:

0, xy = 0,0,0

m, xy = 0,0,1

m, xy = 0,1,0

( ) xy,m =

2 m, - 2 m,

xy = 0,1,1 xy = 1,0,0

- m, xy = 1,0,1

- m, xy = 1,1,0

0, xy = 1,1,1

(6)

In order to implement this algorithm in hardware, several conclusions must be drawn

from the relationships above. From equation 5, it follows that an n 2 -operand adder is

necessary to cumulatively sum the

n 2

terms during each successive multiplication.

For

the Modified Booth recoding function defined in equation 6, a combinational logic

network is necessary in order to produce the recoded multipliers 0, ?m, and ?2m from m,

the multiplicand.

This algorithm reduces the total number of additions from n to

n 2

at

the cost of extra logic to generate and select the necessary recoded multipliers [1,2].

2.2 Design & Methodology

The Mentor Graphics Design Architect tool is used in this tutorial for schematic capture and design. Due to the nature of schematic capture, a hierarchy consisting of encapsulation and abstraction is used to make the design more modular and comprehensible. The ADK libraries consist of all the necessary standard cells needed to build each functional unit comprising the circuit, and therefore they will be used extensively. The top level circuit schematic, presented in figure 1, consists of 7 primary functional units. In total, there are 11 functional units that encompass the design.

Figure 1. Top-Level Circuit Schematic

Some components contain other custom symbols, and therefore these symbols cannot be found via the ADK libraries, rather they must be imported by clicking on the CHOOSE SYMBOL button in the ADD/ROUTE schematic palette window. To import a symbol, you must navigate to the directory containing the symbol. For each functional unit, a symbol must be generated in order for the component to be used elsewhere. As stated earlier, the use of symbols make the schematic more comprehensible. In addition, the design makes extensive use of data buses. Buses allow bits to be grouped so as to avoid having separate wires for each bit running all over the place. Grouping bits into a bus simplifies the overall look of the design and is therefore recommended. A bus can be instantiated by clicking on the ADD BUS/BUNDLE button on the ADD/ROUTE schematic palette window. After a bus route has been placed, the name and size must be specified. To do this, select the bus by clicking on it with the LMB. Choose the NetName Nets popup menu item with the RMB. Enter the name that defines the bus in the Property Value text box. Click the OK button. Move the cursor in the schematic window. Drag the bus name to the location you want it displayed. Click the LMB to fix the text position. The naming of the bus should conform to the following format: bus_net_name(msb:lsb), where bus_net_name is any name of your choice, msb is the most significant bit, and lsb is the least significant bit. Next, add a wire to the bus by clicking on the ADD WIRE button on the ADD/ROUTE schematic palette window and attach it to the bus. A pop-up menu will appear asking you which bit you would like to

use. A bus does not have to be named in the event that two symbols with common bus sizes are to be connected. Ports (inputs/outputs), GND & VDD, basic logic gates, flipflops, transistors, pads, etc. can be added by navigating to the ADK libraries under the Libraries pull-down menu. This will display the ADK libraries palette menu to the right of the screen. This concludes the basic foreknowledge needed in order to reproduce the multiplier presented in this tutorial. The tutorial will proceed as follows: Each functional unit will be presented and a brief description of each will be given. 2.2.1 The Control Unit Figure 2 presents the Design Architect circuit schematic for the control unit. The main control unit is implemented as a finite state machine consisting of eight states.

Figure 2. Control Unit Circuit Schematic (control) Figure 3 presents the state diagram flow chart and the corresponding state table for the control unit. From the diagram, the reset and ready signals control which state the multiplier is in. The reset signal has the effect of clearing all storage units in the multiplier in addition to reinitializing the current state to zero, while the ready signal only has an effect in states zero and seven.

X1 10

X1 X0

7

00

0

10

X1, 00

1 X1 X0

6

X1

2

X1

X0

5

X0

3

X0

4

X0

X1

CONTROL STATES

STATE DEFINITION

0 0 0 CLEAR / WAIT FOR RDY SIGNAL

0 0 1 RDY ASSERTED / LOAD MULTIPLICAND

0 1 0 LOAD MULTIPLIER

0 1 1 ADD RECODED MULTIPLIER AND SHIFT BY 2

1 0 0 ADD RECODED MULTIPLIER AND SHIFT BY 2

1 0 1 ADD RECODED MULTIPLIER AND SHIFT BY 2

1 1 0 ADD RECODED MULTIPLIER AND SHIFT BY 2

1 1 1 WAIT FOR RDY SIGNAL AND ASSERT DONE

Figure 3. Control Unit State Definitions

The primary function of the control unit is to manage the state of the multiplier. The inputs to the control unit consist of a ready signal, which signals the start of a multiplication cycle, a clock signal; and a clear signal, which resets the state of the entire multiplier. The output signals of the control unit consist of a 3-bit bus, which defines the current state of the multiplier; a done signal, which signifies that the multiplication has finished; and an enable signal, which enables storage of the multiplicand into an 8-bit register for recoded multiplier generation. The control unit was designed using D-FlipFlops, and the equations were derived from the state table in figure 4 below.

PRESENT INPUT

NEXT

QS2 QS1 QS0 RDY RST Q'S2 Q'S1 Q'S0

000 0 0 0 0 0

000 1 0 0 0 1

001 0 0 0 1 0

001 1 0 0 1 0

010 0 0 0 1 1

010 1 0 0 1 1

011 0 0 1 0 0

011 1 0 1 0 0

100 0 0 1 0 1

100 1 0 1 0 1

101 0 0 1 1 0

101 1 0 1 1 0

110 0 0 1 1 1

110 1 0 1 1 1

111 0 0 1 1 1

111 1 0 0 0 1

XXX X 1 0 0 0

Figure 4. Control Unit State Table

In an effort to minimize the amount of logic gates required to implement the state machine, the above table was placed into three 4-bit Karnough maps. The following figures present the Karnough maps obtained from the state table shown in figure 4.

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