VHDL Files - People
Appendix I – Notebooks:
Phoebus Chen
= Index =========================================================
Mon Apr 23 16:00:29 PDT 2001 - Group discussion on how to split up work.
Wed Apr 25 16:58:12 PDT 2001 - Planning for Branch prediction.
Fri Apr 27 01:41:51 PDT 2001 - drew 2 bit predictor and starting branch
predictor.
Fri Apr 27 18:45:02 PDT 2001 - Finished making symbol for branch history table.
Mon Apr 30 01:01:29 PDT 2001 - Finished making branch history table entry.
Mon Apr 30 17:52:13 PDT 2001 - Finished making branch prediction unit, changed
branch history table entry, untested.
Fri May 4 23:49:00 PDT 2001 - Finished writing VHDL for testing branch
predictor, but doesn't compile.
Sat May 5 17:20:15 PDT 2001 - Got testbench for branch predictor to compile
but branch predictor fails.
Sun May 6 23:37:26 PDT 2001 - Debugged more of branch predictor.
(- 2 hours for dinner break)
Mon May 7 17:38:19 PDT 2001 - Got tester working.
Tue May 8 00:07:35 PDT 2001 - Finished testing branch predictor, fixed some
bugs (we didn't test branch addresses before).
Wed May 9 01:38:55 PDT 2001 - Almost completed building branch validation unit.
(- 2 hours for dinner break)
Time Spent:
=================================================================
+++ Mon Apr 23 12:15:41 PDT 2001 ================================
Goal: Figure out how to do branch prediction.
We divided up the work for Tomasulo today. I got to do branch prediction.
For branch prediction, I need to build a cache of past branches and the 2 bit branch predictor. I also need to pass the address of the branch that I didn't take to the branch FU reservation station. I'll be working with Manda on how to issue the next instruction quickly, and squashing. It's likely that I'll be working on the branch unit as well.
--- Mon Apr 23 16:00:29 PDT 2001 ================================
+++ Wed Apr 25 14:32:23 PDT 2001 ================================
Goal: Layout branch prediction unit's I/O.
* We always don't branch the first time we see a new branch instruction.
* remember to give an invalid_next signal to Manda, so that when we invalidate a branch, she will throw away the next instruction fetched from memory.
* if a previous branch was incorrect, we flush all instructions after it. This means that if we get a "branch_invalid" signal, the nextPC mux will not see the result of the branch predictor unit. This means the branch prediction unit needs not update the history table until the transition at the beginning of the next cycle.
Branch History Table:
Entries:
PC
valid bit
PC + Immediate (branch)
2 bits for taken/not taken
Tag comparator
2 bit state machine
ALU - for new branches, to calculate branch to address and store in table
Branch Validation FU:
Comparator
register storing non-predicted address
reservation station
*ALG* Branch Prediction (direct mapped, simple 2-bit):
At clock edge, latch in updated entry if misprediction in previous cycle.
||Check Opcode for branch
||Calculate branch address (immed + PC, in ALU)
||Use lower part of PC to index table
||check valid bit
||check tag with PC
||check taken/not taken
||fetch branch address
if (branch_opcode) then
if (not_valid or not_tag_match) then
nextPC_mux_sel chooses PC+4 //predict not branch
store new calculated branch address to table (next cycle)
elseif (taken) then
nextPC_mux_sel chooses branch address from table
else //not taken
nextPC_mux_sel chooses PC+4
endif
endif
Haven't coded anything yet today.
--- Wed Apr 25 16:58:12 PDT 2001 ================================
+++ Fri Apr 27 00:39:23 PDT 2001 ================================
Goal: Build 2 bit predictor and test unit.
Too tired. I built the untested 2 bit predictor and drew an alu for the branch predictor.
I kmapped the 2 bit predictor.
--- Fri Apr 27 01:41:51 PDT 2001 ================================
+++ Fri Apr 27 16:47:09 PDT 2001 ================================
Goal: Finish Branch History Table.
Finished the symbol for the Branch History Table, but not the schematic yet.
--- Fri Apr 27 18:45:02 PDT 2001 ================================
+++ Sun Apr 29 22:39:03 PDT 2001 ================================
Goal: Finish Branch predictor.
Ack, still didn't finish building it. Once I finish building the branch history table, I should be able to begin testing. I did finish the branch history table entry, however.
--- Mon Apr 30 01:01:29 PDT 2001 ================================
+++ Mon Apr 30 14:48:08 PDT 2001 ================================
Goal: Finish Branch Predictor and Start planning for branch unit.
Okay, after talking with JimmyD I realized how stupid it is to store the target branch address considering that it's not a bottleneck for the branch prediction unit - it can still complete in one cycle with an adder. I'll continue to store the tag so that we don't branch predict for different instructions, I suppose. This may make debugging easier.
Yes, finished the branch predictor. It's really simple now. Next comes testing and building the validation unit. Shouldn't be too bad.
--- Mon Apr 30 17:52:13 PDT 2001 ================================
+++ Fri May 4 22:20:11 PDT 2001 ================================
Goal: Test Branch Predictor, look at branch validation unit.
Well, I finished compiling all the files and i write the VHDL file, but I'm having problems compiling it. Will look at this tomorrow.
--- Fri May 4 23:49:00 PDT 2001 ================================
+++ Sat May 5 14:08:05 PDT 2001 ================================
Goal: Finish Testing Branch Predictor and build branch validation unit.
Ack, I got the testbench to compile, but my component is failing the tests. Will keep testing tomorrow (I hate VHDL, wasted so many hours getting the testbench to compile and run correctly).
--- Sat May 5 17:20:15 PDT 2001 ================================
+++ Sun May 6 09:13:44 PDT 2001 ================================
Goal: Get Branch Predictor Working.
I realized that I made some really stupid mistakes yesterday, like not having CLK and RESET pins into my branch predictor.
I also realized that i should not use the lower 2 bits of the PC as the index into the branch table (they're always 00).
I didn't get to finish changing the pins on the decoder in bhtable (I just realized there were bars over all of the outputs!)
Gotta go.
--- Sun May 6 10:58:57 PDT 2001 ================================
+++ Sun May 6 16:57:12 PDT 2001 ================================
Goal: GET BRANCH PREDICTION WORKING!!!!!
Okay, I've taken a 2 hour dinner break, so that doesn't count to my time total.
I've found various bugs in my branch predictor... didn't bother documenting them because this is still initial testing.
I made a fundamental design change... I'm no longer keeping track of the branch tags. Now, my branch history table entries look wimpy.
I don't know what's wrong with the testbench tests, but the original ones work fine.
Another frustrating day....IT'S STILL NOT WORKING WITH TESTBENCHES.
--- Sun May 6 23:37:26 PDT 2001 ================================
+++ Mon May 7 12:36:53 PDT 2001 ================================
Goal: debug testbench? Make branch validation unit.
I'll need 1 FF to store branch prediction result and 32 bit register to store not taken value.
Yea! I finally got the testbench to work. I made a schematic and a symbol for the testbench, changed a few things for the testbench, then tested through this.
All tests have passed thus far.
Dinner break!
--- Mon May 7 17:38:19 PDT 2001 ================================
+++ Mon May 7 18:28:52 PDT 2001 ================================
Goal: write more test cases for testbench.
Yes, it passes most of my test cases. Checks that:
1) the 2 bit predictor works - to saturation, toggling TFTF
2) updates can happen while another entry is being accessed
3) instructions that should collide in the branch history table actually affect the same entry
4) non-branch instructions don't cause branches
5) both bne and beq are recognized
I have used 20 ns delays, because the components are not optimized (I'm using ALU, mux, and tristate in critical path).
I also added in testing for the untaken address and the new branch address, to make sure they were computed properly.
--- Tue May 8 00:07:35 PDT 2001 ================================
+++ Tue May 8 11:05:08 PDT 2001 ================================
Goal: Finish building branch validation unit.
Okay, I didn't build the unit yet. I was looking at Mark's schematic to see how it works. There are some questions I have of his implementation.
--- Tue May 8 12:09:07 PDT 2001 ================================
+++ Tue May 8 15:54:04 PDT 2001 ================================
Goal: Finish building branch validation unit.
The main changes from Mark's ALU reservation station is that I've added the UNTAKEN_ADDR[31:0] and B_TAKEN value to be stored in the stations and I've changed the ISSUE[112:0] bus values that feed into each register in the reservation station.
I've also removed unnecessary pins from each reservation station and made the symbol bigger.
Here's the values from the branch issue bus, as given to me by Po:
Name numbits range
predict 1 [144]
Vjvalid 1 [143]
Vkvalid 1 [142]
OP 2 [141:140]
ROB 4 [139:136]
Vj 32 [135:104]
Vk 32 [103:72]
Qj 4 [71:68]
Qk 4 [67:64]
PC 32 [63:32]
otherPC 32 [31:0]
Here's the opcodes, from Po:
beq = 00
bne = 01
bgez = 10
bltz = 11
1 hour dinner break.
Almost done with branch validation unit, just have to fix the control. Even has squishers!
--- Wed May 9 01:38:55 PDT 2001 ================================
+++ Wed May 9 13:49:24 PDT 2001 ================================
Goal: Finish building branch validation unit.
Koichi has taken on the jump register unit.
I used Mark's RSctrlShift units, and edited it to remove the issue[84:0] pin because it's not used.
Here's the values from the jal issue bus:
Name numbits range
ROB 4 [35:32]
PC 32 [31:0]
(- 40 minutes for HKN meeting)
(- 2 hours for HKN meeting)
Just got the jal unit finished... pretty easy.
Now I'm working on the mfhi, mflo units...
Here's the values from the move issue bus:
Name numbits range
OP 1 [73]
valuevalid 1 [72]
waitMulROB 4 [71:68]
ROB 4 [67:64]
HILO 64 [63:0]
These are not in the issue bus:
mult_not_done
MulROB 4
HI 32 [63:32]
LO 32 [31:0]
Mark Chew
Mon Apr 23 17:43:41 PDT 2001 - Just brainstorming about what it's going to take.
Tue Apr 24 16:27:57 PDT 2001 - Got reservation station schematics drawn.
Wed Apr 25 16:00:48 PDT 2001 - Got framework of RS controller.
Thu Apr 26 21:49:16 PDT 2001 - Started multiply unit
Sat Apr 28 15:01:12 PDT 2001 - Working on VHDL for RS controllers
Wed May 2 23:48:03 PDT 2001 - Wrote most of the code for ALU RS controller. Still have to debug.
Fri May 4 00:23:32 PDT 2001 - Finished preliminary version of ALU RS controller. Also wrote the initial test file for it; just need to resolve technical difficulties next time.
Fri May 4 18:36:59 PDT 2001 - More stuff with the arithmetic units. Got a slt working right, but the RS controller still needs some major work.
Sat May 5 22:38:53 PDT 2001 - Got some instructions executing, but I still need to work on timing.
Tue May 8 00:10:08 PDT 2001 - Got ALU-related instructions working. They stall, request the CDB, and drive the CDB properly now, I think.
Wed May 9 01:02:19 PDT 2001 - Got Shift-related instructions working and improved the algorithm that decides which RS to launch. Now need to work on the multiplying next.
Thu May 10 07:18:49 PDT 2001 - I hate CS 152.
===============================================================================
Mon Apr 23 14:32:34 PDT 2001
Discussed project as a group. Going to get asynchronous DRAM controller working now.
Argh!!! I doesn't work. We're going to have to ask James or something about this one.
Forget it. Going to work on the reservation stations.
An RS needs: name, busy(not available), Op, Vj, Vk, Qj, Qk
It also needs some abstractions, like "source operand ready" or ...
When source operands are ready, it's going to be really hard to nullify Qj and write Vj in hardware, all at the same time.
Also, RS's need to have some way of interfacing with the CDB. Argh...this is really really complicated.
Mon Apr 23 17:43:41 PDT 2001 (3 hours)
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Tue Apr 24 15:40:33 PDT 2001
Goal: Get reservation stations moving!!
I'm not quite sure when a reservation station would be busy, but not have an OP, or have an OP, but not be busy.
Not sure how to identify each RS. For now, I'm just going to have people wire it up from the outside. So it just returns whatever name you give it.
Reservation stations done, in gates. I don't think there's a need to test yet, since everything is pretty self-explanatory and basic. The next task I need to do is build the RS controller. This would be difficult because I'm not going to know exactly the format of the instruction issues. Also, it's going to need to arbitrate and choose which RS under its domain gets to use the functional unit, if 2 RS's become ready at the same time.
Tue Apr 24 16:27:57 PDT 2001 (1 hour)
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Wed Apr 25 14:07:48 PDT 2001
Goal: Do about half of RS controller
Got framework of RS controller. Dang. This thing's complicated.
Wed Apr 25 16:00:48 PDT 2001 (2 hours)
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Thu Apr 26 15:18:30 PDT 2001
Goal: Understand the interfaces that the RS controller is going to do, and start working on some vhdl for it.
We need sets of RS's for shifts, ALU-related operations, multiplies and branches. This project is seeming as difficult as ever.
Working on multiply
Thu Apr 26 21:49:16 PDT 2001 (5.5 hours)
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Sat Apr 28 13:07:20 PDT 2001
Goal: Get working on RS controller, in VHDL.
It's coming...slowly.
Sat Apr 28 15:01:12 PDT 2001 (2 hours)
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Wed May 2 14:22:19 PDT 2001
I think the reservation stations should be more intelligent than they are now. Right now, they're just a collection of flip-flops, but I think they should be able to listen to the CDB and know when to latch stuff in, instead of relying on the RS controllers.
Ok, now a reservation station only needs to know when it can latch stuff. It can sit on the bus and just automatically know whether to listen to a valud. Still, it needs to be able to launch instructions correctly.
Wed May 2 16:06:25 PDT 2001
Wed May 2 18:47:30 PDT 2001 (minus 2.5 hours)
Back
I *think* the reservation station module is done. The RS controller just needs to raise "go" on the cycle that the execution of that instruction gets put into a functional unit, and raise "reset" for a cycle at the completion of the functional unit's execution. This changes the RS controllers big-time, but this is a good change, since it's a change for the better (simpler).
I need to ask Po what happens on a set. How do I tell what kind of set it is?
Aha! If I want to use the CDB on a specific cycle, I'm going to have to request it the cycle before that. For ALU operations, that means that I need to request during the cycle that I launch.
Ok, code for the ALU RS controller is getting filled in now. Soon, it'll just be a matter of debugging this stuff.
Wed May 2 23:48:03 PDT 2001 (7 hours)
-------------------------------------------------------------------------------
Thu May 3 15:40:56 PDT 2001
Goal: Have RS controllers done to my satisfaction, and start working on multiplier and divider units.
Aha!!! There is a SEPARATE EX and WB stage. This means that as long as I request the CDB during the EX stage, then most of the time the WB stage can go smoothly. Also, If I latch the output of the EX stage, I can pipeline everything so that the FU stays busy all the time.
A complexity problem with this is that the RS controller has to stall everything when it doesn't get the CDB. This means not letting the flip-flop get written and putting the same values into the ALU.
Remind Po that we've changed the interface, adding more information so that signed and unsigned sets will work in the ALU unit.
Changing the issue "standard" to make debugging a lot easier.
Ok, the initial test file is written. I still need to figure out the compile/fusion errors, but I think this is a good stopping point.
(minus 1.5 hours for dinner and watching Diehard)
Fri May 4 00:23:32 PDT 2001 (8 hours)
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Fri May 4 14:43:28 PDT 2001
Ok, got one instruction that came out correctly. Dang, it took forever for me to get the logic at the end right. But I still need to worry about the RS controller, which is my main task. It still doesn't seem to be conducting things the right way.
Fri May 4 18:36:59 PDT 2001 (4 hours)
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Sat May 5 10:56:19 PDT 2001
Goal: Get all the ALU-related instructions working.
Minus 2.5 hours for acupuncture.
Right now, the issue unit seems to be working OK, but the launch doesn't.
Now, the instructions are executing and coming out at Dout correctly. However I'm still having a few timing problems. One thing is, it seems like I usually have trouble executing instructions every cycle. I'm seeing a bunch of zeros between every meaningful set of values going into the ALU. Also, I'm having trouble with the CDBrequest. I need an asynchronous arbiter so that I can get the CDB the cycle AFTER I launch. However, I'm having problems with this. The request needs to happen each time I launch an instruction AND each time I have an instruction that still needs to broadcast. How to do this is not clear to me, but I'm so brain-dead from this whole day of working that I need to stop now.
Sat May 5 22:38:53 PDT 2001 (9 hours)
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Mon May 7 12:21:25 PDT 2001
Goal: Get ALU-related instructions totally working.
After 11.5 hours, it's finally working. Now going to port everything over to the shift units.
We need to improve the launch algorithm so that it picks the oldest instruction to launch. Koichi will work on this. Tomorrow, I need to do the shifter and the multiply/divide units.
Minus 4 hours for discussion and break
Tue May 8 00:10:08 PDT 2001 - (8 hours)
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Tue May 8 15:57:29 PDT 2001
Working on algorithm and the shifts.
Koichi did a good job on the algorithm so making the shifts work wasn't too much work. Yay!
Minus a lot of time for breaks.
Wed May 9 01:02:19 PDT 2001 (~ 4 hours) 53.5 hours so far
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Wed May 9 15:50:35 PDT 2001
Goal: Get multiplier and divider working.
Darn it. Giving up on mult and div.
Insight: if we eventually decide to support branch prediction, I'm going to have to modify the launch unit. It needs to not launch when the squish signal is high.
Darn it. Why am I still here?
Thu May 10 07:18:49 PDT 2001 (15.5 hours) 69 hours so far
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Manda Sutijono
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*Start: Mon Apr 23 14:12:50 PDT 2001
Met with group to talk about final project. We split up Tomasulu into parts. I'll be working on the op queue. Looks like we're making it circular, and having 2 counters, the head and tail. The size will be probably twice that of the reorder buffer. So first I'll make it 16, since Koichi's going to first make the reorder buffer 8. I'll also need to make sure to reset the counter and place it correctly for when squashing occurs.
So far I've just placed 16 32-bit registers into the op_queue schematic. Going to read more on Tomasulu tomorrow.
*End: Mon Apr 23 16:21:34 PDT 2001
Approx. total: 2 hours
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*Start: Wed Apr 25 14:16:27 PDT 2001
Working on the op queue. I also have to add when to issue instructions. I must check if there's an empty reservation station and an empty slot in the reorder buffer. If all reservations are full or reorder buffer is full, the instruction issue is stalled until both have available entries.
We just talked and now we decided that Po will handle the issuing. Also, I'll have to look and see whether an instruction is j, jal, or jr. For a jr instruction, the delay slot will be freezed until a signal comes from Po. Also, Phoebus needs another input to the PC mux for branch prediction.
*End: Wed Apr 25 16:00:12 PDT 2001
Approx. total: 2 hours
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*Start: Fri Apr 27 20:36:04 PDT 2001
Finally done with 164, so now I can concentrate on this op queue.
Haven't done much. Just put in the register enable signals that come from the head counter. I have to finish labelling tomorrow. Also have to add the datapath stuff for PC, etc.
*End: Fri Apr 27 22:20:27 PDT 2001
Approx. total: 1.5 hours
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*Start: Sat Apr 28 11:24:15 PDT 2001
Back to finish the op queue.
I remembered how to figure out the FULL and EMPTY signals - see if HEAD = TAIL, then check the previous operation. If it was an insert, that means HEAD moved, so the queue is FULL. If the prev operation was a send, so TAIL moved and the queue is empty.
Starting the op_queue symbol!
*End: Sat Apr 28 13:55:19 PDT 2001
Approx. total: 2.5 hours
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*Start: Sun Apr 29 14:48:56 PDT 2001
Finish making op_queue symbol, and check that I did full/empty signals correctly, then test whole queue.
A little tricky testing because I found out I was using the old tri state buffer, which was low-enabled. I switched to the hi-enabled one and then I was getting stuff for instr_out when I asserted send signal. Oh, and I also forgot to put the squash pin to the symbol. That signal also affects the empty signal, so I fixed that too.
*End: Sun Apr 29 17:15:31 PDT 2001
Approx. total: 2.5 hours
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*Start: Wed May 2 14:05:38 PDT 2001
Meeting with group today to talk about stuff. I think I'll try and think/start on victim cache.
Ok, now I'm going to work on the integer unit. It takes in 2 32-bit inputs, plus a 5-bit operation input. The first 3 bits are to specify the operation for the ALU. The last 2 bits enable which output to take: slt, sltu, or the alu.
*End: Wed May 2 17:14:16 PDT 2001
Approx. total: 3 hours
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*Start: Thu May 3 12:43:03 PDT 2001
Going to try and get the lw/sw unit going. I got that done, and so it takes in 2 inputs, the offset and then the address. It outputs the sum of the sign-extended address with the address.
*End: Thu May 3 13:56:29 PDT 2001
Approx. total: 1 hours
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*Start: Thu May 3 17:00:13 PDT 2001
I'm going to think about the PC FSM. When to freeze it, etc. So I finally got that working. I messed up because I put ground incorrectly into the flip flop. So what the pcwrite symbol does is send hi if the instruction is not jr. If it is, then the pcwrite will be low, so it can freeze the pc. Only when the go signal is asserted (which will come from Po's stuff) will the pcwrite signal be asserted.
*End: Thu May 3 20:22:48 PDT 2001
Approx. total: 3 hours
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*Start: Fri May 4 13:35:28 PDT 2001
Koichi needs me to modify the op queue. Now it needs to hold the PC, so I need more 32-bit registers. After I finish with that, I'll try and start on the victim cache.
I started to place the some units into the tomasulo datapath, such as mux and reg for PC, op queue, integer unit, shifter, and lw/sw unit. Now I'm going to make a symbol that spits out PC+4 and PC+8.
I read a bit about victim caches. They should be fully associative. When miss in cache, look at victim cache. If a hit, swap blocks with cache.
*End: Fri May 4 15:47:53 PDT 2001
Approx. total: 2 hours
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*Start: Sat May 5 10:53:36 PDT 2001
I'm reading about victim caches again. Wondering how big it should be and stuff like that. Haha, it's in the project spec. Victim cache'll be 4 cache lines.
(Took 1hr lunch break)
Oh, found an article on 152 page about victim caches. So I should read it.
I added another register to op queue, to hold the most recent instruction. This will be used to see if it's a j, jr, or jal instruction. If it's jr, then it should disable the write_pc signal, freezing the pc. If it's a j or jal instruction, it will select that address from the pc mux. So I added a j/jal unit that detects for j and jal instructions.
*End: Sat May 5 20:03:47 PDT 2001
Approx. total: 7.5 hours
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*Start: Tue May 8 17:31:22 PDT 2001
Going to add more stuff to op queue for branch prediction. Need 32 bit registers for each slot and flip-flops also.
Took 1hr break.
I added another input for pc to the op_queue. I also tested the tomasulo datapath with just the pc stuff, op queue, cache and dram. Looks good.
*End: Wed May 9 01:31:44 PDT 2001
Approx. total: 7 hours
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*Start: Wed May 9 11:02:46 PDT 2001
Um, tested the op queue again.
Worked on report, started on presentation slides.
Took 30min break.
*End: Wed May 9 14:47:23 PDT 2001
Approx. total: 3 hours
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*Start: Wed May 9 20:57:01 PDT 2001
Guess I'll work on slides and more of report.
*End: Thu May 10 07:13:38 PDT 2001
Approx. total: 10 hours
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Koichi Tsunoda
----------------------------------------------------------------------
Hours: 4.5
Mon Apr 23 14:00:46 PDT 2001
Met with my group to talk about the details of what we are going to implement.
Mon Apr 23 16:11:11 PDT 2001
We decided on what, and split the work up. I am going to work on the reorder buffer aspect of our processor.
Mon Apr 23 18:23:00 PDT 2001
Still in the process of designing the reorder buffer.
Total hours so far: 4.5
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Hours: 1
Tue Apr 24 12:51:19 PDT 2001
Dropped by to work on the reorder buffer again.
Tue Apr 24 14:00:01 PDT 2001
Still working on the datapath. Finished the Buffer-full logic. Now working on the datapath that will allow us to add an entry, and commit the instruction.
Class for now.
Total hours so far: 5.5
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Hours: 7.5
Tue Apr 24 17:40:00 PDT 2001
Came in. Datapath time.
Wed Apr 25 01:00:55 PDT 2001
Datapath is hard. Lots of issues came up so need to talk about it with members later.
Total hours so far: 13
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Hours: 3.75
Wed Apr 25 14:36:59 PDT 2001
Lab time.
Wed Apr 25 18:15:14 PDT 2001
Working on the renaming part. Given the source, I want to be able to give a ROB # if it's in there. Gotta go for now. Will be back later.
Total hours so far: 16.75
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Hours: 5.25
Wed Apr 25 20:44:51 PDT 2001
Came back. Working on the renaming part still.
Wed Apr 25 22:27:19 PDT 2001
Done with the renaming part. Now, I will make a tester for it.
Thu Apr 26 01:56:56 PDT 2001
Woohoo! Got the renaming part working. Done and tested with a testing component. Time to go home!!!
Total hours so far: 22
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Hours: 2
Thu Apr 26 14:01:44 PDT 2001
Starting to work on the ROB again.
Thu Apr 26 16:04:01 PDT 2001
Gotta go for now. Working on the value output for the ROB.
Total hours so far: 24
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Hours: 6.5
Thu Apr 26 19:09:59 PDT 2001
Came in with a surprise of MORE things to do for ROB. Yeah. Need to handle stuff for hi and lo registers.
Fri Apr 27 01:42:43 PDT 2001
Figured out a lot but still not done. Gotta do the controls and talk about the lw unit with mark later. Think everything else is fine...but not sure...
Total hours so far: 30.5
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Hours: 3
Fri Apr 27 14:10:52 PDT 2001
Will start working on the controls for the issuing aspect.
Fri Apr 27 19:41:19 PDT 2001
Food time. Making the symbol for the ROB slots. After this, I can actually work on the ROB itself. Too many pins!!!
Total hours so far: 33.5
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Hours: 1.25
Fri Apr 27 21:07:00 PDT 2001
Back to work!
Fri Apr 27 22:22:11 PDT 2001
Will work on commit controller tomorrow.
Total hours so far: 34.75
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Hours: 3
Sat Apr 28 11:08:59 PDT 2001
Back to the lab. Woohoo~. Gotta work on the commit controller.
Sat Apr 28 14:00:31 PDT 2001
Go for now. Now gotta add all the ROB slots into it and make the actual ROB.
Total hours so far: 37.75
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Hours: 2
Sat Apr 28 18:31:59 PDT 2001
I will now try to make the actual ROB stuff (with the ROB slots all wired up).
Sat Apr 28 20:27:53 PDT 2001
Blah blah. No. I'm going to worry about the LW/SW stuff more seriously later. I have to out put RT_VALUE_VALID and RS_VALUE_VALID and I should (that is, SHOULD) be done with the ROB. So I can start testing. yeah.
Total hours so far: 39.75
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Hours: 3.5
Sun Apr 29 14:28:23 PDT 2001
I will add the two signals that I said that I need to add. And then finish up the ROB.
Sun Apr 29 17:05:19 PDT 2001
Got the ROB finished. Now, let me connect the controllers, and then make a testing component via VHDL.
Sun Apr 29 18:02:11 PDT 2001
I decided that making a testing component for ROB is kind of long and tedious and annoying. Therefore, I will make a CMD file which will test it. But that's when I come back next time.
Total hours so far: 43.25
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Hours: 4
Wed May 2 14:29:53 PDT 2001
Back to lab. Now going to test ROB.
Wed May 2 18:35:11 PDT 2001
Gotta go for now. But remember to check the CDB_WRITE_VALUE thing. It's writing to all of it and need to fix it but...weird.
Total hours so far: 47.25
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Hours: 3
Wed May 2 21:45:00 PDT 2001
Back. Testing.
Thu May 3 00:49:11 PDT 2001
The integer instruction related stuff seems to be working. I will check the stuff with multiply tomorrow. I will need to check if the multiply and integer unit finishing at the same time works too. I will do that tomorrow.
Total hours so far: 50.25
----------------------------------------------------------------------
Hours: 1.25
Thu May 3 12:43:12 PDT 2001
More testing.
Thu May 3 14:00:00 PDT 2001
Class!
Total hours so far: 51.5
----------------------------------------------------------------------
Hours: 4.75
Thu May 3 17:00:05 PDT 2001
About to start checking the sw/lw related stuff. I still have to do the squishing thing for the misprediction but I'll take care of it later. For now, I will do this.
Thu May 3 20:31:33 PDT 2001
Food.
Thu May 3 21:14:55 PDT 2001
Back.
Thu May 3 22:36:35 PDT 2001
Got the main things tested. Seems like it's working fine. Still have couple more things to do. Gotta take care of branch thing and other junks.
Total hours so far: 56.25
----------------------------------------------------------------------
Hours: 2
Fri May 4 13:55:33 PDT 2001
I will make a monitor for the final thing right now. Just have to modify the old one we have to make it work with the new one.
Fri May 4 15:50:11 PDT 2001
Time to stop.
Total hours so far: 58.25
----------------------------------------------------------------------
Hours: 7.75
Sat May 5 10:59:59 PDT 2001
Test my monitor.
Sat May 5 11:23:44 PDT 2001
Monitor seems to be fine. Now, I will fix up the Asynch-dram controller.
Sat May 5 12:30:11 PDT 2001
Food
Sat May 5 13:43:53 PDT 2001
Back.
Sat May 5 20:06:21 PDT 2001
Gotta take care of jump instruction. Don't forget. But super-semi-async-dram controller seems to be fine :)
Total hours so far: 66
----------------------------------------------------------------------
Hours: 10
Mon May 7 13:18:55 PDT 2001
I still have to take care of jump, branch, lw in the ROB.
But I will work on the whole tomasulo datapath. I will take what Manda worked on and try to find out what we're still missing.
Tue May 8 01:37:11 PDT 2001
Think the ROB is pretty much done. We were going to keep the lw seperate from ROB but I think it's better to add it to the ROB. jump and branch is taken care of now. Wow. 12 hours - time for dinner - time for tv.
Total hours so far: 76
----------------------------------------------------------------------
Hours: 1
Tue May 8 12:46:14 PDT 2001
Back to work.
Tue May 8 13:49:33 PDT 2001
Finished the lw related utility. Therefore, I am done. Not. Now I will have to try to put everything together...figure out what's missing...and then work on that. We MUST get some instructions running today.
Total hours so far: 77
----------------------------------------------------------------------
Hours: 7
Tue May 8 15:32:59 PDT 2001
Back. Will test the lw/sw related unit.
Tue May 8 17:33:19 PDT 2001
Worked on an algorithm which will choose who's going to be issued next. It makes sure that the oldest one that is available gets issued next. Haven't tested the lw/sw unit yet. I will test that next perhaps.
Tue May 8 21:27:22 PDT 2001
Got the algorithm for choosing the right instruction to launch done. Now, I will help get the whole tomasulo thing working.
Tue May 8 21:51:19 PDT 2001
Looking good. Got the memory thing ported.
Tue May 8 23:01:51 PDT 2001
Got the integer related stuff ported.
Tue May 9 01:31:23 PDT 2001
Time to jet for now...
Total hours so far: 84
----------------------------------------------------------------------
Hours: .5
Tue May 9 11:04:32 PDT 2001
Back.
Tue May 9 11:43:23 PDT 2001
Eat. Making the JR unit.
Total hours so far: 84.5
----------------------------------------------------------------------
Hours: 2.5
Tue May 9 12:20:11 PDT 2001
Back.
Tue May 9 14:50:51 PDT 2001
Commencement.
Total hours so far: 87
----------------------------------------------------------------------
Hours:
Tue May 9 18:48:01 PDT 2001
Back. JR again.
Total hours so far:
----------------------------------------------------------------------
Posu Yan
====================================================================
Fri Apr 27 13:57:42 PDT 2001
- starting to make carry look ahead adder
Fri Apr 27 16:02:33 PDT 2001
- starting squasher thing
- revised the algorithm
Fri Apr 27 18:15:26 PDT 2001
- finished the squasher thing
====================================================================
Sat Apr 28 13:28:56 PDT 2001
- slightly modifying squasher
Sat Apr 28 15:07:23 PDT 2001
- starting decode for issuer.. trying to decode everything in parallel
Sat Apr 28 18:54:02 PDT 2001
- finished most of the instruction decodes
====================================================================
Wed May 2 13:34:21 PDT 2001
- going to finish instruction decodes.. not sure about what kind of FSM i need, so i'll hold off on that
Wed May 2 19:06:10 PDT 2001
- more or less finished decode... not completely sure where jumps, loads are going (their own station?)
====================================================================
Sat May 5 12:45:24 PDT 2001
- finishing up issuer
Sat May 5 17:18:48 PDT 2001
- pretty much finished with issuer.. not completely sure if i need a state machine in it tho
- i'll test this tomorrow
====================================================================
Sun May 6 16:44:44 PDT 2001
- starting to do final test of issuer, then finalize the data format
Sun May 6 17:13:05 PDT 2001
- finished testing.. it works, now finalizing data formats
Sun May 6 18:00:52 PDT 2001
- pretty much done, just need to add some more interface signals with ROB
====================================================================
Mon May 7 14:27:42 PDT 2001
- making final changes to issuer
Mon May 7 15:30:56 PDT 2001
- creating vhdl component to output for invalid instructions
Mon May 7 16:37:02 PDT 2001
- finished vhdl complainer component
Mon May 7 17:20:36 PDT 2001
- starting to design CDB arbiter
====================================================================
Mon May 7 18:38:25 PDT 2001
- i think i've got the arbiter FSM structure, it's more high level than the other arbiter, i think i'll need some higher level comparators and adders
Mon May 7 19:08:42 PDT 2001
- starting to make a one hot adder in vhdl, it should need 16 inputs, but only 8 outputs
Mon May 7 23:58:22 PDT 2001
- finished cdb arbiter, gonna test it tomorrow
====================================================================
Tue May 8 13:15:38 PDT 2001
- starting arbiter testing
Tue May 8 13:36:19 PDT 2001
- arbiter works fine! no bugs at all
- starting to create symbol
Tue May 8 14:02:32 PDT 2001
- arbiter is done!... although may need to add some data muxing, depends on how mark wants to do it
====================================================================
Tue May 8 17:01:44 PDT 2001
- starting to make lw/sw reservation station unit
Tue May 8 22:12:12 PDT 2001
- this lw/sw thing is much more complicated than i thought... might have to rewrite it completely
Wed May 9 01:35:12 PDT 2001
- argggggggghhh, i've got most of the datapath for lw/sw.. can't think right now so i'll do the control tomorrow
====================================================================
Wed May 9 14:04:55 PDT 2001
- starting to make PC fsm... it's much more complicated than we thought
Wed May 9 17:13:12 PDT 2001
- i think i'm finished with the PC fsm.. it's not even an fsm, just a combinational logic controller
- i'll go back to working on the lw/sw unit
====================================================================
Wed May 9 18:34:51 PDT 2001
- going to need lots of arbiters in the lw/sw unit.. but i have a pretty good idea of how i'm going to do it
Appendix II – Schematics:
Operation Queue
[pic]
[pic]
[pic]
[pic]
[pic]
[pic]
• Reorder Buffer Slot
[pic]
• Reorder Buffer
[pic]
[pic] [pic]
[pic]
• MultROB
[pic]
• Squasher
[pic]
• ROB Oracle
[pic]
[pic]
[pic]
[pic]
[pic]
[pic]
• Address to ROB
[pic]
[pic]
• Address to ROB Slot
[pic]
• J/JR/JAL Detector Unit
[pic]
• Reservation Station
[pic]
• Common Data Bus Arbiter
[pic]
• Common Data Bus Arbiter FSM
[pic]
• Carry Lookahead Adder
[pic]
[pic]
[pic]
• Full Adder
[pic]
• JR Unit
[pic]
• Integer Unit
[pic]
[pic]
[pic]
[pic]
[pic]
• Squasher
[pic]
• Issuer
[pic]
[pic]
[pic]
[pic]
[pic]
• PC FSM
[pic]
[pic]
[pic]
• Tomasulo Datapath
[pic]
[pic]
[pic]
[pic]
Appendix III – VHDL Files
Complainer
library pack1076;
use pack1076.pack1076.all;
use std.textio.all;
entity complainer is
port (clk: in vlbit;
invalid: in vlbit);
end complainer;
architecture behavior of complainer is
begin -- behavior
complainer_process: process
begin
wait until prising(clk);
if (invalid = '1') then
assert false report "invalid instruction!!" severity error;
end if;
end process;
end behavior;
Monitor
library pack1076;
use pack1076.pack1076.all;
use std.textio.all;
entity monitor is
port(signal CLK : in vlbit;
signal INVALIDATE : in vlbit;
signal PC : in vlbit_1d(31 downto 0);
signal INSTRUCTION : in vlbit_1d(31 downto 0);
signal VALUE : in vlbit_1d(31 downto 0);
signal MFHI : in vlbit_1d(31 downto 0);
signal MFLO : in vlbit_1d(31 downto 0);
signal MEM_ADDRESS : in vlbit_1d(31 downto 0));
end monitor;
architecture behavior of monitor is
function vec32tohex(vec: vlbit_1d) return string is
variable str: string(10 downto 1);
variable lo: integer;
variable hi: integer;
begin
for i in 1 to 8 loop
lo := (i-1)*4;
hi := ((i-1)*4)+3;
if(vec(hi downto lo) = "0000") then
str(i) := '0';
elsif(vec(hi downto lo) = "0001") then
str(i) := '1';
elsif(vec(hi downto lo) = "0010") then
str(i) := '2';
elsif(vec(hi downto lo) = "0011") then
str(i) := '3';
elsif(vec(hi downto lo) = "0100") then
str(i) := '4';
elsif(vec(hi downto lo) = "0101") then
str(i) := '5';
elsif(vec(hi downto lo) = "0110") then
str(i) := '6';
elsif(vec(hi downto lo) = "0111") then
str(i) := '7';
elsif(vec(hi downto lo) = "1000") then
str(i) := '8';
elsif(vec(hi downto lo) = "1001") then
str(i) := '9';
elsif(vec(hi downto lo) = "1010") then
str(i) := 'A';
elsif(vec(hi downto lo) = "1011") then
str(i) := 'B';
elsif(vec(hi downto lo) = "1100") then
str(i) := 'C';
elsif(vec(hi downto lo) = "1101") then
str(i) := 'D';
elsif(vec(hi downto lo) = "1110") then
str(i) := 'E';
elsif(vec(hi downto lo) = "1111") then
str(i) := 'F';
else
str(i) := 'X';
end if;
end loop;
str(9) := 'x';
str(10) := '0';
return str;
end;
function vec16tohex(vec: vlbit_1d) return string is
variable str: string(6 downto 1);
variable lo: integer;
variable hi: integer;
begin
for i in 1 to 4 loop
lo := (i-1)*4;
hi := ((i-1)*4)+3;
if(vec(hi downto lo) = "0000") then
str(i) := '0';
elsif(vec(hi downto lo) = "0001") then
str(i) := '1';
elsif(vec(hi downto lo) = "0010") then
str(i) := '2';
elsif(vec(hi downto lo) = "0011") then
str(i) := '3';
elsif(vec(hi downto lo) = "0100") then
str(i) := '4';
elsif(vec(hi downto lo) = "0101") then
str(i) := '5';
elsif(vec(hi downto lo) = "0110") then
str(i) := '6';
elsif(vec(hi downto lo) = "0111") then
str(i) := '7';
elsif(vec(hi downto lo) = "1000") then
str(i) := '8';
elsif(vec(hi downto lo) = "1001") then
str(i) := '9';
elsif(vec(hi downto lo) = "1010") then
str(i) := 'A';
elsif(vec(hi downto lo) = "1011") then
str(i) := 'B';
elsif(vec(hi downto lo) = "1100") then
str(i) := 'C';
elsif(vec(hi downto lo) = "1101") then
str(i) := 'D';
elsif(vec(hi downto lo) = "1110") then
str(i) := 'E';
elsif(vec(hi downto lo) = "1111") then
str(i) := 'F';
else
str(i) := 'X';
end if;
end loop;
str(5) := 'x';
str(6) := '0';
return str;
end;
function vec2intstr(vec: vlbit_1d) return string is
variable stmp: string(2 downto 1);
variable itmp: integer;
begin
itmp := v1d2int(vec);
for i in 1 to 2 loop
case (itmp mod 10) is
when 0 =>
stmp(i downto i) := "0";
when 1 =>
stmp(i downto i) := "1";
when 2 =>
stmp(i downto i) := "2";
when 3 =>
stmp(i downto i) := "3";
when 4 =>
stmp(i downto i) := "4";
when 5 =>
stmp(i downto i) := "5";
when 6 =>
stmp(i downto i) := "6";
when 7 =>
stmp(i downto i) := "7";
when 8 =>
stmp(i downto i) := "8";
when OTHERS =>
stmp(i downto i) := "9";
end case;
itmp := itmp / 10;
end loop;
return stmp;
end;
function toString(dumb: string) return string is
begin
return dumb;
end;
begin
monitor: process
variable outputLine : line;
variable opcode : integer;
variable funct : integer;
variable destR : string(3 downto 1);
variable sourceR1 : string(3 downto 1);
variable sourceR2 : string(3 downto 1);
variable instr_addr : string(10 downto 1);
variable destRData : string(10 downto 1);
variable immed : string(6 downto 1);
variable shiftAmt : string(2 downto 1);
variable bz : integer;
variable mfhiData : string(10 downto 1);
variable mfloData : string(10 downto 1);
constant RTYPE_OP : integer := 0;
constant ADDIU_OP : integer := 9;
constant LW_OP : integer := 35;
constant LUI_OP : integer := 15;
constant SW_OP : integer := 43;
constant BEQ_OP : integer := 4;
constant BNE_OP : integer := 5;
constant BZ_OP : integer := 1; -- for bgez and bltz instructions
constant ANDI_OP : integer := 12;
constant ORI_OP : integer := 13;
constant XORI_OP : integer := 14;
constant SLTI_OP : integer := 10;
constant SLTIU_OP : integer := 11;
constant J_OP : integer := 2;
constant JAL_OP : integer := 3;
constant ADDU_FUNCT : integer := 33;
constant SUBU_FUNCT : integer := 35;
constant AND_FUNCT : integer := 36;
constant OR_FUNCT : integer := 37;
constant XOR_FUNCT : integer := 38;
constant SLL_FUNCT : integer := 0;
constant SRL_FUNCT : integer := 2;
constant SRA_FUNCT : integer := 3;
constant SLT_FUNCT : integer := 42;
constant SLTU_FUNCT : integer := 43;
constant JR_FUNCT : integer := 8;
constant MFHI_FUNCT : integer := 16;
constant MFLO_FUNCT : integer := 18;
constant MULTU_FUNCT : integer := 25;
constant BGEZ_RT : integer := 1;
constant BLTZ_RT : integer := 0;
begin
wait until pfalling(CLK);
if INVALIDATE = '1' then
opcode := vec2int(INSTRUCTION(31 downto 26));
funct := vec2int(INSTRUCTION(5 downto 0));
instr_addr := vec32tohex(PC);
destRData := vec32tohex(VALUE);
mfhiData := vec32tohex(MFHI);
mfloData := vec32tohex(MFLO);
sourceR1(2 downto 1) := vec2intstr(INSTRUCTION(25 downto 21));
sourceR1(3) := 'r';
write(outputLine, toString(instr_addr & ": "));
case opcode is
when RTYPE_OP =>
sourceR2(2 downto 1) := vec2intstr(INSTRUCTION(20 downto 16));
sourceR2(3) := 'r';
destR(2 downto 1) := vec2intstr(INSTRUCTION(15 downto 11));
destR(3) := 'r';
shiftAmt := vec2intstr(INSTRUCTION(10 downto 6));
case funct is
when ADDU_FUNCT =>
write(outputLine, toString("addu "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SUBU_FUNCT =>
write(outputLine, toString("subu "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when AND_FUNCT =>
write(outputLine, toString("and "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when OR_FUNCT =>
write(outputLine, toString("or "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when XOR_FUNCT =>
write(outputLine, toString("xor "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SLL_FUNCT =>
write(outputLine, toString("sll "));
write(outputLine, toString(destR & "," & sourceR2 & "," & shiftAmt));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SRL_FUNCT =>
write(outputLine, toString("srl "));
write(outputLine, toString(destR & "," & sourceR2 & "," & shiftAmt));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SRA_FUNCT =>
write(outputLine, toString("sra "));
write(outputLine, toString(destR & "," & sourceR2 & "," & shiftAmt));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SLT_FUNCT =>
write(outputLine, toString("slt "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SLTU_FUNCT =>
write(outputLine, toString("sltu "));
write(outputLine, toString(destR & "," & sourceR1 & "," & sourceR2));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when JR_FUNCT =>
write(outputLine, toString("jr "));
write(outputLine, toString(sourceR1));
when MFHI_FUNCT =>
write(outputLine, toString("mfhi "));
write(outputLine, toString(destR));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when MFLO_FUNCT =>
write(outputLine, toString("mflo "));
write(outputLine, toString(destR));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when MULTU_FUNCT =>
write(outputLine, toString("multu "));
write(outputLine, toString(sourceR1 & "," & sourceR2));
write(outputLine, toString(" HI=" & mfhiData));
write(outputLine, toString(", LO=" & mfloData));
when OTHERS =>
write(outputLine, toString("UNKNOWN FUNCT"));
end case;
when OTHERS =>
destR(2 downto 1) := vec2intstr(INSTRUCTION(20 downto 16));
destR(3 downto 3) := "r";
immed := vec16tohex(INSTRUCTION(15 downto 0));
case opcode is
when ADDIU_OP =>
write(outputLine, toString("addiu "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when ANDI_OP =>
write(outputLine, toString("andi "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when XORI_OP =>
write(outputLine, toString("xori "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when ORI_OP =>
write(outputLine, toString("ori "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when LW_OP =>
write(outputLine, toString("lw "));
write(outputLine, toString(destR & "," & immed & "(" & sourceR1 & ")"));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when LUI_OP =>
write(outputLine, toString("lui "));
write(outputLine, toString(destR & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SW_OP =>
write(outputLine, toString("sw "));
write(outputLine, toString(destR & "," & immed & "(" & sourceR1 & ")"));
write(outputLine, toString(" MEM[" & vec32tohex(MEM_ADDRESS) & "]=" & destRData));
when BEQ_OP =>
write(outputLine, toString("beq "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
when BNE_OP =>
write(outputLine, toString("bne "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
when BZ_OP =>
bz := v1d2int(INSTRUCTION(20 downto 16));
destR(2 downto 1) := vec2intstr(INSTRUCTION(25 downto 21));
case bz is
when BGEZ_RT =>
write(outputLine, toString("bgez "));
write(outputLine, toString(destR & "," & immed));
when BLTZ_RT =>
write(outputLine, toString("bltz "));
write(outputLine, toString(destR & "," & immed));
when OTHERS =>
write(outputLine, toString("UNKNOWN BRANCH INSTR"));
end case;
when SLTI_OP =>
write(outputLine, toString("slti "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when SLTIU_OP =>
write(outputLine, toString("sltiu "));
write(outputLine, toString(destR & "," & sourceR1 & "," & immed));
write(outputLine, toString(" R[" & destR & "]=" & destRData));
when J_OP =>
immed := vec16tohex(INSTRUCTION(25 downto 0));
write(outputLine, toString("j "));
write(outputLine, toString(immed));
when JAL_OP =>
immed := vec16tohex(INSTRUCTION(25 downto 0));
write(outputLine, toString("jal "));
write(outputLine, toString(immed));
when OTHERS =>
write(outputLine, toString("UNKNOWN OPCODE"));
end case;
end case;
writeline(output, outputLine);
end if;
end process;
end behavior;
Renamer
library pack1076;
use pack1076.pack1076.all;
entity renamer is
port(signal DIN: in vlbit;
signal DOUT: out vlbit);
end renamer;
architecture behavior of renamer is
begin
renamer : process(DIN)
begin
DOUT
NOT_SUPPLEMENTARY_DATA_READY 15) then
return -1;
else
return (x + 1);
end if;
end inc;
function vlbit_1dtoint(input : vlbit_1d) return integer is
variable x : vlbit_1d(3 downto 0) := input;
variable y : integer;
begin
case x is
when "0000" =>
y := 0;
when "0001" =>
y := 1;
when "0010" =>
y := 2;
when "0011" =>
y := 3;
when "0100" =>
y := 4;
when "0101" =>
y := 5;
when "0110" =>
y := 6;
when "0111" =>
y := 7;
when "1000" =>
y := 8;
when "1001" =>
y := 9;
when "1010" =>
y := 10;
when "1011" =>
y := 11;
when "1100" =>
y := 12;
when "1101" =>
y := 13;
when "1110" =>
y := 14;
when "1111" =>
y := 15;
when others =>
y := -1;
end case;
return y;
end;
function inttovlbit_1d(x : integer) return vlbit_1d is
variable y : vlbit_1d(3 downto 0);
begin
case x is
when 0 =>
y := "0000";
when 1 =>
y := "0001";
when 2 =>
y := "0010";
when 3 =>
y := "0011";
when 4 =>
y := "0100";
when 5 =>
y := "0101";
when 6 =>
y := "0110";
when 7 =>
y := "0111";
when 8 =>
y := "1000";
when 9 =>
y := "1001";
when 10 =>
y := "1010";
when 11 =>
y := "1011";
when 12 =>
y := "1100";
when 13 =>
y := "1101";
when 14 =>
y := "1110";
when 15 =>
y := "1111";
when others =>
y := "XXXX";
end case;
return y;
end;
constant numOfStations : integer := 16;
type queue is array((numOfStations-1) downto 0) of integer;
-- initialized so that queue has not duplicates;
-- lowest address is next to be evicted
begin
RSctrlALUL:process
variable stationsNotReady : vlbit_1d((numOfStations - 1) downto 0);
variable stationsTaken : vlbit_1d((numOfStations - 1) downto 0);
variable stationsBusy : vlbit_1d((numOfStations - 1) downto 0);
variable count : integer := 0;
variable launchNum : integer := 0;
variable keepLooping : boolean := true;
variable justRequestedCDB : boolean := false;
variable requestedLongAgo : boolean := false;
variable outputline : line;
variable lastLaunched : integer := -1;
variable oldestInstr : integer := 0;
variable execQueue : queue;
variable initSetupDone : boolean := false;
variable numIssued : integer;
variable issueInQueue : boolean;
variable tempCounter : integer;
--This is where everything REALLY begins
begin
if not initSetupDone then
for i in 0 to numOfStations - 1 loop
execQueue(i) := -1;
end loop; -- i
initSetupDone := true;
end if;
wait until pfalling(CLK);
--latch a few key values
if ISSUE = '1' then
-- check and see if the LISTEN is already in the queue or not.
numIssued := v1d2int(LISTEN);
issueInQueue := false;
for i in 0 to numOfStations - 1 loop
if execQueue(i) = numIssued then
issueInQueue := true;
end if;
end loop; -- i
if not issueInQueue then
-- it was not in the queue so add it to the queue.
tempCounter := 0;
while not issueInQueue loop
if execQueue(tempCounter) = -1 then
execQueue(tempCounter) := numIssued;
issueInQueue := true;
else
tempCounter := tempCounter + 1;
assert tempCounter < numOfStations report "something is wrong in the RSctrlALUL" severity error;
end if;
end loop;
else
assert false report "this means that something that has been issued is being issued again. obviously an error." severity error;
end if;
end if;
stationsNotReady := notReady(15 downto 0);
stationsTaken := taken(15 downto 0);
stationsBusy := busy(15 downto 0);
keepLooping := true;
if ((requestedLongAgo = true) and (granted = '0')) then
-- Do this if you requested, but weren't granted
CDBreq ................
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