Electronics for Pico-Sec Detector
Electronics for Large Scale of Pico-Sec Detector
Timothy Credo, Henry Frisch, Harold Sanders and Fukun Tang
Enrico Fermi Institute, University of Chicago
Karen Byrum and Gary Drake
Argonne National Laboratory
Abstract
With the availability of a large micro-channel plate photomultiplier tube (MCP-PMT) featuring single pulse rise times in the order of 50ps and transit time spread (TTS) in the order of 25ps, it has become possible to attempt a design of a large area array detector with pico-second resolution. We see three severe problems in such a design of this system. The first is a stable and very low jitter (less then 1ps) local clock to be used as either the stop or start instance. The second is to translate the signal from the MCP-PMT as the other terminal signal. The third is to generate a meaningful signal that indicates the time interval between these events. We have selected IHP 0.25um SiGe semiconductor process (SG25H2) which features low noise and a high bandwidth to enable our design effort.
Summary
Pico-second time resolution measurement will benefit both fundamental high energy physics research and medical applications. Figure (1) shows a proposed design for a pico-second readout module. The signal from the MCP-PMT is captured through a very low time walk constant fraction discriminator to generate a “start” signal, we hope to have time walk much less than 1ps. The “stop” signal is generated by the output of a sub-ps phase lock loop (PLL) oscillator that is driven from a global system clock.
[pic]
Fig (1): Proposed Pico-second Readout Chip Diagram
A completely time-to-digital converter (TDC) includes two parts: a coarse TDC and a fine TDC. In our high energy physics application, we use the collider beam crossing clock to be a time reference. It is so called the “time-zero”. The coarse counter counts the time at a 1Ghz rate to determine the greater than 1 ns time interval of the generated elapsed time. The fine 12-bit TDC shown in figure (1) generate the final nanosecond portion with 1ps resolution.
Using the new IHP SH25H2 process that includes CMOS and very high frequency SiGe bipolar transistors, we have designed various schematics to simulate functional modules of the design. Two types of TDCs have been simulated. One is a Wilkinson type of time stretcher in which the detected time interval has been stretched 200 times to allow time interval measurement with a 0.5ps resolution by a 5GHZ 12-bit counter.
The second TDC we simulated is based on time-to-amplitude conversion (TAC). The full dynamic range is set to 1.5V, It means the maximum of 1ns input time interval is converted to a 1.5V voltage that is held in a capacitor. The TAC sensitivity will be 1.5mV/ps. With a 10-bit ADC, we can achieve 1ps time resolution.
Based on our preliminary simulation results and evaluation on both Wilkinson time stretcher type of TDC and TAC type of TDC, we predict both approaches could achieve a time resolution of 1ps.
The first chip submission will concentrate on building a stable voltage control oscillator (VCO) and a zero-crossing voltage comparator. The VCO is a key component in the construction of a low jitter phase lock loop. The fast zero-crossing voltage comparator is an important component to test. This will demonstrate that the low walk constant fraction discriminator can meet our requirements. Just the testing of these components will be a test for our program.
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DATA
Stop
Start
12-Bit TDC
SYSCLKK
1GHz PLL
CFD
MCP
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