DPD Development Plan (NDA)
Xilinx Vivado High-Level Synthesis (HLS) 工具将 C, C++,或者 SystemC 设计规范,算法转成 Register Transfer Level (RTL)实现,可综合到Xilinx FPGA。 将DSP算法快速转到RTL FPGA 实现. 将C 至 RTL时间缩短 4 倍. 基于 C 语言的验证时间缩短100倍. RTL 仿真时间缩短 3 倍. 创建一个Vivado-HLS工程 ................
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