AURIX RAM and Performance - Infineon

AURIX? RAM and Performance

April 26 2021

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TC397XX Architecture

6 MB of RAM in 20 places

Which parts should I use?

2021-04-23

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Copyright ? Infineon Technologies AG 2021. All rights reserved.

2

Agenda

1

AURIX? Architecture

2

TriCore? Architecture

3

Data Cache and Cache Coherency

4

Maximizing Performance

2021-04-23

restricted

Copyright ? Infineon Technologies AG 2021. All rights reserved.

3

Agenda

1

AURIX? Architecture

2

TriCore? Architecture

3

Data Cache and Cache Coherency

4

Maximizing Performance

2021-04-23

restricted

Copyright ? Infineon Technologies AG 2021. All rights reserved.

4

AURIX? Architecture

TC397XX XBAR0 Cluster RAM-centric view

PSPR 64K

PCACHE 32K

PSPR 64K

PCACHE 32K

PSPR 64K

PCACHE 32K

PSPR 64K

PCACHE 32K

CPU0

96K DSPR0

CPU1

96K DSPR1

CPU2

96K DSPR2

CPU3

96K DSPR3

DCACHE 16K

DMI

DCACHE 16K

DMI

DCACHE 16K

DMI

DCACHE 16K

DMI

64K dLMU0

64K dLMU1

64K dLMU2

64K dLMU3

System Resource Interconnect Bus XBAR0 (64-bit / 300 MHz)

64K DAM0

?

?

?

2021-04-23

256K LMU0

Each CPU has local Data Scratchpad Memory (DSPR) ¨C 0 wait states (CPU clocks)

Each CPU has a Distributed Local Memory Unit (dLMU) ¨C 0 cycle read, 2 write

Accessing memories over the SRI bus is slower

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Copyright ? Infineon Technologies AG 2021. All rights reserved.

5

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