Wincupl Tutorial



Wincupl TutorialRevision 01-December 2015Larry D. OwensChanges from initial version (unnumbered) Add page numbers to facilitate editsPage 8-changed operator between Cin and Din from $ to & to reflect the AND operation.The name of the device in the sample header on page 6 is changed from V750C to v750c as reflected in the wincupl compiler.Many of the initial problems with the development process concerned configuration management (Where is the project located? Where is the JED file? etc.). To alleviate such problems I have taken the industry approach of creating a “working directory” within which all PLD designs will reside. Also since the student may be working on one of many computers, I have suggested that the working directory be created on the same EEPROM the student will use to transport the compiled project to the burner. In this manner the project resides in the hands of the student and is not constrained to any single computer.Rather than use dialog boxes I have chosen to use the Device Dependent Compile option available as an icon at the top of the screen to eliminate some of the previous confusion.WINCUPL TutorialINTRODUCTION:WinCUPL is a language designed to support the development of PLDs (Programmable Logic Devices). The language may be used for Combinatorial Circuits (time-independent) and Sequential Circuits (time-dependent). An un-programmed PLD used for Combinatorial Development is shown here:And the same PLD having been programmed to implement F=ABC* + A*BCIs shown here (disconnected inputs are treated as 0’s)THE DEVELOPMENT PROCESSThe PLD development process (briefly) follows the following steps:Follow the steps outlined in this tutorial to create a working directory and the source code for your design. Initially the PLD (the “device”) may either be specified or unspecified. The unspecified device mode allows the designer to try various PLDs to see which is “best”. In this tutorial we will use the “with” option. The source file must be in ASCII format (ASCII is the American Standard Code for Information Interchange and is usually the default format produced by a text editor). Rather than use a standard text editor to create the source file and then import it into WINCUPL we will use the text editor built-in to WINCUPL Select the device. Compile with the device. Correct any errors until a clean compile is obtained. One of the output files produced will have the extension .JEDEC.Move the JEDEC file to a Computer connected to a Device Programmer. Insert the selected device into the device programmerDownload the compiled output and program the devicePlace the programmed PLD on a prototype board, wire and test.WINCUPL Source CodeLike all programming languages, WINCUPL has a specific source format, and uses specific words and phrases. A template for a WINCUPL source program designed to implement a combinatorial function specified as Boolean Equations is shown below:/*************************//* Title Block *//*************************/Name ;/*Header*/PartNo ;Date ;Revision ;Designer ;Company ;Assembly ;Location ;Device ;/* *************** INPUT PINS *********************/PIN = ; /* */ PIN = ; /* */ /* *************** OUTPUT PINS *********************/PIN = ; /* */ /*************Logic Equations*********************/ Comments-As most programming languages, WINCUPL makes liberal use of comments inserted into the source code by the designer. For WINCUPL, a comment begins with the two character sequence /* and ends with the opposite sequence */Statements-Each statement (pin assignment or Boolean equation) is terminated with a semicolon.Reserved Words and Symbols-WINCUPL has a set of words which may NOT be used by the programmer in assignments or equations. In addition WINCUPL has a set of symbols which also may NOT be used by the programmer. These are:As such, an input variable labeled MACRO or an output labeled OUT would not be allowed. WINCUPL template-a WINCUPL program used to implement Combinatorial Functions expressed as Boolean equations might have the following general format:TITLE BLOCKHEADERINPUT PIN ASSIGNMENTSOUTPUT PIN ASSIGNMENTSPINNODE ASSIGNMENTS (optional)LOGIC EQUATIONSTITLE BLOCK-The title block is optional but good programming practice. In the title block the function of the PLD is briefly described, and where it fits into some subsystem or subassembly. The TITLE BLOCK is totally enclosed within comments. An example follows:/********************************************//*This PLD is designed to test the code development*//*process. The program merely OR’s two Boolean *//*input variables A and B and produces and output C *//******************************************/HEADERThe first non-commented section is called the Header . The format is:Name ;PartNo ;Date ;Revision ;Designer ;Company ;Assembly ;Location ;Device ;Most of the field entries are optional but the Header MUST be present. The format above shows the Header with no entries. One important non-optional field is the Device. During development it may be desirable to try the design with different PLDs in which case the Device must be specified as Virtual. Also if at some future time it is decided to simulate the design or produce the output file to actually program the device, the Device field must be correctly entered. Note: In the event you decide to simulate the program, the simulation Header must be identical to that of the design. The fields in the Header follow good engineering design practices: Name-This field identifies the part name or the function of the part-e.g., full_adder, comparator. Upon compilation the .JED file will be stored as Name.JED.PartNo-this field contains the part number. In many cases the PLD is part of a subassembly (e.g. a computer board) in which case it has a designated part number-e.g. CA0012Date-It is very important to keep track of the PLD design process. This is the usually the date of the current revision. Revision-This field tracks a design as it proceeds through the process, perhaps involving multiple iterations of the same design to improve the design or correct design errors. Normally the initial entry is given the revision number 01 and subsequent modifications increment this number.Designer-The identity of the designerCompany-The company for whom the design is being preparedAssembly-This is the (sub) assembly into which the PLD will be placed (e.g. U02 might identify the circuit board)Location-In the event the company has multiple site locations this field identifies the site in which the design was generated (e.g. Palo Alto)Device-This field identifies the target device (the PLD itself). In the event the device has not been specified and the designer would like to try different devices, the PLD device field may be specified as Virtual. In more typical situations the device is specified here. The mnemonic for the device must exactly match the CUPL mnemonic (to find the CUPL mnemonic select Options>Devices from the WINCUPL main menu, select the package -e.g. Dual In-Line Package or DIP and manufacturer-e.g. Atmel- and the device mnemonic from the pull-down list).A sample header is shown:Name test ;PartNo 00 ;Date 1/13/2015 ;Revision 01 ;Designer Student ;Company CSU Fresno ;Assembly None ;Location ;Device v750c ;CUPL Assignment StatementsLike many programming languages CUPL utilizes Assignment Statements for much of the source coding. The assignment may be to associate an input with a particular input pin, associate an output with an output pin, or express the Boolean relationship between variables, inputs or outputs. The form of an assignment statement for a Pin:Pin Number (or Expression) is assigned to Identifier;An example of a Pin Assignment Statement is:PinPin Number=Identifier;Pin 4 = _inputa; /* comment*/KeywordPin NumberIs Assigned toidentifierterminatorAn example of a Logical (Boolean) Assignment is:Aout= !Bin #(Cin&Din); /* Boolean Meaning Ain= (Bin*) OR (Cin AND Din) */Each of the fields is separated by whitespace (a Tab in this case); there is one assignment statement per line; the assignment statement is terminated by a semicolon. An (optional) comment may be included. The equations are evaluated from left to right using the usual Boolean precedence rules. Parentheses may be used to force specific precedence or to make the statements more “readable”. INPUT and OUTPUT PIN ASSIGNMENTSIn the next two fields the relationships between the device inputs and outputs (the pin numbers) and the input and output variables are specified. The inputs and outputs also are specified via assignment statements:/* *************** INPUT PINS *********************/PIN = ; /* */ PIN = ; /* */ /* *************** OUTPUT PINS *********************/PIN = ; /* */ NODES/PINNODESIn many PLDs there are functions or logic blocks (e.g. a full adder) that are “buried” within the PLD (are not brought externally to pins but are available for use by the designer via Nodes or Pin-node statements). In the event the designer wishes to access such blocks the PINNODE or NODE assignment may be used. Our designs will not employ NODES or PINNODEs.LOGIC EQUATIONSThe last section contains the logic equations which specify the relationships between inputs and outputs (recall the input and output pin assignments identified the input and output variables and assigned them to pins). In addition the logic equations may include intermediate variables (variables assigned by the programmer but not assigned to input or output pins./*************Logic Equations*********************/The Logic equations are written as assignment statements in Boolean form. There is one Logic Assignment per line and each assignment is terminated by a semicolon. The WINCUPL Boolean operators are:Examples include:Aout = Bin # Cin; /*Aout, Bin and Cin have been assigned to pins*/Cint = Bin # Ain; /* Cint is an intermediate variable NOT assigned to a pin*/A SAMPLE SESSIONWe follow the steps to produce a compiled PLD design for an Atmel ATF750C PLD in a Dual In-Line (DIP) package designed to implement the Boolean equation:Aout=Bin + CinSetting the working directoryPrior to initiating any design for PLD implementation, a so-called “working directory” should be established. The working directory is the default directory for the storing of all files associated with a design. For our work, the working directory will be created on an EEPROM provided by the student. In this manner all files associated with a design will be available independent of the machine used in the development process.This process need be done only once. Insert the EEPROM into a USB slot and wait until it is recognized by WindowsOpen Windows Explorer (Start>All Programs>Accessories>Windows Explorer). Scroll down to highlight the EEPROM (for this exercise assume it is to be called Larry and is drive e:)-Left click to select itRight click on Larry and select New>Folder; label the New Folder PLD Designs. At this point you have created a working directory on the EEPROM which will contain all your designs and files. This directory is mobile and may be moved from machine to machine (each of which contains WINCUPL). In the next steps you will configure WINCUPL. These steps should be done or verified each time you open WinCUPL on a new computer.Open WinCUPL; a blank screen will appear. Create a link to the working directory. Select Options>WinCUPL>General and link WinCUPL to your working directory: e:>PLD Designs and OK.Create (or verify) a link to the device library. The configuration of each device available for programming is stored in a file called CUPL.DL. Select Options>Compiler>Library and view the location of the device library. Using Windows Explorer verify that the file CUPL.DL is in the library location identified by WinCUPL. If it is not you must use the WinCUPL dialog box to correctly associate the location of the device library (as specified by WinCUPL) with the actual location (as identified by Windows Explorer). To verify the correct settings select (from within WinCUPL) Options>Devices and verify that a list of devices is presented.Select the correct options for the compiled (JEDEC) file. From within WinCUPL select Options>Output File and check .JEDEC, Fuse Plot and Equations. Click Apply followed by OKYou are now ready to enter and compile your design. Step 1: For this design we assume that you have already selected the target device, the Atmel ATF750C. Lookup on the web the pinout for the ATF750C in a DIP (Dual In-Line) package. This pinout will provide information required to select input pins, select output pins, identify the CLOCK pin, etc.Step 2: Open WINCUPL. Select Options>WINCUPL and browse to the correct project directory (PLD Designs). This will be the “working directory” for this design. Select OK and all designs and all files associated with those designs will be placed in this directory.Step 3: Determine the correct mnemonic for the PLD (the ATF750C DIP package)Options>DevicesPackage Type: DIPManufacturer: AtmelDevices: ATF750CThe mnemonic found is v750c (note the case change for the letters v and c)Step 4: Close the Devices Window; select File>New>Project(Note in this simple case a “project” may not be necessary; the concept of a project however allows the designer to collect multiple related designs and simulations and is good engineering practice). In this case opening a New Project automatically opens a template for a new design within this project. A Design Properties template will be presented. Fill in the entries making certain that the device mnemonic exactly matches the selected device (v750c)Select OKIn this design there are two inputs, one output and zero pin nodes (nodes).You will be asked for the number of inputs (2), the number of outputs (1) and the number of pinnodes (0). Once these have been selected, a template for your design is presented (Note: while you could create this template using an external text editor and THEN import the file into WINCUPL it is normally more convenient to use the template features of the program).Step 5: SAVE YOUR WORK (File>Save As>OR GATE; the file will automatically be saved with a .PLD extension in the working directory PLD Designs on drive e:)-many design hours are wasted because the engineer did not save his/her work and due to unfortunate circumstances (e.g. a power outage, coffee spill on the keyboard), the entire design is lost and must be reentered. Step 6: From the chip pinout (step 1), select your input pins and output pins (for this example we choose pins 2 and 3 as our inputs and pin 19 as the output. Select identifiers for each of the inputs and outputs, making sure that none of the identifiers are keywords. Using assignment statements, fill in the INPUT PINS and OUTPUT PINS section (and potentially any comments). (P.S. Save your work). Note that the device reserves some of the pins for specific purposes (e.g. Pin 1 is CLOCK) and should be assigned only for the stated purpose).Step 7: Add a section entitled LOGIC EQUATIONS. Add an input/output assignment statement. Write the input/output relationship using the correct CUPL syntax. Make sure you terminate each assignment statement with a semicolon. (save your work).Step 8: Select Options>Compiler. Verify that the JEDEC box is selected as is the boxes for Fuse Plot and Equations. Select Apply followed by OK; the dialog box will close.Step 9: Compile your source code WITH the device: At the top of the screen there a group of icons. Scroll across until you are over the icon labeled Device Dependent Compile. It looks like this Select this icon and your compile will complete. You should receive the following dialog box if there are no errors:Of course if errors or warnings appear you must correct them prior to continuing. The error(s) will be identified in a similar dialog box as Compilation Results, each error/warning by line number.Open the JEDEC file just to take a look. File>Open>All Files>OR.JED: Note that the JEDEC file compilation has truncated the file to OR.JED. Also the compilation process has created other files such as a .doc file for import into a document such as a manual and a .sim file for input into the CUPL simulator. *******************TIP******************************************************WinCUPL stores some of the files (e.g. the .PLD) in the working directory with the prefix you selected in Step 5, while other files (in particular the .JED) are stored with the prefix specified in the NAME field in step 4; in this tutorial we have been careful to make the identifiers the same but I is possible that after several design iterations, they may have become decoupled. In such an instance the design file (*.PLD) will have a different mnemonic than the object file (*.JED)*******************************************************************************Your compiled program is ready for downloading to the target device and subsequent testing . Take the EEPROM with the JEDEC file and proceed to one of the two programmers at the rear of the laboratory.Step 9: Download to the Target Device/ProgramThere are two programming stations located at the rear of the lab. Select one, turn ON the programmer (switch on the side), load the programming software from the icon on the desktop (EMP996) and wait for a verification that the two are properly communicating (this process should take about 10 seconds and you should receive a screen message confirming communications).The target PLD itself is found in the cabinet. Each PLD has been placed on an anti-static mat (the PLD is very susceptible to static electricity and can be damaged by carrying it in the hand). Carry the device (on its mat) to the programming station. Carefully insert the device in the Universal Socket (make sure that the orientation is correct-pin 1 is at the top-left-and the base of the device is flush with the bottom of the socket). Close the Zero-Insertion Force (ZIF) socket to connect the PLD.Load the programming software from the icon on the desktopInsert the thumb drive with the compiled design (*.JED).Select Device (Device icon at the top)Select PLD, ATMEL and ATF 750COKLoad the JEDEC file from the thumb drive:Load icon at the top of the screenBrowse to the thumb driveSelect your compiled program (e.g. OR.JED)Select OPEN to load the file (you should receive Load File OK to confirm the process)Program the PLDSelect Program ICONThe device will be erased automatically (you should receive a progress message)When the device has been programmed you will receive Program OKStep 10: TestOpen the ZIF socket and carefully remove the PLD chip (best done by grasping the device by the two ends which do NOT contain pins-this will mitigate static electricity), and place on the anti-static mat. Carry the chip on the mat to the test area on your bench (The Logic Development System or LDS). Set the chip aside while the test environment is being prepared.Wire your prototype board as per your design, place the wired board on the Logic Development System at your bench, and interconnect the board (WITHOUT the chip) with the associated switches, power and ground, clock, etc. on the test station; use the Logic Probe to confirm the correct wiring of the board. Carefully insert the chip into the socket on the board, make sure the chip is in the correct location, turn ON the power and test the system. Testing usually entails matching the PLD outputs with the design equations( or next state table in the case of a sequential circuit). If the programmed device does NOT match the design you must debug the device to determine the problem(s). Unfortunately in many cases some interconnections are “inside” the PLD and cannot be probed. However if access to one or more internal points is required, there are sufficient number of available output pins on the PLD so that the internal point(s) may be brought to vacant pins for testing. This will entail creating internal NODES at the desired test location(s) and interconnecting these NODES with vacant PLD output pins. Your instructor can assist you in this process.If the tests confirm correct operation, show the working system to your lab instructor. If the system does NOT work as designed you must debug your design and return to the point in the design process where the design flaw(s) were introduced and repeat the process from that point.Step 11: Clean UP and ERASEWhen the design has been verified and demonstrated, you may clean up the workbench:Return the PLD (on its mat) to the programmer, insert in the ZIF socket and select the ERASE icon to erase the device (even though the next programming will in fact erase the device, this is good practice)Return the PLD (on its mat) to the cabinetRemove your prototype board and any interconnecting wires from the Logic Development System.Sequential Circuits/State MachinesSequential Circuits differ from combinatorial circuits in two important ways: Each circuit has a sequential (time-dependent) input called CLOCK. The circuit contains one or more memory elements called Latches or Flip-FlopsIn order to implement sequential circuits, of course, the PLD must be augmented to include flip-flops and clock interconnection. Such devices are typically referred to as Registered PLDs. The ATMEL 750C is a Registered PLD.State Machine ModelsAs described in class, the two classic models for State Machines are:Moore: In which the output depends on the current state only:InputsOutput Forming LogicCombinatorialInput Forming LogicCombinatorialMemoryFlip-FlopsAnd Mealey: In which the output depends on the current state and the current inputsInputsOutputsOutput Forming LogicCombinatorialInput Forming LogicCombinatorialMemoryFlip-FlopsWINCUPL combines these two into a single model which it uses for state machines:There are two distinct approaches for the implementation of sequential circuits in PLDs that also contain Flip-Flops (registered PLD)s: From the generic description of the state machine (usually a Next State Table) synthesize the state machine directly from this specification using a special descriptive language (“Functional” approach).From the generic description of the state machine, complete the design “off-line” incorporating mechanisms for state reduction, removal of output “glitches”, and Input and Output Forming Logic (IFL/OFL) minimization. Describe the machine as a set of components (gates, flip-flops) and their interconnection (“Structural” approach).State Machine SynthesisThe design of a State Machine begins with a formal description. Usually this description takes one of two forms:State DiagramThe State Diagram is a directed graph. As shown each state is a circle with the name of the state enclosed. Arrows between states represent state transitions. Each transition is labeled X/Y where X is the input which caused the state change and Y is the resulting output. For example if the machine is in state S0 and a 1 input is applied, the state is changed to state S1 and the output is 0.Next State TablePresent State InputA B XNext State OutputA B Y0 0 0 0 1 00 0 1 0 1 00 1 0 0 1 00 1 1 1 1 01 0 0 0 0 01 0 1 0 0 01 1 0 0 0 11 1 1 1 0 1The Next State Table presents the same information as the state diagram in tabular form. For example (from the table) if the present state is 01 and the input is X=0, the next state will be 01 and the output will be Y=0.Functional SynthesisIn the event the selected method of implementation is the Functional approach, the state machine description (State Diagram or Next State Table) must be translated into a specific formal language description. Once the machine is described using the language, a compiler translates the functional description into the implementation as specified by the PLD vendor. There are two High-Level industry standard definition languages (HDL’s) available for this approach, Verilog and VHDL. A VHDL snippet is shown for example:case LIGHTS iswhen IDLE => if HAZ='1' or (LEFT='1' and RIGHT='1') then LIGHTS <= LR3;elsif LEFT='1' then LIGHTS <= L1;elsif RIGHT='1' then LIGHTS <= R1;else LIGHTS <= IDLE;end if;when L1 => if HAZ='1' then LIGHTS <= LR3; else LIGHTS <= L2; end if;when L2 => if HAZ='1' then LIGHTS <= LR3; else LIGHTS <= L3; end if;when L3 => LIGHTS <= IDLE;when R1 => if HAZ='1' then LIGHTS <= LR3; else LIGHTS <= R2; end if;when R2 => if HAZ='1' then LIGHTS <= LR3; else LIGHTS <= R3; end if;when R3 => LIGHTS <= IDLE;when LR3 => LIGHTS <= IDLE;when others => null;end case;In addition Atmel provides a Hardware Definition Language specific for state machine implementation on its PLDs. A snippet is shown below:Sequence stpctrl {present S9 if up next S2; if down next S2; if hup next S1; if hdown next S1;present S0 if up next S2; if down next S2; if hup next S1; if hdown next S1;present S1 if up next S2; if down next S8; if hup next S2; if hdown next S8;present S2 if up next S4; if down next S8; if hup next S3; if hdown next S1;Although the syntax is a bit obtuse one can see that the description is much like a next state table in which the present and next states and their transitions are specified. You need not understand this code-it is for example only.It should be clear that the translation of this description (which is quite close to the formal specification) is relatively straightforward. In fact the HDL (Hardware Description Language) approach is that which is most-employed in industry. Unfortunately for a novice, the approach suffers from the following issues: If the design does not compile, identifying the issue(s) is non-trivial (unlike the structural approach in which case the design resembles a circuit diagram which may be debugged in a conventional manner such as the use of Multi-Sim).If the design compiles but does not “fit” into the PLD, it is unclear what (if anything) the designer could do to reduce the circuitry.If the design compiles and “fits” but does not work, debugging is extremely difficult since the specification does not resemble a circuit.In contrast the structural approach overcomes most of the difficulties identified with the functional approach but requires additional design effort (essentially the engineer is required to complete the physical design including component reduction where possible, also potentially including “test points” for debugging).In this tutorial which by nature is introductory, we will employ the structural approach. The functional approach is utilized in advanced courses such as ECE176.ATF750 enhancements to support state machinesThe classic PLD structure which is combinatorial only cannot be employed to implement state machines which by nature possess memory. As such the ‘750’ is organized as follows:As in the combinatorial implementation, knowledge of the actual architecture is not required in order to implement state machines. Instead the designer utilizes the state machine model (Mealy or Moore) for implementation. This approach involves:Combinatorial equations for the Input Forming Logic (IFL)Combinatorial equations for the Output Forming Logic (OFL)Specific identification of the individual Flip-Flops used for the memory elements (number, FF type, inputs and outputs)Clock interconnection to the Flip-FlopsFlip-Flop initialization to set the power-up stateInterconnection of the IFL to the Flip-Flop inputsInterconnection of the OFL to the Flip-Flop outputsIdentification of the Flip-FlopsThe ATF750C possesses 20 flip-flops. As in most schematic capture programs each is identified as Q followed by an integer beginning with 0. As an example if two flip-flops were to be used they would be identified as Q0 and Q1.Specification of the Flip-Flop type(s)The V750C allows only D type flip-flops. Other PLD devices may support other types (e.g. J-K, T).Interconnection of the ClockFor a synchronous state machine each flip-flop must be interconnected to the clock signal (CLK). For the AFT750 this is done in two steps: The (external) clock (called CLK in this example) must be connected to input Pin 1 of the ‘750 which is dedicated to clock. This interconnection is specified in the CUPL input section:PIN 1 = CLK; For Synchronous Operation, this clock input must be interconnected with the clock input on each flip-flop. This interconnection appears as shown (the flip-flop has been specified as Y):As an example if one flip-flop has been designated Y then the CUPL syntax would be:Y.CKMUX = CLK;Such interconnection must be specified for EACH flip-flop in the state machine.Flip-Flop Identification of the Inputs and OutputsA flip-flop D input is identified as Qx.D where x is the numerical identifier associated with the flip-flop. The flip-flop output is the flip-flop identifier itself-e.g., Qx.Flip-Flop InitializationIn many if not most state machine implementations it is important to force the initial state to some predetermined condition. This is called Initialization. WINCUPL provides two mechanisms for setting the initial state, a Synchronous Preset and an Asynchronous ResetSynchronous Preset-Each of the D flip-flops is equipped with an input pin Synchronous Preset (.SP). This pin can be connected internally to ground as follows to initialize the flip-flop:Q0.SP = ‘b’0; /*The pin Q0.SP is connected to Binary Zero or Ground*/Asynchronous Reset-Each of the D flip-flops is equipped with an input pin Asynchronous Reset (.AR). This pin can be connected to an external input (in this example called RESET) which in turn may be connected to a reset button. This is accomplished as follows (with Pin 2 assigned to RESET)Pin 2 = RESET; /*this belongs in the input section of the pin assignments*/Q0.AR = RESET /*this belongs in the state section of the logic*/IFL SpecificationThe input Forming Logic comprises a set of combinatorial equations who’s inputs may be: The actual input(s) to the State Machine (e.g. A, B); andThe outputs of the memory (e.g., Qx, Qy)The Output(s) of the Input Forming Logic are connected to the D inputs of the State Machine Memory and/or to the Output Forming LogicOFL SpecificationThe Output Forming Logic comprises a set of combinatorial equations who’s inputs may be: The actual input(s) to the State Machine (e.g. A, B); andThe output of the memory elements (e.g. Qx, Qy)The output of the Input Forming Logic.The output(s) of the OFL are the actual outputs of the State Machine (e.g. OUTPUT_1, OUTPUT_2)State Machine ExampleAs an example we implement the following state machine in an ATMEL 750C PLD using the structural approach. Some initial observations: There are two inputs A and BThere is one Output called OUTThere are two D flip-flops(arbitrarily called X and Y in which X is the upper FF.) and thus 4 states (maximum)XYFrom the circuit we may write the IFL as:Dx=ADy=BAnd the OFL as:Out=A*BQY*QX Step 1: Open WINCUPLSame process as the combinatorial exampleStep 2: Determine the correct Mnemonic for the target PLD from the Devices menu (same process as in the combinatorial example)-V750C.Step 3: Close the Devices dialog box and select New>Project. Fill in the entries as in the combinatorial example:A new dialog box will appear asking for the number of inputs, outputs and pinnodes. Recall pin 1 MUST be reserved for clock. Also note that “out” is a keyword so we re-name our output OUTPUT to prevent confusion. Also Pin 13 is reserved for Output Enable (using Registered Outputs) and should not be used for inputs/outputs. For this implementation no Pinnodes are required.Save your work (this should be repeated for each major modification or correction): Step 4: To assist in debugging bring the output of each of the flip-flops to an output pin (arbitrarily use pins 14 and 15). Step 5: Connect the clock to each flip-flop; initialize both flip-flops:Step 6: IFL and OFL equations: Include the combinatorial equations for the IFL and OFL:Step 7: Compile for the device (icon at top or select as per step 7 in the combinatorial example); correct any errors or warnings. Note that the compilation has truncated the JEDEC file to state.jed.Step 8: Complete the download and testing as described in the corresponding sections of the combinatorial circuit tutorial. For state machines it is useful in debugging to initially connect the CLOCK input to a push-button switch (push-ON, push-OFF) rather than a periodic clock. In this manner the machine may be forced to go through its next state table one clock pulse at a time. In industry this is called “single-stepping”. Once the single-stepping verifies the operation, the periodic CLOCK replaces the stepping switch.Step 9: Clean-Up and Erase-Same as in the Combinatorial Design ................
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