4. Cadence Incisive Enterprise Simulator Support

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QII53003-13.0.0

4. Cadence Incisive Enterprise Simulator Support

This chapter provides specific guidelines for simulation of Quartus? II designs with the Cadence Incisive Enterprise (IES) software. You can also refer to the following for more information about EDA simulation:

For overview and version support information, Simulating Altera Designs in the Quartus II Handbook and About Using EDA Simulators in Quartus II Help.

For detailed GUI steps, Preparing for EDA Simulation and Running EDA Simulators in Quartus II Help.

Quick Start Example (NC-Verilog)

You can adapt the following RTL simulation example to get started quickly with IES:

1. Specify your EDA simulator and executable path in the Quartus II software: set_user_option -name EDA_TOOL_PATH_NCSIM r set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"r

2. Compile simulation model libraries using one of the following:

Run NativeLink RTL simulation to compile required design files, simulation models, and run your simulator. Verify results in your simulator. Skip steps 3 through 4.

Use Simulation Library Compiler to compile all required simulation models.

Map Altera simulation libraries by adding the following commands to a cds.lib file: include ${CDS_INST_DIR}/tools/inca/files/cds.lib DEFINE _ver

Then, compile Altera simulation models manually: vlog -work r

3. Elaborate your design and testbench with IES: ncelab .r

4. Run the simulation: ncsim .r

Cadence Incisive Enterprise Guidelines

The following guidelines apply to simulation of Altera designs in the IES software.

? 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at mon/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO 9001:2008 Registered

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Simulation Tool Interfaces

Altera supports both the IES GUI and command-line simulator interfaces. To start the IES GUI, type the following command at a command prompt: nclaunchr Table 4?1 lists the ISE command-line programs supported for IES simulation.

Table 4?1. ISE Command-Line Programs

Program

ncvlog ncvhdl

ncelab ncsdfc ncsim

Function

ncvlog compiles your Verilog HDL code and performs syntax and static semantics checks.

ncvhdl compiles your VHDL code and performs syntax and static semantics checks.

Elaborates the design hierarchy and determines signal connectivity.

Performs back-annotation for simulation with VHDL simulators.

Runs mixed-language simulation. This program is the simulation kernel that performs event scheduling and executes the simulation code.

Elaborating Your Design

The simulator automatically reads the .sdo file during elaboration of the Quartus II-generated Verilog HDL or SystemVerilog HDL netlist file. The ncelab executable recognizes the embedded system task $sdf_annotate and automatically compiles and annotates the .sdo file (runs ncsdfc automatically). VHDL netlist files do not contain system task calls to locate your .sdf file; therefore, you must compile the standard .sdo file manually. Locate the .sdo file in the same directory where you run elaboration or simulation. Otherwise, the $sdf_annotate task cannot reference the .sdo file correctly. If you are starting an elaboration or simulation from a different directory, you can either comment out the $sdf_annotate and annotate the .sdo file with the GUI, or add the full path of the .sdo file.

1 If you use NC-Sim for post-fit VHDL functional simulation of a Stratix V design that includes RAM, an elaboration error might occur if the component declaration parameters are not in the same order as the architecture parameters. Use the -namemap_mixgen option with the ncelab command to match the component declaration parameter and architecture parameter names.

Back-Annotating Simulation Timing Data (VHDL Only)

You can back annotate timing information in a Standard Delay Output File (.sdo) for VHDL simulators. To back annotate the .sdo timing data at the command line, follow these steps:

1. To compile the .sdo with the ncsdfc program, type the following command at the command prompt: ncsdfc _vhd.sdo ?output r The ncsdfc program generates an .sdf.X compiled .sdo file.

1 If you do not specify an output name, ncsdfc uses .sdo.X.

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Cadence Incisive Enterprise Guidelines

2. Specify the compiled .sdf file for the project by adding the following command to an ASCII SDF command file for the project:

COMPILED_SDF_FILE = ".sdf.X" SCOPE =

Example 4?1 shows an example of an SDF command file.

Example 4?1. SDF Command File

// SDF command file sdf_file COMPILED_SDF_FILE = "lpm_ram_dp_test_vhd.sdo.X", SCOPE = :tb, MTM_CONTROL = "TYPICAL", SCALE_FACTORS = "1.0:1.0:1.0", SCALE_TYPE = "FROM_MTM";

After you compile the .sdf file, type the following command to elaborate the design: ncelab worklib.:entity ?SDF_CMD_FILE r

Disabling Timing Violations on Registers

In certain situations, you may want to ignore timing violations on registers and disable the "X" propagation that occurs (for example, timing violations in internal synchronization registers in asynchronous clock-domain crossing).

By default, the x_on_violation_option logic option applying to all design registers is On, resulting in an output of "X" at timing violation. To disable "X" propagation at timing violations on a specific register, set the x_on_violation_option logic option to Off for that register. The following command is an example from the Quartus II Settings File (.qsf):

set_instance_assignment -name X_ON_VIOLATION_OPTION OFF -to \

Simulating Pulse Reject Delays

By default, the IES software filters out all pulses that are shorter than the propagation delay between primitives. Setting the pulse reject delays options in the IES software prevents the simulation tool from filtering out these pulses. Use the following options to ensure that all signal pulses are seen in the simulation results.

Table 4?2 describes the pulse reject delay options.

Table 4?2. Pulse Reject Delay Options

Option

Description

-PULSE_R -PULSE_INT_R

Use when simulation pulses are shorter than the delay in a gate-level primitive. The argument is the percentage of delay for pulse reject limit for the path.

Use when simulation pulses are shorter than the interconnect delay between gate-level primitives. The argument is the percentage of delay for pulse reject limit for the path.

1 The -PULSE_R and -PULSE_INT_R options apply by default during NativeLink gate-level timing simulation.

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To perform a gate-level timing simulation with the device family library, type the following IES software command:

ncelab worklib.:entity ?SDF_CMD_FILE \ -TIMESCALE 1ps/1ps -PULSE_R 0 -PULSE_INT_R 0r

Viewing a Simulation Waveform

IES generates a.trn file automatically following simulation. You can use the .trn for generating the SimVision waveform view.

To view a waveform from a .trn file through SimVision, follow these steps:

1. Type simvision at the command line. The Design Browser dialog box appears.

2. In the File menu, click Open Database and click the .trn file.

3. In the Design Browser dialog box, select the signals that you want to observe from the Hierarchy.

4. Right-click the selected signals and click Send to Waveform Window.

1 You cannot view a waveform from a .vcd file in SimVision, and the .vcd file cannot be converted to a .trn file.

Simulation Setup Script Example

The Quartus II software can generate a ncsim_setup.sh simulation setup script for IP cores in your design. The script contains shell commands that compile the required device libraries, IP, or Qsys simulation models in the correct order. The script then elaborates the top-level design and runs the simulation for 100 time units by default. You can run these scripts from a Linux command shell.

To set up the simulation script for a design, you can use the command-line to pass variable values to the shell script, as illustrated in Example 4?2.

Read the generated .sh script to see the variables that are available for you to override when you source the script or that you can redefine directly in the generated .sh script. For example, you can specify additional elaboration and simulation options with the variables USER_DEFINED_ELAB_OPTIONS and USER_DEFINED_SIM_OPTIONS.

Example 4?2. Example Top-Level Simulation Shell Script for Incisive (NCSIM)

# Run script to compile libraries and IP simulation files # Skip elaboration and simulation of the IP variation sh ./ip_top_sim/cadence/ncsim_setup.sh SKIP_ELAB=1 SKIP_SIM=1 QSYS_SIMDIR="./ip_top_sim"

#Compile the top-level testbench that instantiates your IP ncvlog -sv ./top_testbench.sv

#Elaborate and simulate the top-level design ncelab top_testbench ncsim top_testbench

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Document Revision History

Document Revision History

Table 4?3 shows the revision history for this chapter.

Table 4?3. Document Revision History

Date May 2013 November 2012 June 2012 November 2011 May 2011 December 2010 July 2010

November 2009

March 2009

November 2008

May 2008

Version 13.0.0 12.1.0 12.0.0 11.0.1 11.0.0 10.0.1 10.0.0

9.1.0

9.0.0

8.1.0

8.0.0.

Changes Added note about parameter mismatch workaround. Relocated general simulation information to Simulating Altera Designs. Removed survey link. Template update. Minor editorial updates. Changed chapter title Linked to Help for Stratix V Libraries Added SystemVerilog HDL information Other minor changes throughout Changed to new document template. No change to content. Linked to Help where appropriate Minor text edits Removed Referenced Documents section Removed NativeLink information and referenced new Simulating Designs with EDA

Tools chapter in volume 3 of the Quartus II Handbook Added "RTL Functional Simulation for Stratix IV Devices" and "Gate-Level Timing

Simulation for Stratix IV Devices" sections Minor text edits Removed "Compile Libraries Using the Altera Simulation Library Compiler" Added "Compile Libraries Using the EDA Simulation Library Compiler" on page 4?5 Added "Generate Simulation Script from EDA Netlist Writer" on page 4?35 Added "Viewing a Waveform from a .trn File" on page 4?36 Added "Compile Libraries Using the Altera Simulation Library Compiler" on page 4?5. Added information about the --simlib_comp utility. Minor editorial updates. Updated entire chapter using 8?" ? 11" chapter template. Updated Table 4?1. Updated Figure 4?1. Updated "Compilation in Command-Line Mode" on page 4?9. Updated "Generating a Timing Netlist with Different Timing Models" on page 4?18. Added "Disable Timing Violation on Registers" on page 4?20. Updated "Simulating Designs that Include Transceivers" on page 4?23. Updated "Performing a Gate Level Simulation Using NativeLink" on page 4?30. Added "Generating a Timing VCD File for PowerPlay" on page 4?33. Added hyperlinks to referenced documents throughout the chapter. Minor editorial updates.

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