Procurement Specification for Intel Printed Circuit Boards
DESCRIPTION of CHANGES: See last page of spec.
Title: Intel Printed Circuit Board Procurement Specification
APPROVALS
|Owner: |David W Boggs |ISSUE DATE: |April-2010 |
|Materials: |Pan Michael |REVIEW CYCLE: |1 Year |
|Quality/Reliability: |Eric Shi |EXPIRATION DATE: |April- 2011 |
|GMPO: |Wang Yip Kong |GROUP RESP: |GMPO |
1. PURPOSE/SCOPE:
1. Purpose: To define the functional, quality, and material (i.e. visual, dimensional, physical) requirements and specifications of Intel Printed Circuit Boards. To provide manufacturing with Printed Circuit Boards that meets or exceeds applicable standards and Intel manufacturing criteria. To define Intel lot acceptance criteria and Intel quality levels.
2. Scope: This document specifies the finished product acceptance criteria for printed circuit boards designed to meet Intel requirements. This specification applies to rigid multi-layer printed boards consisting of two or more copper conductive patterns separated by an insulating epoxy glass laminate. This specification does not apply to flexible circuits, ceramic substrates, or other exotic materials.
This specification is for the procurement of printed circuit boards from the printed circuit board manufacturer and does not apply to printed board assemblies. PTP and Intel consign projects must follow this specification unless otherwise approved by Intel.
Any requirements not included in this specification shall meet the conditions specified for Performance Class 2, as defined by the IPC Association Connecting Electronics Industries.
3. This document supersedes all earlier revisions. This document replaces procurement specification 454979.
2. INDEX:
CATEGORY PARA #
Purpose/Scope 1.0
Index 2.0
Reference Documents 3.0
Definitions 4.0
Material Requirements 5.0
Visual 5.1
Dimensional 5.2
Functional 5.3
Quality Assurance Requirements 6.0
Special Requirements 7.0
Packaging/Labeling/Handling Requirements 8.0
Appendices 9.0
3. REFERENCE DOCUMENTS:
The current version of the following documents of the issue in effect on the date of the request for purchase, forms a part of this specification to the extent specified. In the event of conflict between the reference documentation, the order of precedence shall be defined by the documents below:
1. Purchase order/receiver
2. Applicable Printed Circuit Board Fabrication CAD data
3. Applicable Printed Circuit Board Fabrication Drawing / Photo Tools
4. Current Temporary Engineering Instructions (TEI)
5. Current revision of A84501 GMPO Procurement Specification for Intel Printed Circuit Boards
6. IPC Standards:
IPC-6011 Generic performance specification for PWB’s
IPC-6012 Qualification and Performance Specification for Rigid Printed Boards
IPC-6016 Qualification and Performance Specification for High Density Interconnect (HDI) layers or boards
IPC/JPCA-4104 Specification for High Density Interconnect (HDI) and Microvia Materials
IPC-T-50 Terms & definitions for interconnecting and packaging electronic circuits
IPC-A-600 Acceptability of Printed boards
IPC-7711/7721 Repair & Modification of Printed Boards & Electronic Assemblies
IPC-D-300 Printed board dimensions and tolerances
IPC-TM-650 PWB test methods manual
IPC-4101 Specification for base materials for rigid and multi-layer PWB’s
IPC-SM-840 Qualification & Performance of Permanent Polymer Coating (Solder mask) For PWB’s
IPC-MF-150 Metal foil for PWB’s
J-STD-003 Solderability tests for PWB’s
7. American National Standards Institute Standards:
ASME Y14.5 Dimensioning and Tolerancing for Engineering Drawings
ANSI/ASQ Z1.4 Sampling Procedures and Tables for Inspection by Attributes
8. Underwriters Laboratory Standard:
UL 796 Standard for Safety, Printed Wiring Boards
UL 94 Standard for Safety, Tests for Flammability of Plastic Materials
9. Intel Specifications:
405-3109 Intel Environmental and Lead-Free Solder System Requirements for Purchased Electronic Components (including Restriction on Hazardous Substances, RoHS)
BS-MTN-0001 Intel Environmental Product Content Specification
4. DEFINITIONS:
Terms and definitions used in this document are as specified in IPC-T-50. The following Intel terms are provided for clarification.
1. Annular Ring: remaining metal land surrounding a plated-through hole.
2. Barcode Block: Solid rectangles of (typically) legend ink applied to the board for adding laser etched barcodes during assembly.
3. Blind via: Plated hole open to one side of the board and terminating at an internal board layer.
4. BGA: Ball Grid Array
5. Breakaway: Synonymous with “outrigger”. A (typically) non-functional laminate area supporting two or more PCBs within the multipack that is discarded after assembly de-panelization. Also the non-functional supporting area of a uni-pack.
6. Capture Pad: Outer layer microvia pad.
7. Certificate of Conformance (C of C): A document that lists key information and data about a specific shipment and certifies that the material conforms to this procurement specification. Parameters outlined in the example of the C of C in Appendix A of this specification are to be used as the indicators for lot acceptance. NOTE: The terms Certificate of Analysis (C of A) and Certificate of Compliance are synonymous.
8. Critical to Function (CTF) parameter: A PCB characteristic defined by Intel as critical to assembly and/or function of the PCB. A Frozen CTF parameter is defined as a characteristic that meets the capability and stability requirements during development and must meet all Lot Acceptance criteria shown on the C of C on all subsequent lots. Non-frozen CTF parameters must have an improvement plan to meet capability and stability requirements approved by Intel.
9. CSP: Chip Scale Package: BGA less than 1.0 mm pitch.
10. Delamination: separation between any of the layers of the base material and/or between the base material and copper.
11. DPM = Defects per Million
12. Diameter True Position (DTP): Geometric tolerance notation describing the allowable tolerance zone (expressed as circular with given diameter) for the location of features from datum. Reference ASME Y14.5 Geometric Dimensioning and Tolerancing.
13. Element symbols:
Cu: Copper Ni: Nickel Au: Gold Ag: Silver Sn: Tin Pb: Lead
14. Encroached via: Solder mask partially covers the PTH/via metal pad up to the plated hole, but solder mask is not allowed in the hole. Design is typically nominal finished hole size plus six mils. Function is to minimize exposed metal and maximize solder mask web between adjacent vias or solder lands while leaving via barrel open for optimum processing and reliability.
15. Fiducial: A solid metal feature on the external layers of a board used for the alignment of surface mount assembly equipment.
16. Functional Land: A land required for circuit interconnection or termination.
17. Gold Fingers: Strips of conductive material that are a part of the external etch layers of a board and form a male edge-connector. The strips are normally plated with gold, but sometimes plated with other conductive material.
18. LPI: Liquid Photo Imagible Solder Mask
19. Metal Defined Pad or Land: The entire SMT/BGA/CSP land is available as a solderable surface (including edges of pads).
20. Microvia: Layer to layer interconnect that is less than 10 mils in diameter produced by laser drilling. Other methods of microvia formation are excluded from this specification for clarity. Laser via ablation is the current approved process for Intel and is the method specified within this document.
21. Microvia in pad (mVIP or μVIP): microvia placed within the solder land or pad of a SMT/BGA/CSP device.
22. Multipack: A standard Intel panel used as a carrier for either a smaller board or an array of multiple boards.
23. Non-Functional Land: A PTH land on an internal layer without a connecting trace or conductor.
24. Outrigger: Synonymous with “breakaway”. A (typically) non-functional laminate area supporting two or more PCBs within the multipack that is discarded after assembly de-panelization. Also the non-functional supporting area of a uni-pack.
25. PTP: Pass Through Pricing, Intel negotiated pricing with PCB supplier and then extend the pricing to the subcontractors who procure PCBs for integration into Intel products.
26. PWB: Printed Wire Board, which is synonymous with Printed Circuit Board (PCB).
27. Resin Coated Foil (RCF) also know as Resin Coated Copper (RCC): Thin layer of non-reinforced dielectric coated with copper typically used for redistribution layers of microvia printed circuit boards.
28. Selective Gold Plating: Any gold plated area that must be manufactured without the aid of plating bars. These gold plated features are typically located in the center regions of Intel boards, preventing standard tab plating processes.
29. Solder Mask Defined Pad or Land (SMDP): Solder mask defines the amount of solderable surface on a SMT/BGA/CSP land.
30. Solder Mask Foreign Material: Material not present by design either embedded in or attached to the surface in the solder mask.
31. Solder Mask Residue: Excess solder mask material typically from a capping or touch up repair operation.
32. Solder Mask Scratches: Disruptions in the surface of the solder mask and surrounding area due to mechanical damage.
33. Solder Mask Voids: Pinholes, scratches, or bubbles that cause an interruption in the solder mask coverage.
34. Target Pad: Inner layer microvia pad.
35. Test Point: There are two types of test points: plated through holes (PTH) and surface pads. The PTH is the most common type. It is an uncapped via that also serves as a test point. A surface test point is a conductive pad placed directly on the PCB surface.
36. True Position: The theoretically exact location of a feature established by basic dimensions. [Reference ASME Y14.5]
37. Uni-pack: A single board having material separated by tab routing or V-grooves that later will be removed from the assembly. The extra material is designed as an assembly aid.
38. Vendor Design Change Request (VDCR): A closed loop system for tracking any design changes requested by the supplier. All changes must be reviewed and signed off by Intel before start of fabrication
39. Via Cap: Intel defines as a post-solder mask via tenting process with no via barrel fill requirement.
40. Via Plug: Intel defines as a pre or post- solder mask via fill and tent process with a specified via barrel fill requirement.
5. MATERIAL REQUIREMENTS:
1. Visual Inspection:
1. Visual Inspection Method:
1. Visual inspection criteria per IPC-A-600 unless otherwise specified within this document.
2. The breakaway section of the multipack is a non-functional area however it may contain some Intel designed features. Defects found in this area, which are not associated with the Intel designed features, are considered to be acceptable if defect does not impact assembly (i.e. large solder mask voids over metal). In addition, the supplier may add features, such as coupons, provided there is no impact to Intel designated features or edge profile quality. Any changes to the breakaway require Intel notification.
2. Solder Mask
1. The areas of the board defined by CAD design shall be completely covered with green solder mask material that meets the requirements of IPC-SM-840, class 2.
2. The clearances surrounding conductive features may be modified if necessary, provided that adjacent conductors are completely covered and other requirements of this section are satisfied. Specific requirements for fiducials are covered in section 7. Refer to section 5.2 for maximum allowable solder mask clearance pad compensation.
3. Large plated-through holes (.156" and larger) may contain minor solder mask residue provided it does not reduce dimensions below the minimum hole size specification.
4. No more than one application layer of solder mask shall be permitted over the bare laminate or traces with the exception of any small areas of touch up (see section 7) and via cap overlap areas.
5. With the exception of via capping/plugging in accordance with other requirements of this section there shall be no solder mask residue in the holes.
6. Using the primary solder mask to flood vias is NOT permitted. Via cap and via plug operations require a separate operation.
7. VOIDS: Minor scratches, pinholes or voids in the solder mask which occur before surface finish application and are thus coated, shall be acceptable provided there is no exposed adjacent metal within 0.020" of the defect. Minor scratches, pinholes or voids in the solder mask which occur after surface finish application resulting in exposed copper will be acceptable provided:
1. The exposed copper area is no larger than 0.125" in any direction.
2. There is no exposed metal adjacent to the void within 0.020" or less.
8. TOUCH UP: Solder mask touchup is allowed per section 7 and to a maximum of 5% of the surface area per board side. Thickness of the touchup must not exceed 0.006” from the board surface, unless the void is closer than 0.250” from a sub 0.050” pitch SMT land or BGA pad. Under this condition, touchup thickness must not exceed 0.003” thickness.
3. Electrolytic Gold Contacts
1. Scratches, pits and dents are acceptable provided there is no exposed nickel and/or copper. Refer to IPC-600 and 6012 for additional gold finger requirements.
2. There shall be no solder residue allowed on the contact area of the gold fingers.
3. Cosmetic stains affecting more than 20% of the area of any single gold finger contact are not allowed without written permission from Intel (see example in Figure 5-6).
4. Plating Thieves
1. Unless otherwise stated on the fabrication drawing, plating thieves may be added to external layers of the board, and to the multi-pack breakaway section to achieve more uniform electrolytic plating.
2. For embedded microstrip designs, no external layer thieving is allowed within 1” of internal impedance traces on adjacent layers.
3. Metallization added shall be square pads, sized 0.050" to 0.080" and placed on 0.100" centers.
4. Layer tabs, barcode blocks and Intel logo must not be obstructed.
5. Added metal must be covered with solder mask.
6. Minimum spacing to traces/pads shall be 0.050”.
5. Legend
1. Legend shall be legible unless otherwise stated on the fab drawing.
2. Legend shall be on the primary and/or secondary side of the board, over the solder mask.
3. Legend ink on any SMT/BGA/CSP lands will be treated the same as solder mask (see sections 5.1 and 5.2)
4. If the legend design overlaps the component holes, the vendor is permitted to adjust the artwork to prevent ink from covering them. Ink will be permitted in the smaller via holes that are not used for lead attachment.
5. All legend shall be white epoxy ink and shall be non-flammable, non conductive, and non-hydroscopic.
6. Board Edges
1. There shall be no fraying of the board edges. All edges must be smooth and free of continuous burrs.
7. Via Capping for gold surface finishing
1. When via capping is required, a CAD file with the title "Via Cap" will be provided. This file will identify which vias to cap.
2. Unless otherwise specified, the following process will be followed for via capping:
1. The via capping process must occur after the final surface finish.
2. Vias will be capped from the secondary side (solder side) only.
3. The vias will be capped with an epoxy or solvent type solder mask and completely cured. Typical via cap depth is 15% – 25% of the thickness of the board. The maximum allowed via cap depth is 80%.
4. There will be no smearing of the via cap material onto any adjacent SMT pads or test points and via capping must completely cover the pad, ensuring no exposed metal.
5. 100% of the vias must be capped. Up to 5% of the vias are permitted to have broken caps that do not expose surface metal.
8. Via Plugging
1. Via plugging is required when a) an Immersion Silver or OSP surface finish is specified and b) a CAD file with the title “Via Cap” is provided, or when otherwise specified. The hole locations provided in the “Via Cap” file indicate the holes which require via plugging, in the case of the Immersion Silver or OSP finish.
2. Via plugging for Immersion Silver or OSP boards requires a separate operation from the primary soldermask coating, prior to the Immersion Silver or OSP application.
3. Boards with via plugging prior to a horizontal conveyorized Immersion Silver or OSP process must be processed with the via plug side facing up.
4. Via plugs must not protrude above the surface of the via pad.
5. A high-solids material is recommended for the via plugging to comply with requirements of Section 5.2.20
9. Microvia
1. Resin residue at the base of the microvia is not allowed (see figure 5-9).
2. Final surface finish plating within the microvia is preferred, but it is acceptable to have incomplete coverage inside the microvia.
3. Foreign material contamination inside the microvia is not allowed.
4. Microvia hole-to-pad breakout is NOT allowed on external or internal laser lands or pads.
2. DIMENSIONAL Inspection / MATERIAL CHARACTERISTICS:
All dimensions and tolerances specified herein are applicable to the finished board only. A summary of dimensional information is given in Table I. The symbols listed refer to physical descriptions shown in Figure 5-1.
TABLE I
DIMENSIONS AND TOLERANCES
|Symbol |Characteristic |Para. |
|(FIG. 5-1) | | |
| |Conductors/Lands | |
| |- Feature Size Tolerance |5.2.2 |
| |- Feature Location |5.2.5 |
|A |- Copper Thickness, Inner Layer |5.2.6 |
| |- Copper Thickness, Outer Layer |5.2.7 |
|B |Nominal Trace Width | |
| | General Reductions |5.2.2 |
| | Defect Reductions |5.2.4 |
|C |Space Reductions from Defects |5.2.11 |
|D |Min. Plated Hole to Conductor or Plane |5.2.8 |
| |Spacing | |
|E |Min. Dielectric Spacing |5.2.10 |
|F |Overall Board Thickness |5.2.13.1 |
|G |Hole Location Tolerance |5.2.12.1 |
|H |Plated Hole Dia. Tolerance |5.2.12.2 |
|I |Non-Plated Dia. Tolerance. |5.2.12.2 |
|K |Annular Ring (Min.) |5.2.12.3 |
| |Bow and Twist |5.2.13.2 |
| |Connector / Edge Bevel |5.2.13.3 |
| |PTH Copper Thickness |5.2.15.3 |
| |Final Surface Finish |5.2.16 |
| |Electrical Gold Contacts |5.2.17 |
| |Solder Mask |5.2.18 |
| |Legend |5.2.19 |
| |Board Profile |5.2.13.4 |
FIGURE 5-1: Circuit Board Basic Dimensions
1. Requirements
1. The supplier shall have and supply documented measurement procedures and proven measurement capability for the metrology used to measure and/or monitor all parameters defined in this specification and appropriate printed circuit board fabrication drawings.
2. All of the finished, unpopulated, printed circuit boards shall meet the dimensional requirements as specified in this document and mechanical drawing.
2. Conductor Feature Size Tolerance: Unless otherwise stated, conductor size tolerances and measurement locations shall be as specified in Table II. If not defined in Table II or elsewhere, the default feature size tolerance is +/-20% for features < 25 mils, and +/-5.0 mils for features > 25 mils, with respect to the design data provided by Intel.
TABLE II
CONDUCTOR SIZE TOLERANCE
|Size |Shape |Conductor Type |Trace Width or Pad |Size Tolerance |Measurement |
| | | |Pitch |(From Nominal CAD Dimension) |Location |
|0.050” |Smaller of +/-20% or +/-5 mils |Base |
|All |Rectangular |SMT Pad |< 0.050” |+0.002” / -0.0005” |Base |
|> 0.012” |Round or |SMT Pad |< 0.050” |+/- 0.0023” |Base |
| |non-rectangular | | | | |
|< 0.012” |Round or |SMT Pad |< 0.050” |+0.0005” / -0.002” |Base |
| |non-rectangular | | | | |
| |
|Measurement locations of base refer to the interface of the copper to the laminate. |
3. Plated-through hole pads smaller of +/- 20% or +/- 5 mil and internal plane clearances (anti-pads) diameter must be +/- 2 mil of their nominal CAD dimension
4. Trace Width Reductions from Defects: Any combination of edge roughness, nicks, pinholes and scratches exposing the base material shall not reduce the conductor width by more than 30% of the CAD trace width. There shall be no occurrence spanning a distance greater than the trace width. Minimum trace widths will be measured at the base laminate/foil interface.
5. Conductor Feature Location Tolerance (Outer Layers): Lands, traces, pads and other conductive features shall be located within 8 mil diameter true position (DTP) tolerance (equal to 4mil radial true position) to the design grid. Datum’s A & B on the fabrication drawing will serve as reference points for validation measurements.
6. The default, nominal, internal copper weight is 1 oz/ft2, unless otherwise specified. The minimum internal copper thickness shall be in accordance with IPC, class 2. The following values are shown for reference only.
|COPPER WEIGHT | NOMINAL THICKNESS |PROCESSED MINIMUM |
|1/2 oz/ft2 |.0007" |.0005” |
|1 oz/ft2 |.00135" |.001” |
|2 oz/ft2 |.0028" |.0022” |
7. The default, nominal, external copper weight prior to plating is 1/2 oz/ft2, unless otherwise specified. The minimum external conductor thickness after plating is 0.001”. The electrodeposited copper shall be no less than 99.5% pure, as tested by IPC-TM-650, method 2.3.15.
8. Plated through hole to conductive feature [Fig. 5-1, D] minimum spacing shall be >= 0.004”.
9. Non-plated through hole to conductive feature minimum spacing shall be >= 0.004”.
10. Dielectric Spacing [Fig. 5-1, E]: Unless otherwise specified on the drawing, the minimum dielectric spacing shall be 0.002” distance between copper-copper peaks.
11. Space Reductions from Defects: Any isolated defect shall not reduce the space by more than 30% of the CAD dimension. Defect shall not be longer than the width of the nominal space.
12. Holes and Slots
1. Hole Location Tolerance [Fig. 5-1, G]:
1. Plated-Through Holes shall be located within 8 mil (0.2mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing.
2. Non plated holes 0.200” shall be located within 12 mil (0.3mm) diameter true position (DTP) tolerance to the design coordinates as established by the A & B datums or as dimensioned on the fabrication drawing.
4. Non plated slots 50% of the hole volume. Both sides of the via hole solder mask top surface shall be visible under 10X eyepiece inspection.
2. Cracks or voids in the via plug material are allowed if they a) are not located within .005” (0.13mm) of the surface of the via plug, and b) do not touch the hole wall at any point.
3. Separation between the via plug material and the hole wall is not allowed.
21. Breakaway
1. There shall be no dimensional defects in the x, y, or z directions in the breakaway area. Unless otherwise noted, visual defects shall be acceptable provided that the dimensional requirements are met
22. Microvia
[pic]
FIGURE 5-9
1. Microvia hole diameter is defined as the laser drilled size of the hole as measured from the topside of the via (Dtop) excluding plating (see Figure 5-9).
2. Bottom hole diameter (Dbottom) shall not be less than 0.0025 inch for typical 4-5mil microvia, and smaller microvias can produce a smaller hole diameter.
3. Resin residue, as depicted in Figure 5-9, at the base of the microvia is not allowed.
4. Copper thickness of the microvia (hole wall and base) shall be minimum 0.0005 inch (0.5 mil) thick for any single point measurement.
5. Burnt Dielectric: The dielectric material directly beneath or adjacent to the inner layer laser pad shall not be melted, separated, contain voids, or otherwise damaged due to the heat generated by the laser process (see figure 5-9).
6. Enclosed voids, as illustrated in Figure 5-10, are not allowed within the microvia holes. Unless otherwise specified, the minimum opening is 0.001 inch (1 mil), when measured at the center of the microvia.
[pic]
FIGURE 5-10
3. FUNCTIONAL INSPECTION
1. Electrical
1. Measurement equipment used shall have sufficient precision to ensure measurements made are within stated tolerances.
2. 100% of the boards shall be tested for continuity using the test method described in IPC-6012, Class 2, section 3.9.2.1. 100% electrical test shall consist of probing every end of the net feature.
3. Continuity and Isolation – Test requirements shall be as follows:
1. Test voltage shall be a minimum of 100 Vdc.
2. Resistance between isolated conductors shall be a minimum of 5 M(.
3. Resistance between points measured on the same net shall not exceed 0.5( per inch of circuit length.
4. There shall be no circuits with resistance that exceeds 25 ohms.
4. Fixture Requirements: Boards shall be tested using a fixture or flying probe. For a fixture, the test shall be conducted with all probes simultaneously in contact with the board. This means that dual-sided testing is required if there are surface pads on both sides. As a minimum, the test fixture shall include probes that contact the board at the locations listed below. The fixture may contain additional probes, at the manufacturer's discretion.
1. Every component through hole.
2. Every surface pad that has zero or one trace connected to it.
3. Both through holes for each alignment target on the board, if applicable.
2. Underwriter’s Laboratory Requirements
1. Boards shall be recognized by UL in accordance with UL 796 with a flammability classification of V-0 as defined in UL 94. Boards shall be UL certified for 130 degree C maximum operating temperature.
2. The Vendors UL designation, as defined in section 7, shall be located without interfering with circuitry or nomenclature on the secondary side of the board in copper and shall not be plane areas.
6. qUALITY aSSURANCE rEQUIREMENTS
1. Certificate of Conformance (C of C) data shall be collected on a date code basis and a copy for each date code included with every shipment. A sample Certificate of Conformance showing the minimum requirements is given as Appendix A. Intel will notify supplier of any additional requirements. Any additional information on the material, such as supporting test analyses and traceability information for raw materials, must be maintained at the supplier and available to Intel upon request.
1. The C of C shall be signed by the quality manager, an engineer, or a person of authority with that person's appropriate title stated below their signature.
2. The supplier must keep a copy of the C of C on file for a minimum of 12 months. Electronic copy to be available upon request.
2. The supplier shall provide monthly process capability information as requested by Intel.
3. Supplier shall maintain traceability for raw materials and manufacturing equipment/lines by date code and be available upon request.
4. Supplier Outgoing Quality Metrology:
1. Measurement capability shall be demonstrated for all metrologies used to monitor C of C parameters. Intel must approve measurement capability results. The supplier shall have and supply documented measurement procedures and proven measurement capability for all parameters defined in this specification and appropriate drawings. The supplier shall have documented maintenance and calibration records for all measurement equipment. The supplier shall also have documented records that reflect equipment performance over time (stability) and equipment performance to specifications (capability). These records shall be made available to Intel upon request
2. Metrology Correlation
When requested by the Intel Materials Engineer, successful correlation of C of C parameter metrology with Intel metrology must be completed.
3. Visual Inspection Capability
Upon request, the supplier shall supply documented visual inspection procedures and proven inspection capability for all visual defect criteria defined in this specification. The supplier shall have a documented inspector training and certification program. The supplier shall also have documented records that reflect inspector training and performance over time. The supplier shall have documented maintenance and calibration records for all automated visual inspection equipment. The supplier shall also have documented records that reflect equipment performance over time. These records shall be made available to Intel upon request.
4. Inspection Correlation
Deviation from the inspection methods indicated may be performed by correlated alternative methods, with approval from Intel. The supplier will furnish acceptable visual inspection correlation data to (and approved by) the Intel materials quality engineer.
5. Supplier Change Control Requirements:
1. The supplier shall maintain suitable manufacturing process controls, and quality assurance to assure that these requirements are met. Intel’s PCB Commodity Management shall be notified prior to any changes in materials or manufacturing processes. This applies to all subcontractors used in the process and the metrologies used to monitor the quality of the product. All projected changes must be supplied to Intel in the form of Supplier Change Horizon in advance of implementing changes.
2. The supplier is required to forecast and update all known changes (see checklist in appendix B) on a Change Horizon spanning a rolling quarterly period.
3. Intel must provide written approval of all changes prior to supplier implementation.
4. If requested by Intel, the supplier shall submit a detailed process flow to assist in the judgment of the classification of changes made.
6. Supplier Corrective Action Format
1. Supplier corrective action may be requested from Intel for quality issues that meet Intel excursion criteria or require supplier corrective action. Intel must approve the supplier’s corrective action report (CAR) format.
7. Revision Control:
1. Intel shall provide a complete Gerber package including Intel part number(s), all file layers, fab drawings, and multipack drawings if applicable. The supplier should reference these part numbers to ensure the proper part number and three-digit revision number is included, If the three-digit revision number (example E78435-002) is not included in the CAD for either the single board or multipack, the supplier will be required to add it.
8. Lot Acceptance Criteria
1. Supplier Expectations:
1. Greater than 5000 DPM for any date code will trigger a supplier excursion.
2. Compliance to Intel’s target Cpk ≥ 1.33 for all critical to function parameters requested by Intel. For CpKs less than 1.33, supplier will provide an improvement plan to Intel upon request.
2. The criteria for lot acceptance are defined in the C of C.
3. Intel shall be notified and will provide written approval of any lot that fails C of C criteria prior to shipping.
9. Quality Indicators
1. The following indicators relating to the PCB specifically will be reported to Intel upon request:
1. End of Line Yield (Y) as calculated by the following formula:
Y = total good units into OQA inspection
total units inspected
Calculate for each lot and report as an average for the month.
2. Visual Inspection Yield and Defect Pareto
1. Report previous month yield percentage of total good vs total inspected.
2. Accumulate previous month defect pareto from all defects found in 100 % screening inspection area.
3. Electrical Test Yield and Defect Pareto
1. Report previous month yield percentage of total good vs. total tested.
2. Provide defect pareto of electrical testing failure modes.
4. In Process Parameter Cpk
1. Record Cpk data according to the content and format requested by Intel.
10. Qualification
1. Each supplier shall be qualified by Intel for the level of product technology that they will supply.
1. Qualification requirements may include IPC reliability tests such as thermal shock, solderability, T-260, etc. as well as IST (Interconnect Stress Testing) depending on the technology envelope to be qualified. Typical IST test will require preconditioning at lead-free temperatures (3 passes through reflow oven; peak temperature of 260°C; 60-90 seconds time above liquidous); typical passing criteria is minimum average of 150 cycles for all coupons and no coupon failing before 100 cycles.
6.10.1.2 Intel will provide a comprehensive qualification expectation document whenever a bare board qualification is required
2. First Article Inspection:
1. If requested, a First Article Inspection will be performed and results sent to the Materials Engineer.
2. First Article Inspections must include results from the following measurements / tests, if applicable, at a minimum:
Overall multipack length and width Solderability
Overall PCB length and width SMT/BGA/CSP pad sizes
Hole size/position of datum tooling hole(s) Gold plating adhesion (tape test)
Overall PCB thickness Impedance by layer
Final surface finish plating thickness Dielectric thickness each layer
Gold finger plating thickness Solder mask thickness
PCB and/or Multipack warp PTH Cu wall thickness
Solder mask type Solder mask registration
Inner layer lines/spaces dimensions Outer layer lines/spaces dimensions
Via percent filled Raw material specifications
Stack up construction
3. Micro-section samples taken for the First Article Inspection must be kept for minimum 6 months and made available upon request.
3. Processes qualified as producing acceptable printed circuit boards shall be the same processes used in the manufacture of production lots.
11. Records:
1. Suppliers shall have established procedures to ensure that boards supplied to Intel comply with the requirements of the purchase order, CAD files, fabrication drawing(s), TEIs, and this specification.
2. Supplier quality records shall be retained for a minimum period of one year.
12. Audits:
1. The suppliers’ facility shall be available for audit by members of Intel’s PCB Commodity Team as required.
13. Environmental Compliance:
1. All suppliers and their products shipped to Intel are required to comply with Intel’s specification 405-3109 “Environmental and Lead-Free Solder System Requirements for Purchased Electronic Components (including Restriction on Hazardous Substances, RoHS)”, including submission of attachments.
2. All suppliers are required to comply with Intel’s Environmental Product Content Specification (BS-MTN-0001), including submission of attachments.
3. RoHS compliance is optional for quick turn suppliers who only supply non-revenue product PCB.
4. Halogen free PCB raw materials, which include laminates, prepregs, via-plug material and solder mask, are defined as containing less than 900 PPM bromine and 900 PPM chlorine, and less than 1500 PPM combined bromine + chlorine. No red phosphorous to be used as a flame retardant for halogen free materials.
5. All suppliers are requested to declare environmental compliance by uploading IPC-1752 form through supplier portal, within 3 business days after receiving Intel environmental data requesting notification.
7. SPECIAL rEQUIREMENTS
1. Tools and Documentation:
All engineering changes, deviations and off-specifications must be documented and approved by Intel PCB Commodity Management. A document control system must provide for the tracking, purging and status of changes to specific Purchase Orders or Part Numbers.
1. CAD Data
1. Intel will supply CAD data in Gerber format for generation of film master, drill program and electrical test fixture. Included with the procurement package will be a text file containing the Engineering Parts List (EPL). The EPL is a record of all revision levels for each data file. Any discrepancy between the EPL and data provided must be resolved prior to proceeding with fabrication. When a net list is provided (IPC-D-356, etc), the supplier shall perform a comparison of supplier-generated net list to the original Intel version supplied. All discrepancies shall be reported to Intel. These items are the property of Intel.
2. Fabrication drawings:
Intel will supply fabrication drawings that define the mechanical features of the board. The main elements of the fabrication drawing are:
1. Profile dimensions and tolerances.
2. Hole chart and location map.
3. Stack up construction dimensions and tolerances (if required).
4. Notes and special requirements.
3. Film Discrepancies / Changes:
1. The supplier shall be responsible for ensuring that the final generation film is suitable for the production of printed boards in accordance with the fabrication drawing, this specification and the purchase order. All change requests are to be communicated to Intel using VDCR document number E76649. Fabrication shall not commence until all items are addressed and signed off by both Intel and the supplier
2. Any discrepancies found in the film shall be reported immediately to Intel Printed Circuit Board Commodity for resolution.
3. With the following exceptions, no further changes shall be made to the film without prior authorization from Intel.
1. Non-functional pads may be removed at the supplier’s discretion.
2. Unless otherwise noted on the fabrication drawing or Purchase Order, plating thieves may be added per the requirements outlined in this specification.
3. Teardrops may be added to external and internal layers as long as other requirements within this specification, such as minimum spacing, are met.
4. Drill Discrepancies / Changes
1. If the engineering supplied drill data contains multiple holes at the same X-Y coordinate, the supplier may delete the duplicate holes. If the holes are different sizes, the smaller size shall be deleted.
2. Via in Pad for Passive Components (VIP-P) – Obsoleted and intentionally removed from this document
3. Via Between Pad (VBP) – Obsoleted and intentionally removed from this document
4. Marking Requirements:
1. General
1. No hand-written markings are acceptable on the PCB
2. Legend: see section 5 for specific visual, material, and dimensional requirements.
3. Date Code
1. The secondary side of each board shall contain a permanent date code stating the week and year of manufacture in the format WWYY.
WW: Week
YY: Year
Example: 1202 = week 12, year 2002
2. For multipacks, each individual board shall contain this code.
3. If required, controlled impedance coupons will also contain a matching date code.
4. Part number (base and dash) for individual PCB and multipack, if applicable, must be permanently marked on the secondary side of the individual PCBs per mechanical drawing.
5. Vendor / UL Logo
1. The secondary side of each individual board shall be permanently marked with the vendors’ UL logo and V-0 flammability rating.
2. Marking must not be located in an area that will be routed off or separated from the finished assembly. Marking shall not be etched in plane areas of the board
6. Electrical Test Mark
1. Each individual board must have a permanent mark as evidence of passing Intel’s requirements for bare board electrical test (see section 5.3).
2. This mark can be a stamp on the surface of the boards or along an edge.
7. Customs:
1. Unless otherwise specified on the fabrication drawing, all reference to the country of origin (Made in ______ ) shall be removed from the film leaving no such wording on the finished board.
2. The packaging material must be marked with country of origin on each box.
3. If the supplier is required to mark inside bundles of boards this is permitted provided the bags are marked and not the boards.
5. Multipack X-out
INTEL DOES NOT ALLOW X-OUTS UNLESS OTHERWISE NEGOTIATED.
6. Post Processing Requirements:
1. Rework: There shall be no rework allowed on any PCB unless approved by Intel Corporation.
1. Any rework not authorized in Table IV must be pre-approved in writing by Intel.
1. Non-standard rework authorization is to include marking instructions to identify reworked boards.
2. Supplier is to maintain rework records.
1. The record shall include work order number, date code, rework process, and quantity reworked.
2. Records must be retained for a minimum of one year.
3. Records must be supplied to Intel upon request.
3. Rework must be inspected.
TABLE IV: REWORK
|Rework |Allowed |Method |Inspection |Limitation |
|Type |or | | | |
| |Not allowed | | | |
|Black oxide |Allowed |Reprocess |Visual |1 oz max. 2X reprocess |
| | | | |H oz max. 1X reprocess |
|Drill missing hole |Allowed |Reprocess |X-ray for PTH | |
| | | |Coordinate measuring machine for | |
| | | |NPTH | |
|Panel copper too thin |Allowed |Manual or auto control of |Cross-section/XRF | |
| | |chemical line | | |
|Electroless |Allowed |Reprocess |Visual | |
| | | |Cross-section | |
|Photoresist |Allowed |Strip & reprocess |Visual | |
|Under etching before etch |Allowed |Reprocess |Visual |Record line width and spacing and report to|
|resist removal | | | |Intel upon request. |
|Uncured solder mask |Allowed |Strip & recoat |Visual |Max. 1X reprocess |
|Pre surface finish solder |Allowed |Brush coat or stencil coat |Visual |Max 5% of board area and not to exceed |
|mask touch-up | | | |requirements of section 5.1 and 5.2. |
|Missing via cap |Allowed |Re-screen/fill |Visual |Boards must be marked to indicate extra |
| | | | |bake cycle |
TABLE IV: REWORK (continued)
|Rework |Allowed |Method |Inspection |Limitation |
|Type |or | | | |
| |Not allowed | | | |
|Gold finger rework |Allowed |Strip & re-plate |Ni/Au thickness |Max. 1X reprocess |
| | | |Peel strength | |
| | | |Visual | |
|Immersion Silver reprocessing |Not allowed |NA |NA |No immersion silver rework without written |
| | | | |permission from Intel |
|Outline dimension |Allowed |Reprocess |Visual/dimensional | |
|Open trace |Allowed |IPC-R-700 |Visual/Ohm Meter |Not allowed for RAMBUS traces |
|Short trace |Allowed |IPC-R-700 |Visual | |
|Gold finger touch up (solder |Allowed |Remove solder spot & re-plate |Visual |Must meet requirements of Section 5.1 |
|on gold) | | |Peel strength | |
|Solder pad touch up |Allowed |Soldering Iron |Visual | |
|(insufficient & excess solder)| | | | |
|Warpage |Allowed |Stress relief bake |Visual/dimensional |Must report the bake cycle to Intel |
|(bow and twist) | | | | |
|OSP |Allowed |Strip and Re-coat |Visual |Max. 1 time and need marking for |
| | | | |identification |
| [pic]Panel copper too thick |Not allowed |Mechanical removal |Visual |Not allowed without written permission from|
| | | |Cross-section/XRF |Intel. |
| | | |Electrical test | |
|Pattern copper Plating |Not allowed |Strip resist and/or reprocess |Solder Float |Not allowed without written permission from|
| | | |Cross-section |Intel. |
|Solder mask double coat |Not allowed | | | |
|Cured soldermask |Not allowed |Strip and recoat | | |
|PCBA open trace rework |Not allowed | | | |
|Surface finish cleaning |Not allowed |Jet scrubbing |Visual |Not allowed on immersion or flash gold |
| | | | |surface |
2. Assembly Process Compatibility:
Boards shall be capable of withstanding all Intel assembly process times and temperatures without evidence of delaminating, cracking, blistering, resin recession, or scorching (visible discoloration). Table V is for reference only. Built-in stresses of the materials shall not result in warp as specified in section 5.2 after thermal assembly processes.
Table V
Reference PROCESS CONDITIONS (subject to change)
| |MAXIMUM CONDITIONS |
|PROCESS STEP |oF |oC |TIME |
|Board Baking |230 |110 |4 hours |
|Wave solder preheat |240 |116 |2 minutes |
|Wave Soldering |518* |270* |5 seconds |
|Manual (de)solder |500 |260 |10 seconds |
|SMT reflow |500 |260 |4 minutes |
|Static burn-in |260 |126 |24 hours |
|Rework |500 |260 |1 minute |
|Solvent clean (TMS) |110 |43 |4 minutes |
|Aqueous clean |170 |77 |5 minutes |
* Solder Pot Temp - Top side of board and components do not exceed 190oC (374F)
* Typical lead-free thermal cycles shall include 2 passes reflow, one wave solder, and one rework all at maximum board temperature of 260oC.
3. Rework Simulation:
1. Boards shall be capable of withstanding rework simulation per IPC-TM-650.
2. The test shall be performed after stabilizing the specimens at 23oC, 40 to 60% relative humidity.
4. Solderability
1. Boards shall meet solderability requirements per J-STD-003. When tested, the specimens shall exhibit proper wetting of the wall of the plated-through hole and associated land.
5. Thermal Stress
1. Boards shall be capable of withstanding thermal stress per IPC-TM-650, Method 2.6.8. Test temperature shall be 550° +/-10°F for 10 seconds (288°C).
6. Cleanliness:
1. Per IPC-TM-650, Method 2.3.25 paragraph 4.0. Prior to assembly, bare boards shall have a maximum ionic contamination of 1.56 micrograms per cm2 of NaCl equivalent (10.06 micrograms per in2) of board surface area.
7. Special Performance Requirements:
1. Controlled Impedance
1. For boards requiring controlled impedance, the supplier will be responsible for testing to insure that the impedance is controlled within the specified limits. Upon request, supplier shall provide critical process control data.
2. Coupons are required for the following tolerances:
|Impedance Type |Tolerance |Impedance Coupons Required |
|Single Ended |< 15% |Yes |
|Stripline Differential |< 15% |Yes |
|Microstrip Differential | < 17.5% |Yes |
3. For boards requiring coupons :
1. Supplier will add test coupons, a minimum of one for each manufacturing working panel, unless the engineering drawing specifies an on-board coupon. The preferred location of the panel coupon is the center of the panel.
2. Minimum trace length of each coupon shall be 6.0 inches, and the supplier should measure 50%-70% of the trace.
3. The TDR coupon shall have the Intel part number, date code, and vendor permanently marked.
4. 100% testing of panel coupons required, unless on-board coupons are specified on the engineering drawing and then 100% of the on-board coupons require test. Test data must be made available upon request.
5. Test coupons shall be retained at the supplier site for a minimum period of 90 days after shipment of boards.
2. Fiducials
1. On surface mount boards, fiducials may be located on the boards usually at three corner locations. These features are typically 0.040" round pads surrounded by a 0.120" solder mask clearance. These fiducials are not to be adjusted in size from what is provided in CAD.
2. On multi-pack panels, the board supplier may be required to add fiducials per the dimensions and locations shown on the multi-pack drawing. In order to maintain consistency, these multi-pack fiducials added by the supplier must match the size of the fiducial on the CAD data provided by Intel.
3. Workmanship
1. Workmanship characteristics shall be in accordance with the preferred or acceptable levels of quality as specified by IPC-A-600, current revision.
2. Outgoing visual inspection shall be conducted at 1.75X (approximately 3 diopters).
4. Immersion Silver Handling
1. Board shall be handled with clean gloves after the application of immersion silver. Immersion silver coated boards shall not be exposed to sulfur or acids.
2. No labels, stickers, defect markers, ink stamps, markers, or rubber bands should come in contact with solderable areas of the immersion silver board
5. Compliancy Coupons
1. Certain boards will have registration compliancy coupons located in the corners. A drawing note will identify these locations and specify no custom edits. Only etch compensation is allowed in order to target the exact dimensions provided in the CAD for the finished board.
2. The compliancy coupons must be drilled with the same bit size and drill settings (feeds and speeds) as the vias within the board.
3. The compliancy coupons must be included in the electrical testing of each board.
4. The purpose of the compliancy coupon is to serve as a reference to the registration of the drilled via holes to adjacent copper. Shorted coupons must be reported to Intel and proof of registration compliance must be provided before lot acceptance can be granted.
8. PACKAGING/LABELING/SHIPPING REQUIREMENTS
1. Packaging Requirements
1. Packaging materials shall be selected to prevent any degradation, contamination, or mechanical damage of the material.
2. All boards shall be securely packaged in plastic bags, preferably 10 per bag, not to exceed 15 boards per bag. Package only one date code per bag.
3. The required package is vacuum pack for non-HAL surface finishing PCB. This requirement is not applicable for Quick turn/NPI builds.
4. For overseas shipments, each bag must contain a desiccant to minimize moisture absorption during transportation/storage.
5. The preferred material for packing filler is corrugated cardboard or some other form of paper product and not Styrofoam or CFC materials.
6. Boards shall be packed in a substantial container to ensure acceptance by common carrier at time of shipment.
7. Containers shall conform to the requirements of the consolidated freight classification rules in effect at the time of shipment, 25 lbs. recommended maximum per box. Boxes that exceed 25 lbs must be labeled "CAUTION, HEAVY PACKAGE; LIFT WITH CARE". No box shall exceed 35 lbs. in weight.
8. Each box must be labeled on the outside with the date code(s) of the boards contained therein.
9. Repackaging must comply with requirements within this section.
10. 8.1.10 Individual paper separation is not required for immersion silver PCB however the top and bottom of each pack must be enclosed with sulfur and acid free paper. Vacuum pack is preferred. See esction 7 for immersion silver handling requirements.
11. OSP boards don’t need paper separation but need to put paper on top and bottom for each pack.
12. Use of rubber bands is not allowed.
13. More than 4 date codes in a shipment is not allowed.
2. Labeling Requirements: refer to Intel specification 08-2110 “Incoming Direct Materials Bar-coding Specification” for barcode requirements.
3. Shelf Life – Board Supplier
1. Boards must have date codes showing date of manufacture was less than six months prior to the date of shipment.
2. Board solderability and all other quality within this specification shall be guaranteed for 12 months from date of manufacture (date code) for all surface finishes.
3. Immersion silver and OSP boards shall be stored per surface finish vendors’ recommendation
4. Shelf Life – Assembly
1. Boards with a date code older than 12 months must be evaluated prior to use.
9. APPENDICES:
Appendix A - C of C Requirements for Intel PCBs – reference document only
Appendix B - Supplier Change Control Checklist
Appendix A: C of C Example
[pic]
Appendix B: Supplier Change Control Checklist
|YES |NO |DOES YOUR CHANGE MEET ANY OF THE FOLLOWING CRITERIA? IF SO, NOTIFY INTEL! |
| | | |
| | |KEY/CRITICAL PARAMETERS |
|Y |N |1 - Does change affect (or potentially affect) component form, fit, or function? |
|Y |N |2 - Change is visually or functionally obvious to Intel |
|Y |N |3 - Change could cause Intel concern (manufacturability, reliability or performance) |
|Y |N |4 - Change to part dimensions or design (including CPD changes) |
|Y |N |5 - Changes to CTF parameters |
| | |PRODUCT/SITE TRANSFER |
|Y |N |6 - Move of a production site or the transfer of a piece part material to another production site |
|Y |N |7 - Begin use of, or change subcontractors |
| | |RAW MATERIALS |
|Y |N |8 - Change of raw material content |
|Y |N |9 - Change to a different material |
| | |SHIPPING MATERIALS |
|Y |N |10 - Change to packing or shipping materials |
|Y |N |11 - Change to labels |
| | |GENERIC |
|Y |N |12 - Has there been a problem as a result of such a change before? |
| | |INSPECTION/MONITORS |
|Y |N |13 - Change in sampling plan to loosen criteria for lot acceptance |
|Y |N |14 – Reduction/elimination in sampling frequency or sample size for key process parameters |
| | |MEASUREMENT |
|Y |N |15 - New measurement method or equipment for TDR, XRF, or CMM |
| | |REWORK |
|Y |N |16 - Implementation of a new rework step |
|Y |N |17 - Change to qualified rework procedure |
| | |PROCESS FLOW |
|Y |N |18 - Addition/deletion of a process step in the process flow |
| | |PROCESS METHOD |
|Y |N |19 - Change in production line equipment |
|Y |N |20 - Relocation of a production line |
|Y |N |21 - Change in process chemistry or technology (i.e., plating chemistry, surface preconditioning) |
|Y |N |22 - Change to critical aspect of preventative maintenance procedure |
REVISION HISTORY
REV DATE DESCRIPTION
|0 |7/2002 |New (converted to ATMO format) PCB Procurement Specification |
|1 |5/2003 |Incorporated TEI #1 and TEI#2. |
| | |Revised section 5.2.16.3.1 to add thickness requirements for MacDermid immersion silver |
| | |Revised section 5.2.16.3.2 to add MacDermid immersion silver as an approved process |
| | |Revised section 5.2.18.11.2 to add Goo PSR 550 as an approved photoimageable solder mask |
| | |Revised section 7.2.2 to specify a target VIP-P hole fill of 40% |
| | |Added section 7.3.5.6 to specify that VBP vias shall not be via capped on secondary side |
| | |Revised section 7.8.1.3.1 to clarify requirements if an on-board coupon is provided by the drawing and that the panel refers to |
| | |“manufacturers working panel” |
| | |Revised section 7.8.1.3.4 to clearly specify that 100% impedance testing of panels is required when drawing specifies tolerances of ................
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