University of Bridgeport



Verilog Reference Guide

1. Basic Syntax

I. Comments

Comments can be used to provide annotations about Verilog code to provide additional information about the code. Verilog comments can be either single line comments or block comments.

Example

//Single line comment

/*Block comments

can span multiple

lines */

II. Identifiers

User-defined identifiers are used within Verilog to describe parts of a design. User-defined names must start with a letter or underscore. Verilog is case-sensitive.

Example

A

B14

Wire_A

wire_A //different from Wire_A

_go_12

Invalid names

4wire //does not start with a letter or underscore

input //keyword

III. Keywords

A keyword, or reserved word, is an identifier that has a special significance in Verilog.

|always |and |assign |automatic |begin |

|buf |bufif0 |bufif1 |case |casex |

|casez |cell |cmos |config |deassign |

|default |defparam |design |disable |edge |

|else |end |endcase |endconfig |endfunction |

|endgenerate |endmodule |endprimitive |endspecify |endtable |

|endtask |event |for |force |forever |

|fork |function |generate |genvar |highz0 |

|highz1 |if |ifnone |incdir |include |

|initial |inout |input |instance |integer |

|join |large |liblist |library |localparam |

|macromodule |medium |module |nand |negedge |

|nmos |nor |noshowcancelled |not |notif0 |

|notif1 |or |output |parameter |pmos |

|posedge |primitive |pull0 |pull1 |pulldown |

|pullup |pulsestyle_ |pulsestyle_ |rcmos |real |

| |onevent |ondetect | | |

|realtime |reg |release |repeat |rnmos |

|rpmos |rtran |rtranif0 |rtranif1 |scalared |

|showcancelled |signed |small |specify |specparam |

|strong0 |strong1 |supply0 |supply1 |table |

|task |time |tran |tranif0 |tranif1 |

|tri |tri0 |tri1 |triand |trior |

|trireg |unsigned |use |uwire |vectored |

|wait |wand |weak0 |weak1 |while |

|wire |wor |xnor |xor | |

IV. Numbers

A number is the representation of a numeric value. Numbers are used to assign specific values to variables, parameters, and similar items and within expressions that include a specific value.

Integer constant

An integer constant number is an integer value specified in one of four bases: decimal, hexadecimal, octal or binary. Integer constants can be specified as a simple decimal number or as a based constant. Simple decimal numbers are considered signed integer numbers, but may be preceded by the ‘+’ or ‘-‘ unary sign operators to specify the value’s sign.

Based Constant

Based constant number is an integer specified as three parts: the size of the value, an apostrophe followed by the base indicator, and the sequence of digits representing the desired integer value. The size part is optional and specifies the size of the integer in bits. The base indicator specifies the base of the number as a single case insensitive letter: d for decimal, h for hexadecimal, o for octal, or b for binary. The base indicator may be followed by an optional sign indicator, s, indicating the value to be specified is a signed number.

Example

32

‘b1 // 1

4’b1101 // 1101

8’hA1 // 10100001 = 161

4’hsF // 1111 = -1

2. Declarations

I. Net (wire)

wire name1, name2, name3;

A net is a data type that does not store a value, but rather is used for connections, and derives its value from what it is connected to. A net declaration muse define the net type and name. A net may be declared as wire, supply0, supply1, tri, triand, trior, tri0, tri1, uwire, wand or wor, though wire is the most common and useful. A wire net declaration defines a single bit net that may be connected to a module’s inputs or outputs within a module instantiation, or may be assigned a value within a continuous assignment statement. A multi-bit vector of wire nets may also be declared using a range specification and defines a collection of nets.

Example

wire B, X, F;

wire [3:0] A // A multi-bit vector of wire nets

II. Module

module (ports)

port_declarations

module_statements

endmodule;

A module definition defines a module’s interface to the outside world, including the module’s name, inputs and outputs.

Ports

input Port1, Port2, Port3;

output Port1, Port2, Port3;

output reg Port1, Port2, Port3;

The module’s inputs and outputs, known as ports, appear in a list contained between the parentheses just after the module’s name. Each port must then appear in an input, output or inout declaration to indicate the port’s direction. Multiple ports of the same type may be declared within a single port declaration. By default, all outputs are assumed to be wire nets. An output port may be declared as reg variable data type either within a separate reg variable declaration or within a single output reg declaration.

Example

module And2(X,Y,F);

input X,Y;

output F;

reg F;

//Module’s statements

endmodule

III. Parameter

parameter Name1 = Value1, Name2 = Value2;

A parameter is a constant value defined within a module and represents a fixed value that cannot be changed within the module’s definition. A parameter declaration statement must specify the parameter name and define the value for the parameter. Multiple parameters of the same type can be declared within a single parameter declaration statement.

Example

parameter ClkPeriod = 20;

IV. Variable (Reg)

reg Name1, Name2, Name3;

reg Name = Value;

A variable data type holds its value between assignments. A variable declaration statement must define the variable type and variable name and can optionally define an initial value for the variable. A variable may be declared as reg, integer, real, time, or realtime, though reg is the most common. A reg variable data type is a 1-bit variable that can be assigned a value within a procedure, although a multi-bit vector of type reg may be declared using a range specification. A range specification defines the vector’s most significant bit position, least significant bit position, ordering of the bits within the vector as well as implicitly defining the number of bits within the vector. Variables of type reg may be connected to a module’s inputs within a module instantiation, but may not be connected to a module’ outputs.

Example

reg A;

reg [1:0] regA = 2’b11;

3. Statements

I. Assignment Statement

Blocking Assignment

Variable_Name = Expression;

A blocking assignment is a procedural assignment using the “=” operator to assign a value to a variable. A blocking assignment updates the left-side variable with the value of the right-side expression before proceeding to execute the next statement.

Example

Sum = 0;

X = A + B;

Non-blocking Assignment

Variable_Name = : Greater than or equal

• > : logical right shift

• >> : arithmetic right shift

• 1; //Q = 1100

X. Operator Precedence

• Unary Operator: +, -, !, ~, &, ~&, |, ~|, ^, ~^

• Power : **

• Multiplication/Division: *, /, %

• Addition, Subtraction: +, -

• Shift: ,

• Relational: =

• Equality: ==, !=, ===, !==

• Bitwise AND: &

• Bitwise XOR/XNOR: ^, ~^

• Bitwise OR: |

• Logical AND: &&

• Logical OR: ||

• Conditional : ?

• Concatenation/Replication : {}, { {} }

5. Common Data Types

I. Array

Example

//Array of 4 32-bit elements

reg [31:0] RegFile [0:3];

//Array of 256 8-bit elements

reg [31:0] Memory [0:255];

II. Integer

An integer variable data type is a 32 bit signed value.

Example

integer I;

integer Sum;

III. Signed

In Verilog, input and output ports and reg variables are interpreted as unsigned values unless specified with the keyword signed.

Example

input signed [3:0] B;

reg signed [3:0] B_wire;

IV. Vector

A vector data type defines a collection of bits and is more convenient than declaring each bit separately. The vector declaration must specify the numbering and order of the bits using a range specification. A range specification defines the vector’s most significant bit position, least significant bit position, ordering of the bits within the vector as well as implicitly defining the number of bits within the vector.

To access an individual bit of a vector, we use a bit selection by specifying the bit position in brackets.

Example

output [3:0] S;

reg [7:0] A;

A[0] = A[1] ^ A[2];

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