Verilog Quiz # 1



Verilog Quiz # 1

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Use Verilog to describe the 2:1 multiplexer as shown in the following figure.

[pic]

1. Use gate-level modeling.

module mux2_1 (SEL, A, B, OUT)

input SEL, A, B;

output OUT ;

NOT (                             ) ;

AND (                                      ) ;

AND (                                      ) ;

OR (                                        ) ;

endmodule

　

2. Use continuous assignment statements.

module mux2_1 (SEL, A, B, OUT)

input SEL, A, B;

output OUT ;

assign Out =                                   ;

endmodule

　

3. Use an "always" procedure block.

module mux2_1 (SEL, A, B, OUT)

input SEL, A, B;

output OUT ;

reg OUT ;

always @(                                 ) begin

    if (SEL)

                                                  ;

    else

                                                   ;

end

endmodule

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