Verilog HDL
Lecture 4 - Finite State Machines (FSM) in Verilog
Combinational always Block (review)
• Inputs:
o The Sensitivity List (follows always @ ) should include ALL inputs separated by or.
• Outputs:
o Must be assigned a value under ALL conditions.
▪ if/then/else or case statements cover all possible combintations of condition. (Mux2To1 from Verilog HDL Introduction, page 2).
▪ Default value assigned at top of always block. (Mux2To1 from page 9).
o Type reg.
o Use = for assignments.
• Simulation Model – Code executes from top to bottom sequentially whenever an input in the sensitivity list changes.
Sequential always Block (review)
• Always needs an always block.
• Use ................
................
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