Lab 1: Obtaining the Quartus Prime Lite Design Tools

Should you choose this option, once you copy the code and save the Verilog file to the name Mux_2_to_1.v, you may skip to the next section of this lab manual. The other option is to create a Verilog file from scratch for the 3-bit wide 2-to-1 multiplexer in your project. Take a look at section 3.2 on how to declare the ports on your module. ................
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