EE314 CMOS RF Integrated Circuits - Artificial Intelligence



EE314 CMOS RF Integrated Circuits

( Stanford University: Dr. Hamid Rategh )

Wide-Band High-Performance LNA Project Report

Michael Min Sun aliensun@stanford.edu

Ming Tao Chien mtchienb@stanford.edu

Winter 2006

Single- Ended Source-Degenerated Common-Source

Low-Noise Amplifier

Achieved Specifications

|　 |Specs |Results |　 |　 |

|Pdc(mw) |-5 |11.01 |　 |　 |

|Vdd(v) |10dB when RLoad=Rsg. Considering the wideband requirement will be hard to reach if we use more impedance transform circuits, we decide to set RLoad = Rsg = 50Ω and fT/f0=5. And we also kept in mind to check if Q of the serial RLC < 5=f0/B.

I tried to estimate what gm/id will give me the lowest noise figure. We simply assume the total noise sources of the LNA are device induce gate noise and drain noise. By using noise model in textbook, page 358, and assuming the induce gate noise and drain noise is uncorrelated, we obtain equation (2) and found out that for gm around 40ms-55ms the noise figure is around 1.14dB which is close to the bottom of the bowel. Then I chose Pdc=10mw to preserving 3mw for later adjustment and prepare to consume more power from the discrepancy of Id due to channel length modulation. And I picked Vdd=1.5 for the starting design to have gm = 48ms which is around 40ms-55ms (check Q=2 |4.0000E+08 |→ |Q< |5.0000E+00 |  |

|  |→ |gm> |2.0000E-02 |  |OK |  |

|  |Q= |2.0529E+00 |  |  |  |  |

|Rsg= |50 |  |  |  |  |  |

|Ls= |7.9618E-10 |  |Lg= |7.3761E-09 |  |  |

Table (2): The values in the gray blocks are the design choices

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Assume Rp small due to large number of finger

Assume

L1=0.1mm (Chip to Pad)

L2=0.4mm (Ground plane to Chip)

L3=0.5mm (Pin to Ground plane)

L3

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L1

Die width= 8-(6-0.5-0.1)-(0.4) = 2.2mm

Die length=8-(0.4)-(4-0.5-0.1) =4.2mm

Die size= 2.1mm x 4.2mm = 9.24mm²

(Note)

← 13.8% of package area

← Gross die number, 3150 (8inch wafer)

Table (1)

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