Massachusetts Institute of Technology
Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science
6.111 Introductory Digital Systems Laboratory (Spring 2007)
Final Project Check Off Sheet
Project Title: Wireless Headphones
Student Names: Nivedita Chandrasekaran, Jessica Nesvold, Aditi Shrikumar
TA Name: David Wentzloff
TA Signature/Date:
System Level
|Transmit a 3 minute audio file wirelessly to the receiving headphone set. |[pic] |
|Compresses the digital signal into a packet form compatible with the wireless transmitter and receiver. |[pic] |
|Transmits and receives packets from distances of at least 20 feet. |[pic] |
|Decompresses the received packets. |[pic] |
|Converts the decompressed digital packets back into analog. |[pic] |
|Outputs the analog signal to headphones. |[pic] |
ADC and DAC (Aditi)
|Finite state machine transition diagrams, block diagrams, and Verilog code. |[pic] |
|5x16bit interface between ADC/DAC and compression/decompression modules. |[pic] |
|Implement serial interface to ADC/DAC. |[pic] |
Compression/Decompression (Jessica)
|Finite State Machine transition diagrams, block diagrams, and Verilog code. |[pic] |
|Verilog compression algorithm for use with signed 16-bit integer inputs. |[pic] |
|Verilog decompression algorithm that takes in compressed packets and outputs signed 16-bit integers. |[pic] |
|Working buffer for interfacing to wireless module. |[pic] |
Wireless (Nivedita)
|Finite State Machine transition diagrams, block diagrams, and Verilog code. |[pic] |
|Major FSM properly transitions between transmission, reception, and configuration states. |[pic] |
|Wireless chip reset and configured correctly (panID, device ID). |[pic] |
|Transmits packets from FPGA transmit FIFO buffer, resends if necessary. |[pic] |
|Receives packets into FPGA reception FIFO buffer, sends ACK if CRC is correct. |[pic] |
|Transmit a 10 byte packet of data across the lab. |[pic] |
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