Course Syllabus



Course SyllabusECE526L – Digital Design with Verilog and System Verilog Laboratory Department of Electrical & Computer Engineering1. Course Number and Name:ECE526 L– Digital Design with Verilog and System Verilog Laboratory2. Credit Units/Contact Hours:1/33. Course Coordinator:Ronald W. Mehler4. Text, References & SoftwareRecommended Text:ECE 526L Verilog HDL Laboratory ManualSoftwareCadence NC Verilog simulator5. Specific Course Information a. Course DescriptionA series of exercises and experiments covering bottom-up structural design and top-down behavioral design using Verilog and SystemVerilog (IEEE Std. 1800) for circuit description and design verification. Lab exercises emphasize use of professional compilation and simulation tools for design validation.b. Prerequisite by TopicECE 320/L. Corequisite: ECE 526. Students need a thorough understanding of Boolean algebra, combinational and sequential digital circuits and number systems (binary, hexadecimal).c. Elective Course 6. Specific Goals for the Coursea. Specific Outcomes of Instructions – After completing this course the students should be able to:1. The ability to code and simulate any digital function in Verilog HDL.2. Know the difference between synthesizable and non-synthesizable code.3. Understand library modeling, behavioral code and the differences between then.4. Understand the differences between simulator algorithms.5. Learn good coding techniques per current industrial practices.6. Understand logic verification using Verilog simulation.b. Relationship to Student OutcomesThis supports the achievement of the following student outcomes:a.An ability to apply knowledge of mathematics, science, and engineering to the analysis of electrical and computer engineering problems.b.An ability to design and conduct scientific and engineering experiments, as well as to analyze and interpret data.c. An ability to design systems which include hardware and/or software components within realistic constraints such as cost, manufacturability, safety and environmental concerns.e.An ability to identify, formulate, and solve electrical and computer engineering problems.g.An ability to communicate effectively through written reports and oral presentations.k.An ability to use modern engineering techniques for analysis and design.m.An ability to analyze and design complex devices and/or systems containing hardware and/or software components.7. Topics Covered/Course OutlineThe following are detailed contents of the course:Laboratory #1:Introduction to hardware Modeling and Simulation in VerilogThe student will get familiar with Cadence Verilog XL software and laboratory equipmentLaboratory #2:Structural Modeling in VerilogThe student will model master-slave flip-flop using primitive gatesLaboratory #3:Design Hierarchy in VerilogThe student will model an 8-bit register with design hierarchyLaboratory #4:5-bit counter Behavioral ModelingThe student will model, simulate and test a 5-bit counter using behavioral constructs.Laboratory #5:Modeling with Continuous AssignmentsThe student will model, simulate and test a scalable MultiplexerLaboratory #6:Carry Select Adder ModelingThe student will model, simulate a Carry Select Adder and test its functionality.Laboratory #7:Memory ModelingThe student will model, simulate and test memory a module.Laboratory #8:Arithmetic Logic Unit ModelingThe student will design, model, simulate and test an arithmetic logic unit.Laboratory #9:Modeling a Sequence ControllerThe student will design, model, simulate and test a sequence controller.Laboratory #10: Central Processing Unit ModelingThe student will design, model, simulate and test a CPU.Prepared by:Ronald W. Mehler, Professor of Electrical and Computer Engineering, October 2012Ali Amini, Professor of Electrical and Computer Engineering, March 2013 ................
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