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CHAPTER 1
DISCRETE DEVICES
1. Introduction
We are living in an age of Information Technology. Electronics is at the very foundation of the Information and Computer Age. The giant strides that we have made in the areas of Communications and Computers are possible only because of the great successes that we have achieved in the field of Electronics.
It is sometimes unbelievable, how many electronics gadgets that we carry these days in our person –Digital Wrist-watch, Calculator, Cell-phone, Digital Diary or a PDA, Digital Camera or a Video camera, etc.
The different type of Electronic equipments that has invaded our offices and homes these days is also mind boggling. Many things we use at home and office are “remote controlled”, for example, Television (TV), Air-Conditioners, Audio equipment, Telephone, etc. It is almost close to “magic” how even a child, now-a-days, can switch channels, or increase decrease the volume of sound in a TV at home by just clicking on a few buttons sitting at the comfort of a sofa away from the Television apparently without any physical wiring or connection!
Again, we are astonished, how we are able to talk to our near and dear living several thousands of kilometres away, from wherever we are, at home, office, on the road in a car, or in a classroom –by just clicking a few n numbers on our palm sized cellular phones!
Electronics has made deep impact in several vital areas such as health care, medical diagnosis and treatment, Air and space travels, Automobiles, etc. In short, the technological developments of several countries of the globe are directly related to their strengths in electronics design, manufacture, products and services. It appears as though we have to add inevitably an “E” to the three “R”s, namely, Reading, writing, and arithmetic, to declare a Man or Woman to be “literate”! Needless to add that the “E” here means “Electronics”! Thus Electronics has become surely a “Basic Science”. It is no more an “applied science”. Just as we teach physics, chemistry, biology and mathematics in our schools, it is high time we start teaching our children at school, Electronics as a separate subject by itself.
1.1 Semiconductors:
We know the importance of using the materials like copper, aluminum etc. in electrical applications. This is because copper, aluminum etc are good conductors. Similarly, some materials like glass, wood, paper etc. Also, find wide applications in electrical and electronic applications. These are called insulators. There is another category of materials whose ability to carry current, called conductivity, lies between that of conductor and insulators. Such materials are known as semi conductors. Germanium and silicon are two well-known semiconductors.
A silicon crystal is different from an insulator because at any temperature above absolute zero temperature, there is a finite probability that an electron in the lattice will be knocked loose from its position, leaving behind an electron deficiency called a "hole”. If a voltage is applied, then both the electron and the hole can contribute to a small current flow. The semiconductors in the pure form are known as intrinsic semiconductor.
The addition of a small percentage of foreign atoms in the regular crystal lattice of silicon or germanium produces dramatic changes in their electrical properties, producing n-type and p-type semiconductors.
In an n-type semiconductor, pentavalent impurities such as antimony, arsenic or phosphorous are added to intrinsic semiconductor. These dopants contribute extra electrons, dramatically increasing the conductivity. The addition of trivalent impurities such as boron, aluminium or gallium to an intrinsic semiconductor makes it p-type semiconductor. The dopant produces extra vacancies or holes, which likewise increase the conductivity. It is however the behaviour of the p-n junction which is the key to the enormous variety of solid-state electronic devices.
1.2 PN Junction Diode:
One of the crucial keys to solid-state electronics is the nature of the P-N junction. When p-type and n-type materials are placed in contact with each other, the junction behaves very differently than either type of material alone. Specifically, current will flow in one direction (forward biased) but not in the other (reverse biased), creating the basic diode.
[pic]
Figure 1.2.1: Diode
Figure 1.2.1 shows the circuit symbol of a diode and photograph of typical diode. Since the diode is a two terminal device, the application of a voltage across its terminals leaves three possibilities:
• No bias
• Forward bias
• Reverse bias
No Bias
In the absence of an applied bias voltage, the net flow of charge in any one direction for a semiconductor is zero. The current, which flows under the unbiased condition, is called diffusion. Diffusion is a process in which the charge carriers move from the region of higher concentration to the region of lower concentration. The concentration of holes in the p region is more compared to n region and similarly the concentrations of electrons are more in n region than p region. There will be diffusion of charge carriers and then they undergo recombination with the opposite charge carriers. The recombined carriers are neutral in charge and they oppose further movements of charge carriers. The region near the junction occupied by the recombined charges is called as depletion region. The difference of potential across the depletion region is called barrier potential. For silicon diodes barrier potential is in the range of 0.6 to 0.7 V and for Germanium it ranges from 0.2V-0.3V.
Forward Bias
A forward bias or ON condition is established by applying positive potential to the p-type material and the negative potential to the n-type material as shown in figure 1.2.2
On forward biasing a diode initially, no current flows due to the barrier potential. The applied forward potential repels the charge carriers and hence pushes it towards the junction. This results in construction of the depletion region. As the applied potential increases, it exceeds the barrier potentials at one value (above cut-off value), and the charge carriers gain sufficient energy to cross the potential barrier and enter the other region. The holes, which are majority carriers in the p-region, becomes minority carrier on entering the n-region, and the electrons, which are majority carriers in n-region, become minority carriers on entering the p-region. This injection of the majority carriers into the opposite region results in current called diode forward current IF.
The application of a forward-bias potential will pressure electrons in the n-type material and holes in the p-type material to recombine with the ions near the boundary and reduce the width of the depletion region as shown in the figure 1.2.2. There is no change the flow of minority charge carriers, but there is heavy flow of majority charge carriers across the junction. An electron of the n-type material will cross the reduced depletion region at the junction and attracted by the positive potential applied to the p-type material. As the applied bias increases in magnitude, the depletion region width continues to decrease and finally flood of electronics will pass through the junction, resulting in an exponential rise in the current as shown the VI characteristic curve in figure 1.2.4.
Reverse Bias
Under reverse bias condition, the positive terminal of the DC supply is connected to the n-type and negative terminal to the p-type semiconductor as shown in the figure 1.2.3.
On reverse biasing the majority charge carriers are attracted towards the terminals of the applied potential. This results in the widening of the depletion region. That is number of uncovered positive ions in the depletion region of the n-type material will increase due to the large number of electrons are flown towards the applied positive potential and similarly the number of negative ions in the p-type also will increase due to applied negative potential. The net effect is widening of the depletion region, which will introduce a great barrier for the majority carriers to overcome resulting in zero current flow due to majority charge carriers. The current due to minority charge carriers still do not change, and takes part in the diode current. So the current that exist under the reverse bias conditions is called the reverse saturation current and is represented by I0 or IS it is in the range of few micro amperes.
The Diode Current
The Forward diode current flowing during the forward bias is given by the following equation.
(1)
ID= Diode Forward Current
I0 = Reverse saturation current.
VD= Applied bias voltage
[pic] (T in Kelvin), Volt equivalent of temperature.
η= Constant for Germanium η =1 and for Silicon η =2
When the diode is forward biased, the applied voltage is positive and is large compared to VT and exp(VD/ηVT) >>1, there for 1 can be neglected from the equation and final equation will be
(2)
The ID current will increase exponentially with an increase in the forward voltage VD after the cut in voltage is reached. When the diode is reverse biased, the applied voltage is negative and is small compared to VT and exponential term can be neglected. Then the diode equation becomes ID≈I0.
V–I characteristics of PN Junction diode
As we can see from the V-I characteristics when the diode is forward biased initially, the forward current is zero and when we increase the forward voltage, the forward current will vary in small magnitude, as the barrier potential is not reached. Once the applied voltage is exceeds the barrier potential or cut-in voltage or Vknee, then there will be exponential rise in the forward current. The forward current is in the range of milli amperes.
When the diode is reverse biased and when we increase the reverse applied voltage, as we know only reverse saturation current flows, which is due to the minority charge carriers. The reverse current is in the range of few micro amperes. Finally, when the reverse voltage is increased beyond certain limit, the diode breaks down and reverse current shoots up to a very large value. The breakdown of diode can be either zener breakdown or avalanche multiplication, which will be discussed next.
The Diode Breakdown
The reverse break down in diodes can occur due to two mechanisms, each of them require critical electric field at the depletion region of the diode. They are
• Zener breakdown
• Avalanche Multiplication
Zener breakdown
When the doping is very high (≥ 1025 atoms/m3), the depletion region is very narrow, which results in tunnelling of electrons from p-type valance band to the n-side conduction band constitutes a reverse current from n to p, this is called zener effect. The basic requirement for the tunnelling current is a large number of electrons separated from a large number of empty states by a narrow potential barrier.
The electric field resulting due to the depletion region causes field emission where by the force on outer orbit electrons due to field is very high that they are pulled out from the parent nucleus to become free carriers. This ionization by electro-static attraction is known as “Zener breakdown” and causes an increase in the free carriers density and hence an increase in the reverse current of the junction. Only for the lower level of reverse voltage the zener effect is exhibited
Avalanche Multiplication
When the diode is reverse biased, carriers acquire sufficient energy from the thermal energy and along with the applied reverse bias results in the high electric field in the depletion region. An electron entering from the p-side may be accelerated to high kinetic energy to cause ionizing collision. This ionizing collision results in the breakage of covalent bonds of the bound charges, this result in the generation of new electron-hole pair. The original electron and generated electron are both swept to the n-side of the junction and generated hole is swept to the p-side. The generation of electron-hole pair results in the generation of enormous energy by the process called fission. The liberated fission energy along with the applied potential and thermal energy colloid with other non-ionized bonds. This collision and generation of new electron-hole pairs are continuous and multiplicative, which results in a large amount of charge carriers and thus an increase in the reverse current.
Effect of Temperature on the Reverse current
Since the reverse saturation current is temperature dependent parameter, the reverse saturation current approximately doubles for every 10o C rise in temperature. Let I01 is the reverse saturation current at temperature T1 and I02 is the reverse saturation current at temperature T2, where T2 > T1. The rise in reverse saturation current is given by the relation.
[pic]
The Diode resistance
The static resistance(R) of the diode is defined as the ratio of voltage to current at any point on the characteristics. It is reciprocal of the slope of the line joining the operating point to the origin. The study of the static resistance is very important when the diode characteristic is linearised from the exponential from the modelling point of view. The value of the static resistance remains constant for the region of operation.
The dynamic resistance (r) of a diode is defined as the ratio of change in voltage to the change in current. The dynamic resistance is not as constant as static resistance; it depends upon the operating voltage.
ID= Diode Forward Current
I0 = Reverse saturation current.
VD= Applied bias voltage
[pic] (T in 0Kelvin) Volt equivalent of temperature.
η= Constant for Germanium η =1 and for Silicon η =2
Peak Inverse Voltage (PIV)
This is defined as the voltage that the diode has to withstand under reverse biased condition.
Solved Problems
1. A Silicon diode has a saturation current of 1pA at 20oC. Find Diode bias voltage when diode current is 3mA. Diode bias current when the temperature is 100OC assuming the diode voltage to be constant.
Solution:
Given
The diode current ID=3mA,
Reverse saturation current IO=1x10-12 A,
Temperature T=20OC = 273+20 = 293OK
The diode is silicon η=2
The equation for the diode current ID is given by
[pic] and [pic]
i. The diode bias voltage
[pic]
ii. The diode current when the temperature is 100OC
[pic]
The temperature is raised to 100OC (So the reverse saturation current I0 changes) use the relation.
[pic]
[pic]
2. Find the static and dynamic resistance of a p-n junction germanium diode if the temperature is 27OC and IO=1μA for an applied forward bias of 0.2V.
Solution
Given
Applied forward voltage= 0.2 V
Reverse saturation current IO=1x10-6 A,
Temperature T=20OC = 273+27 = 300OK
The diode is Ge η=1
[pic]
[pic]
[pic]
[pic]
Exercise Problems:
1. A Silicon diode has a saturation current of 0.1pA at 20OC. Find its forward voltage when the current is 0.3mA.
2. A Germanium diode has IO=10μA. Determine its forward voltage when it is carrying 50mA of current. Compute the dynamic resistance at this operating point.
3. A Silicon diode at room temperature conducts 5mA at 0.7V. If the voltage increases to 0.8V. Find reverse saturation current.
4. Calculate the factor by which reverse saturation current IO of Germanium diode is multiplied when the temperature increases from 25 to 100OC.
5. Determine the voltage for which the reverse current in a germanium diode reaches 70% of its reverse saturation value at room temperature.
1.4 BIPOLAR JUNCTION TRANSISTOR
Introduction
Demonstrated by a team of scientists at Bell laboratories in 1947.
Brought an end to the era of vacuum tube devices.
Advantages:
• Smaller size, light weight
• No heating elements required
• Low power consumption
• Low operating voltages
Used in applications such as signal amplifiers, electronic switches, oscillators, etc.
Transistor structure
Three terminal, Three-layered, two-junction device
Two types:
• Thin layer of n-type material sandwiched between two p-type materials (called PNP transistor)
• Thin layer of p-type material sandwiched between two n-type materials (called NPN transistor)
Fig 1.4.1: Transistor structure
Emitter is heavily doped – supplies charge carriers
Base is lightly doped – allows most of the charge carriers to pass through it
Collector is moderately doped – collects the charge carriers
Two junctions are:
• Emitter-base junction (or E-B diode)
• Collector-base junction (or C-B diode)
For normal operation, E-B diode should be forward biased and C-B diode should be reverse biased.
Transistor operation
Working of NPN transistor is discussed here. Working of PNP transistor is similar (roles of free electrons and holes are interchanged and current directions are reversed)
• EB diode is forward biased. So, depletion region at EB junction is narrow
• CB diode is reverse biased. So, depletion region at CB junction is wide
• Free electrons from emitter region cross the junction and reach base region. (Repelled by the negative potential at the emitter terminal)
• Some of these free electrons combine with the holes in the base region. They move towards the base terminal and form the base current.
• There are very less number of holes available in base. Therefore, most electrons (about 99%) coming from emitter do not combine with holes. They fall down the potential gradient and enter collector region. (Attracted by the positive potential at the collector terminal)
• So, emitter emits electrons, collector collects these electrons.
Directions of three currents are shown in figure 1.4.2.
Fig. 1.4.2: Transistor operation
Current directions are opposite to electron-flow directions. IE is emitter current, IB is base current, IC is collector current
Current relationship:
[pic] - (1.1)
When emitter circuit is opened, there is no supply of free electrons from emitter to collector. Even then, there will be small collector current called reverse saturation collector current[pic]. This is due to thermally generated electron-hole pairs.
Even during normal operation, [pic]is present. So, total collector current is:
[pic] - (1.2)
where, [pic] is fraction of emitter current, which flows to collector. From (1.2),
[pic] - (1.3)
Since ICBO is very small,
[pic] - (1.4a)
Also,
[pic] - (1.4b)
Transistor symbols
Fig. 1.4.3: Transistor symbols
Arrow head represents the direction of current through emitter.
Transistor configurations
Transistor is 3-terminal device. For amplifier circuit, four terminals are required – two for input and two for output. So, one of three terminals of transistor is made common for both input and output. Accordingly, there are 3 configurations:
• Common base (CB) configuration
• Common emitter (CE) configuration
• Common collector (CC) configuration
Common base configuration
Fig: 1.4.4 Common Base configuration
Base is common, emitter is input terminal, and collector is output terminal. We get two characteristics: input characteristics and output characteristics
Input characteristics
It is the plot of input current IE, versus input voltage VEB, for various values of output voltage VCB. As VEB is increased, IE increases similar to diode characteristics. If VCB is increased, then IE increases slightly. This is due to the increase in electric field aiding the flow of electrons from emitter.
Fig 1.4.5: CB Input and Output characteristics
Output characteristics
Plot of output current IC versus output voltage VCB for various values of input current IE.
Three regions can be identified: Active, cutoff and saturation
Active region: Region to the right of y-axis, above IE=0 curve, where the curves are linear. IE is positive nonzero (i.e., E-B diode is forward biased) and VCB is positive (i.e., C-B diode is reverse biased),When VCB is increased, IC increases slightly. This is because, when VCB is increased, depletion region width at C-B junction increases, so effective base width decreases, so IB decreases. Hence IC increases (IC = IE – IB) This effect is known as Early effect (also called base width modulation).If IE is increased, IC also increases. When IE=0, IC=ICBO (reverse saturation Collector current in common Base with emitter Open). ICBO doubles for every 10 degree rise in temperature
Cutoff region: Region below IE=0 curve
Here IE is less than zero (E-B diode is reverse biased) and VCB is positive (C-B diode is reverse biased).Transistor is said to be in OFF state since IC is zero.
Saturation region: Region to the left of y-axis, above IE=0 curve.
Here IE is positive nonzero (E-B diode forward biased) and VCB is negative (C-B diode is forward biased) IC decreases exponentially in this region.
Common emitter configuration
Emitter is common, base is input terminal, collector is output terminal
Again we get two characteristics: input characteristics and output characteristics
[pic]
Fig. 1.4.6: Common-Emitter configuration
Input characteristics
It is the plot of input current IB versus input voltage VBE for various values of output voltage VCE. As VBE is increased, IB increases similar to diode characteristics. If increased, then IB decreases slightly. This is due to Early effect.
Output characteristics
Plot of output current IC versus output voltage VCE for various values of input current IB.
Three regions can be identified: Active, cutoff and saturation
[pic]
Fig1.4.7: Input and output characteristics of CE mode transistor.
Active region: Region to the right of VCE Sat, above IB=0 curve, where the curves are linear. Note that VCE = VCB + VBE - (1.5)
If VCE > VCE Sat, then VCB becomes positive (i.e., C-B diode is reverse biased)
VCE Sat is around 0.3V for silicon transistor. If IB > 0, then it means E-B diode is forward biased. When VCE is increased, IC increases slightly due to Early effect. Note that slope of curve is more than that of CB o/p characteristics. If IB is increased, IC also increases
When IB=0, IC=ICEO (Collector current in common Emitter with base Open) ICEO is much more than ICBO of CB configuration.
Cutoff region: Region below IB=0 curve Here E-B diode and C-B diode are both reverse biased Transistor is said to be in OFF state since IC is almost zero.
Saturation region: Region to the left of VCE Sat and right of y-axis Here E-B diode and C-B diode are both forward biased
Note: Common collector characteristic is similar to that of common emitter, hence not discussed here.
Relation between αdc and βdc
From equation (1.1) we have [pic]
Dividing throughout by IC we get: [pic]
From equations (1.4a) and (1.4b) we get: [pic]
Rearranging, we get: [pic] - (1.6)
Rearranging again, we get: [pic] - (1.7)
In the above two equations, we can replace αdc and βdc by αac and βac respectively without causing any harm.
Relation between ICBO and ICEO
From equation (1.2) we have [pic]
Using eq. (1.1) we get: [pic]
Rearranging, we get: [pic]
Hence, we get: [pic]
We know that, at IB = 0, IC = ICEO.
Substituting IB = 0, we get: [pic] - (1.8)
Practical transistor circuits
In the circuit diagrams shown earlier, there were no resistors. Without resistors, currents may be high enough to burn the transistor!
Figure shows practical transistor circuit used to determine input and output characteristics in CE configuration
[pic]
Fig. 1.4.8: Practical Common Emitter Transistor circuit
Rearranging, we get: [pic] - (1.9)
Applying KVL to the output loop: VCC – ICRC – VCE = 0
Rearranging, we get: [pic] - (1.10)
Equations (1.9) and (1.10) are two important design equations
VBE is often taken as +0.7 V for Silicon and +0.2 V for Germanium, for simplicity.
Note: for PNP transistor, VBE is negative.
Transistor maximum ratings
There are limits on voltage, current and power dissipation in transistor. If these limits are exceeded, then transistor will not function properly, or may even burn.
For CE configuration, limits are set on VCE, IC and PC = VCEIC.
i.e., VCE should not cross VCEMAX, IC should not cross ICMAX, and PC should not cross PCMAX. All three conditions should be satisfied at the same time.
For the transistor to operate in active region, within the maximum ratings, we require:
[pic]
7
Problems
1. In pnp transistor circuit, the ammeter reads the base current as 16 µA. If the emitter current is 1.618 mA, determine the collector current.
2. A BJT has α = 0.99, IB = 25 µA and ICBO = 200 nA. Find the collector current.
3. For problem 2, find the emitter current. Also find the emitter current by neglecting ICBO and then find the percentage of error.
4. For a certain BJT, β = 50, ICEO = 3 µA and IC = 1.2 mA. Find IB and IE.
5. A Ge transistor with β = 100 has base-to-collector leakage current of 5 µA. If the transistor is connected in common-emitter operation, find the collector current for base current (a) 0 and (b) 40 µA.
6. A Ge Transistor has collector current of 51 mA when the base current is 0.4 mA. If β = 125, then what is its collector cutoff current ICEO?
7. In a transistor circuit, when the base current is increased from 0.32 mA to 0.48 mA, the emitter current increases from 15 mA to 20 mA. Find αac and βac values.
8. A transistor with α = 0.98 and ICBO = 5 µA has IB = 100 µA. Find IC and IE.
1.5 Light Emitting Diode:
The increasing use of digital displays in calculators, watches and all forms of instrumentation has contributed to an extensive inherent in structures that emit light when properly biased. The two types of displays commonly used are light emitting diode (LED) and liquid crystal display(LCD).
Light emitting diode is a diode that gives of visible or invisible (infrared) light when energized. In any p-n junction there is a recombination of holes and electrons. During this process energy possessed by the free electron is transferred to another state, some of this energy is transferred into heat and some in the form of photons. In silicon and germanium greater percentage is converted into heat and the emitted light is insignificant.
Diodes constructed of GaAs emit light in the infrared zone during the process of recombination. Even though the light is not visible, they have numerous applications like, security systems, industrial processing, optical coupling etc. where visible light is not a desirable effect visible light can be generated.
By using elements like gallium, arsenic and phosphorous LEDs producing red, green, yellow, blue, orange or infrared (visible). LED’s have replaced incandescent lamps in many applications because of their low voltage, long life, and fast on-off switching.\
[pic]
Fig1.5.1 LED symbol and circuit
Brightness of LED depends on current brightness is usually controlled by current source.
Seven Segment Display:
[pic]
Fig 1.5.2: Seven segment display
Figure shows seven segment display. It contains seven LEDs. It can be used to display any alphanumeric character. Fig is schematic diagram of seven segment display, where all the anodes connected together.
External series resistance is used to limit the current. By grounding one or more resistors we can display a character.
Application of LED:
• In burglar alarm system
• Picture phones
• Multi meters and digital meters
• Electronic panels
• Optical communication system
1.6 Photo Diode:
When a p-n junction diode is reverse biased the current flow is only due to the minority charge carriers. These carriers exists because of thermal energy, which dislocates valance electrons from their orbits, producing electron hole-pairs.
When light energy bombards a p-n junction, it can dislodge valance electrons. The more light striking the junction, reverse current increases. In photo diode light is made to fall on p-n junction by providing a window to allow the light fall.
[pic]
Fig1.6.1: Photo diode
Application of Photo diodes:
• As light detectors
• As demodulators
• Encoders
• Optical Communications
• High speed counting
• Switching circuits
1.7 Photo Transistor:
The photo transistor is like a normal transistor, but the base is kept open. The incident light is made to fall on the base terminal so that base current is generated and the output current is multiplied by the β of the transistor. The symbol and typical application circuit is as shown in fig.1.7.1.
[pic][pic]
(a) (b)
Fig 1.7.1 : Photo Transistor a) Symbol and b) Typical application
Applications:
• In high speed reading of computer punched cards and tapes
• Light detector systems
• Light operated switches
Production line counting objects
1.8 Opto Coupler: Opto coupler or opto isolator combines an LED and a photo diode in a single package as shown below in Fig. no.1.8.1.
When input voltage is applied to LED emits light and this light is detected by photo diode. The reverse current flowing in the photo diode circuit produces a voltage drop across series resistor, which is proportional to reverse current, which in turn proportional to input voltage. This device can couple an input signal to the output circuit.
Advantage of opto coupler is the isolation between input and output circuits.
[pic] [pic]
(a) (b)
Fig 1.8.1:Opto coupler a) Symbol b) Typical aplication
1.9 Varactor Diode:
The depletion layer formed in a p-n junction is like a parallel plate capacitor. The capacitance of this depends on the width of the depletion layer. Width of the depletion layer is directly -proportional applied reverse voltage. Thus capacitance can be controlled by reverse voltage. Diodes used for this purpose are called varactor or voltage variable capacitor or varicaps.
Symbol and variation in capacitance are as shown:
[pic]
Fig1.9.1: Varactor Diode
Because the capacitance is voltage controlled, varactors have replaced mechanically tuned capacitors in many applications such as television receivers automobile radios and other communication equipments.
When it is connected in parallel with inductor it forms a resonant circuit, having resonant frequency which is function of applied voltage. This is the principle behind electronic tuning of a radio station, or a TV channel.
Applications
• FM radio and TV receivers
• AFC circuits
• Self adjusting bridge circuits
• Adjustable band pass filters
• Tuning LC resonant circuits
CHAPTER 2
DIODE CIRCUITS
2.1 Clipper: Clipping circuits are used to select that part of the input wave which lies above or below some reference level. A clipper is a device designed to prevent the output of a circuit from exceeding a predetermined voltage level without distorting the remaining part of the applied waveform.
A clipping circuit consists of linear elements like resistors and non-linear elements like diodes or transistors. Clipping circuits are used to select for purposes of transmission, that part of a signal wave form which lies above or below a certain reference voltage level.
Clipping circuits can be classified as positive clipper and negative clippers.
Positive clipper: Fig. shows positive clipper.
[pic]
The action of the circuit is explained below. When the input signal voltage is negative, the diode D is reverse-biased and behaves as an open-switch, the entire negative half cycle appears across the load( output). When the input signal voltage is positive but does not exceed battery voltage VR, the diode D remains reverse-biased and most of the input voltage appears across the output. When during the positive half cycle of input signal, the signal voltage exceeds the battery voltage VR, the diode D is forward biased i.e conducts heavily. The output voltage is equal to VR and stays at VR as long as the input signal voltage is greater than battery voltage VR in magnitude. Thus a biased positive clipper removes input voltage when the input signal voltage exceeds the battery voltage. Clipping can be changed by reversing the battery and diode connections.
That is Vo = Vi if ViVR
[pic]
Negative biased clipper: the clipping circuit which removes part of the negative input is as shown in Fig. below
[pic]
When the input signal voltage is positive, the diode D is reverse-biased and behaves as an open-switch, the entire positive half cycle appears across the load. When the input signal voltage is negative but does not exceed battery voltage V, the diode D remains reverse-biased and most of the input voltage appears across the output. When during the negative half cycle of input signal, the signal voltage exceeds the battery voltage V, the diode D is forward biased i.e conducts heavily. The output voltage is equal to – V and stays at – V as long as the input signal voltage is greater than battery voltage V in magnitude. Thus a biased negative clipper removes input voltage when the input signal voltage exceeds the battery voltage
Consider another circuit shown below
In this circuit,
Vo = Vi if Vi>VR
Vo = VR if Vi> 1, we have (β+1) ≈ β. If βRE >> RTH, then equation (12) reduces to:
[pic] - (3.29)
Now, [pic] - (3.30)
Since equation for IC does not contain β, we say that IC is independent of temperature variation and transistor replacement.
Advantages of voltage divider bias
• Collector current, and hence Q-point is independent of β. Hence Q-point is stable against variation in temperature and replacement of transistor
Disadvantages of voltage divider bias
• Analysis and design are complex
• More circuit components required
Problems
1. For a fixed bias circuit using Si transistor, RB = 500 kΩ, RC = 2 kΩ, VCC = 15 V, ICBO = 20 µA and β = 70. Find the Q-point collector current ICQ.
2. A Si transistor is biased for a constant base current. If β = 80, VCEQ = 8 V, RC = 3 kΩ and VCC = 15 V, find ICQ and the value of RB required.
3. Repeat problem 2 if the transistor is a germanium device.
4. For a fixed bias circuit, VCC = 12 V and RC = 4 kΩ. The Ge transistor used is characterized by β = 50, ICEO = 0 and VCE sat = 0.2 V. Find the value of RB that just results in saturation.
5. For a self bias circuit using silicon transistor, RE = 300 Ω, RC = 500 Ω, VCC = 15 V, β = 100 and [pic]. Find the values of R1 and R2 to get VCEQ = VCC / 2.
6. For a self bias circuit, the transistor is a Si device, RE = 200 Ω, R1 = 10R2 = 10 kΩ, RC = 2 kΩ, β = 100 and VCC = 15 V. Determine the values of ICQ and VCEQ.
7. For a self bias circuit using Si transistor with β = 100, RC = 330 Ω, RE = 100 Ω and VCC = 12 V. Determine the values of R1 and R2 required to provide a base bias current of 0.3 mA, so as to locate the operating point at ICQ = 18 mA and VCEQ = 4.25 V.
8. A fixed bias circuit has VCC = 20 V, RC = 5 kΩ, RE = 4 kΩ and RB = 300 kΩ. The Si transistor has ICBO = 0 and β = 50. Find ICQ and VCEQ.
9. Suppose if the transistor used in problem 8 failed, and was replaced with a new transistor with ICBO = 0 and β = 75. Is the new transistor still biased for active region operation?
Connecting ac signal to a Transistor:
After a transistor has been biased with the Q point near the middle of the load line, we can couple a small AC voltage in to the base. This produces AC collector voltage which is proportional to AC input voltage. For applying this voltage a coupling capacitors are used.
Coupling Capacitor:
Consider the RC circuit shown below. Here R represents the input resistance or the load resistance of the amplifier.
Here a capacitor is used to connect the AC signal source to load R. Since capacitive reactance is inversely proportional to frequency for DC voltages. This capacitor acts as a open and at very high frequency it acts as a short circuit. When capacitor is used in this way it is called Coupling capacitor. For this to work properly its reactance must be very small even at the lowest frequency of the source.
As a rule Xc < 0.1 R
Where R is the input resistance of amplifier. For example if the frequency variation is 20 Hz to 20 KHz, thus at 20 Hz, also [pic] < 0.1 R
Ex: If R = 2 KΩ, and frequency range is 20 Hz to 20 KHz, the value of the capacitor needed is
Xc < 0.1 R
[pic] < R C= 39.8 µF
Emitter Bypass Capacitor:
Emitter resistance RE is used to stabilize the operating point. Similar to coupling capacitor bypass capacitor must be open for DC signals and short for AC signals.
Fig shows an AC voltage connected to RC circuit. For high frequency capacitive reactance is too small and acts like a short circuit. In other words point E is effectively connected to ground. Similarly by connecting a capacitor in parallel it passes all AC components and effectively grounding emitter, without disturbing DC conditions.
For bypass capacitor to work effectively, even at the lowest frequency capacitive reactance must be too small. As a rule Xc < 0.1 RE.
Ex: In the circuit shown of f = 1 KHz, then
Xc < 0.1 RTh , RTh = R1|| R2 = 375Ω
C = [pic] , C = 4.2 µF
Small Signal Operation:
When a sinusoidal voltage (ac) is applied it appears across the emitter diode and produces the sinusoidal variations in VBE . When input voltage increases to positive peak Q point moves to QA, and when the input voltage reaches negative peak point moves to QB. Thus Q point is moving along the curve. The size of the AC voltage determines how far the instantaneous point moves away from the Q point. Large AC voltage produces large variations and small ac voltage produces smaller variations.
If the movement of the instantaneous Q point is large it will produce distortions because of the curvature of the graph. To reduce the distortion smaller swing in input voltage is desired.
AC Beta : When AC signal is applied ib and ic also changes and we define AC current gain β = [pic] this is different from β dc = = [pic]
h-parameter model:
Another model used for transistor earlier is h-parameter model. Manufacturer specification sheets provide this parameters. The H-parameter model of transistor in general and for common emitter are as shown below
[pic]
[pic]
hie = input impedance =[pic]
hfe = forward current gain = [pic]
hoe = output conductance = [pic]
hre = reverse transfer ratio = [pic]
These parameters can be determined from the transistor static characteristics.
Transistor Amplifier
Amplifier is a circuit which increases the magnitude of input quantity applied
Bipolar junction transistor basically amplifies current
If base current is considered as input current, then collector current which is output current is beta times the input current. This is known as transistor action
By suitably designing transistor circuit, we can get voltage amplification and power amplification to work as amplifier, transistor should be in active region throughout the input waveform cycle. i.e., base-emitter junction forward biased, collector-base junction reverse biased. This is achieved by proper use of biasing circuit Consider the working of the circuit shown below:
Batteries VBB and VCC ensure that transistor is operating in the active region. It causes direct currents IB, IC and IE to flow Vin is a weak signal to be amplified. This causes an alternating current ib to flow through input circuit Total base current iB is sum of IB and ib, which is alternating current During positive quarter cycle of input waveform, as input voltage increases, ib and hence iB increases. Due to transistor action, iC also increases.
We have [pic], where β = βac is current amplification factor Since β is very large, even for small increase in iB, there is a large increase in iC. Hence large alternating voltage Vout =iCRL develops across load resistor RL. During second quarter cycle of input waveform, as input voltage decreases, iB decreases, and also iC decreases.
During negative half cycle of input waveform, E-B junction still remains forward biased because, VBB is so chosen that it is greater than peak value of Vin. So, during negative half cycle when iB decreases, iC also decreases, and hence Vout decreases Thus output voltage Vout will be exact replica of input voltage Vin, but magnified many times However, since current direction through RL is from bottom to top, the output voltage is 180o out of phase with input.
3.3 Single stage CE transistor amplifier
A practical common-emitter transistor amplifier using voltage divider bias is shown fig. The use of bias eliminates the need for two separate batteries VBB and VCC.
Resistors R1, R2, RC and RE, and voltage source VCC fix operating point in active region. This is voltage divider bias, which is already discussed. CC is called coupling capacitor. At input side, it blocks dc component of input voltage (or output of previous stage) from reaching the base of transistor. If dc is not blocked, then it will shift the operating point. At output side, CC blocks dc component from entering into the load (or next stage).
Figure3.3.1: RC coupled amplifier
CE is called emitter by-pass capacitor. It offers low reactance path for ac component, thus preventing ac component from passing through RE. If ac is allowed to pass through RE, then it will decrease VBE, bringing down output voltage. RL is the equivalent resistance of the load connected at output of amplifier.
As explained earlier, when input voltage varies, iB varies and hence iC varies. Thus output voltage is proportional to input voltage, but amplified.
Note that output can also be taken across RC.
3.4 Classification of amplifiers
Classified based on different criteria.
Based on signal frequency
• Audio amplifier (frequencies between 20Hz and 20KHz)
• Video amplifier (frequencies above 20KHz up to a few MHz)
• Radio amplifier (frequencies up to several MHz)
Based on quantity amplified
• Voltage amplifier (input voltage level is amplified)
• Current amplifier (input current level is amplified)
• Power amplifier (input power level is amplified)
Based on mode of operation
• Class A amplifier (collector current flows throughout the input signal cycle)
• Class B amplifier (collector current flows only during positive or negative half cycle of input signal cycle)
• Class C amplifier (collector current flows for less than half cycle of input signal)
• Class AB amplifier (collector current flows for more than half, but less than full cycle of input signal)
3.5 Gain of amplifier
Voltage gain of amplifier is given by
[pic] - (3.32)
It has no units as it is ratio of voltages. However, gain is measured in terms of decibels defined by:
[pic] - (3.33)
Note that unit less gain AV is negative since Vout is 180o out of phase with Vin. However, while expressing in terms of dB, negative sign is obviously not taken.
Usually gain of around 100 (approximately) (i.e., 40 dB) can be easily obtained using one stage amplifier. Sometimes, this may not be sufficient. Especially when input is in micro volts, we may require gain more than 1000 or 10000.
In such cases, we have to cascade amplifier stages. i.e., connect amplifiers in series, with output of one stage given to input of next stage.
3.6 Multistage amplifiers
If high gain is required, then amplifier stages are cascaded as shown in figure 3.18.
Overall gain AV is product of individual gains: [pic] - (3.34)
In decibels, overall gain is sum of individual gains:
[pic] - (3.35)
However, practically the gain will be less than calculated AV due to loading effects
Fig 3.6.1: Multistage amplifier
3.7 Frequency response of amplifier
Plot of amplifier gain versus frequency of input signal is called frequency response. Frequency of input signal is increased in steps. At each frequency, voltage gain is determined and then plotted. It is found that gain is very small at lower frequencies and at higher frequencies. Gain remains constant at mid frequencies. For audio amplifier, it is required that gain should be constant over the audio frequency range from 20 Hz to 20 kHz.Bandwidth of amplifier is defined as range of frequencies over which gain is either equal or greater than 0.707 (or 1/√2)times the maximum gain Since 20 log (0.707) = – 3, bandwidth is also defined as range of frequencies over which gain is within 3 dB of maximum gain (in dB) Fig shows frequency responses of RC coupled amplifier
Figure 3.7.1 : Frequency response of amplifier
Here, f1 is called lower cutoff frequency; f2 is called upper cutoff frequency. These are also called 3 dB frequencies
Bandwidth is: BW = f2 – f1 - (3.36)
Analysis of frequency response curve of RC coupled amplifier
At low frequencies, reactance of coupling capacitors is high. So, part of input does not reach the transistor. So gain reduces. Also at low frequencies reactance of emitter bypass capacitors is high. So, ac component of emitter current is not fully bypassed. Hence there will be ac voltage drop across RE, which reduces gain.
At high frequencies, reactance of shunt capacitances due to wiring and reactance of junction capacitances will become low. This offers low reactance path for signal to ground, thus reducing voltage gain.
At mid frequencies, reactance of coupling and emitter bypass capacitors is low; reactance of shunt capacitances is high. So there is no loss of signal. Hence gain is constant.
Note that this is only a qualitative analysis; exact analysis of RC coupled amplifier is not required at this stage.
Problems
1. An amplifier is known to have a power gain of 40 dB. If the output power is 4 watts, determine the input power.
2. What output power is obtained from an amplifier whose power gain is 55 dB, when the input power is 1 mW?
3. In a three-stage amplifier, the gain of first stage is 40 dB, gain of second stage is 200 (not in dB) and that of third stage is 0 dB. Find the overall gain of the amplifier.
CHAPTER 4
OPERATIONAL AMPLIFIERS
4.1 Introduction: “An opamp is a very high gain directly coupled amplifier which can amplify signals having wide range of frequencies.”
The term operational amplifier refers to a class of high-gain DC coupled amplifiers with two inputs and a single output. The modern integrated circuit version is typified by the famous 741 op-amp .Op-amps are high gain amplifier, and are used almost invariably with overall loop-feedback
[pic]
Figure 4.1 Op-Amp
4.2 Amplifier Circuit model:
The circuit model of an amplifier is shown in Figure (centre dashed box, with an input port and an output port). The input port plays a passive role, producing no voltage of its own, and is modelled by a resistive element Ri called the input resistance. The output port is modelled by a dependent voltage source AVi in series with the output resistance Ro, where Vi is the potential difference between the input port terminals. Figure 1 shows a complete amplifier circuit, which consists of an input voltage source Vs in series with the source resistance Rs, and an output “load” resistance RL. From this figure, it can be seen that we have voltage-divider circuits at both the input port and the output port of the amplifier. This requires us to re-calculate Vi and Vo whenever a different source and/or load is used:
[pic] [pic]
Figure 4.2: Circuit model of an amplifier circuit.
4.3 The Operational Amplifier: Ideal Op-Amp Model
The amplifier model shown in Figure 1 is redrawn in Figure 2 showing the standard op-amp notation. An op-amp is a “differential-to-single-ended” amplifier, i.e., it amplifies the voltage difference Vp – Vn = Vi at the input port and produces a voltage Vo at the output port that is referenced to the ground node of the circuit in which the op-amp is used.
Figure 4.3.1: Standard op-amp Figure 4.3.2: Ideal op-amp
The ideal op-amp model was derived to simplify circuit analysis and it is commonly used by engineers for first-order approximate calculations. The ideal model makes three simplifying assumptions:
Gain is infinite: A = ∞
Input resistance is infinite: Ri = ∞
Output resistance is zero: Ro= 0
Applying these assumptions to the standard op-amp model results in the ideal op-amp model shown in Figure 3. Because Ri = ∞ and the voltage difference Vp – Vn = Vi at the input port is finite, the input currents are zero for an ideal op-amp:
in = ip = 0
Hence there is no loading effect at the input port of an ideal op-amp:
[pic] (7)
In addition, because Ro = 0, there is no loading effect at the output port of an ideal op-amp: Vo = A * Vi (8)
Finally, because A = ∞ and Vo must be finite, Vi = Vp – Vn = 0, or
Vp = Vn (9)
4.4 The Ideal Op-amp: An Ideal Op-Amp has the following characteristics .
• An infinite voltage gain
• An infinite bandwidth
• An infinite input resistance: The resistance b/w V1 and V2 terminals is infinite .
• Zero output resistance: Vo remains constant no matter what resistance is applied across output.
• Perfect balance : When V1 is equal to V2 the Vo is 0
• Zero input offset voltage (i.e., exactly zero out if zero in)
• Infinite CMRR
• Infinite slew rate
• Zero input offset current
• The characteristic of an op-amp do not change with temperature
4.5 The 741 Op-amp
The most common and most famous op-amp is the mA741C or just 741, which is packaged in an 8-pin mini-DIP. Here is the pin-out for a typical 741 op-amp in a DIP (Dual In-line Package).
Figure 4.5.1:Pin-out for a typical 741 op-amp
OPAMP Characteristics/ Parameters:
1. output offset voltage Voo: The actual value of the output voltage when the inputs of an op-amp are zero is called the output offset voltage. Output offset voltage is basically due to two distinct phenomenon. a)input offset voltage b) input bias current
2. Input bias current(Ib): It is the average of the current that flows in to the inverting and non inverting input terminals of the opamp.
3. Input offset current(Iio): it is the algebraic difference between the currents flowing in to non inverting and inverting terminals.
4. Input resistance (Ri): It is the equivalent resistance that can be measured at either the inverting or non-inverting terminal with the other terminal connected to ground.
5. CMRR: This is a figure of merit for an opamp. It is defined as the ratio of the differential gain to the common mode gain.
6. Slew Rate: It is defined as the maximum rate of change of output voltage per unit time
7. SVRR: Supply Voltage Rejection Ratio: The change in opamp input offset voltage caused by variations in supply voltage is called SVRR.
8. Output resistance (Ro): The equivalent resistance can be measured between the output terminal of opamp and the ground.
Common Mode Gain:
Recall that the op-amp amplifies the difference between the two input signals V+ and V-, i.e. Vo = Aol(V+ - V-). So by this equation, if both input signals are the same then the output will be zero. However, this is not the case in real op-amps. Any signal common to both inputs will also be amplified by a common mode gain.
The common mode gain, Acm, is the ratio of the output voltage, Vo, to the common mode input signal, Vcm, i.e. Vo = AcmVcm. For two independent input signals, the common mode signal is often taken to be the average of the two input signal voltages, i.e. Vo = Acm((V+ + V-) / 2) So the final gain equation is: Vo = Aol(V+ - V-) + Acm((V+ + V-) / 2) To limit the effects of common mode gain on the output signal, the open loop gain, Aol, needs to be much larger than the common mode gain, Acm. The common mode rejection ratio (CMRR) is a measure of the 'quality' of the op-amp to reject common mode signals (the higher the better) and is defined as:
CMRR = Aol / Acm
CMRR is often expressed in dB:
CMRR = 20 log10(Aol / Acm) dB
The Effect of Common Mode Gain
Common mode gain affects the closed loop gain of the non-inverting amplifier as follows:
Vo = ViÃol(1 + 1/CMRR)
where Ãcl is the 'ideal' closed loop gain, i.e. Ãcl = 1 + R2/R1
Use the tool below to see the effect of common mode gain on the non-inverting amplifier.
Practical considerations: common-mode gain
As stated before, an ideal differential amplifier only amplifies the voltage difference between its two inputs. If the two inputs of a differential amplifier were to be shorted together (thus ensuring zero potential difference between them), there should be no change in output voltage for any amount of voltage applied between those two shorted inputs and ground:
Voltage that is common between either of the inputs and ground, as "Vcommon-mode" is in this case, is called common-mode voltage. As we vary this common voltage, the perfect differential amplifier's output voltage should hold absolutely steady (no change in output for any arbitrary change in common-mode input). This translates to a common-mode voltage gain of zero.
The operational amplifier, being a differential amplifier with high differential gain, would ideally have zero common-mode gain as well. In real life, however, this is not easily attained. Thus, common-mode voltages will invariably have some effect on the op-amp's output voltage.
The performance of a real op-amp in this regard is most commonly measured in terms of its differential voltage gain (how much it amplifies the difference between two input voltages) versus its common-mode voltage gain (how much it amplifies a common-mode voltage). The ratio of the former to the latter is called the common-mode rejection ratio, abbreviated as CMRR:
An ideal op-amp, with zero common-mode gain would have an infinite CMRR. Real op-amps have high CMRRs, the ubiquitous 741 having something around 70 dB, which works out to a little over 3,000 in terms of a ratio. Because the common mode rejection ratio in a typical op-amp is so high, common-mode gain is usually not a great concern in circuits where the op-amp is being used with negative feedback. If the common-mode input voltage of an amplifier circuit were to suddenly change, thus producing a corresponding change in the output due to common-mode gain, that change in output would be quickly corrected as negative feedback and differential gain (being much greater than common-mode gain) worked to bring the system back to equilibrium. Sure enough, a change might be seen at the output, but it would be a lot smaller than what you might expect.
A consideration to keep in mind, though, is common-mode gain in differential op-amp circuits such as instrumentation amplifiers. Outside of the op-amp's sealed package and extremely high differential gain, we may find common-mode gain introduced by an imbalance of resistor values. To demonstrate this, we'll run a SPICE analysis on an instrumentation amplifier with inputs shorted together (no differential voltage), imposing a common-mode voltage to see what happens. First, we'll run the analysis showing the output voltage of a perfectly balanced circuit. We should expect to see no change in output voltage as the common-mode voltage changes:
Common-mode rejection ratio:
The common-mode rejection ratio (CMRR) of an amplifier (or other device) measures the tendency of the device to reject input signals common to both input leads. A high CMRR is important in applications where the signal of interest is represented by a small voltage fluctuation superimposed on a (possibly large) voltage offset, or when relevant information is contained in the voltage difference between two signals. (An example is audio transmission over balanced lines.)
The CMRR, measured in positive decibels, is defined by the following equation:
where Ad is the differential gain and As is the common-mode gain. This is a very important specification, as it indicates how much of the common-mode signal will appear in your measurement. The value of the CMRR often depends on signal frequency as well, and must be specified as a function thereof.
CMRR is often important in reducing noise on transmission lines. For example, when measuring a thermocouple in a noisy environment, the noise from the environment appears as an offset on both input leads, making it a common-mode voltage signal. The CMRR of the measurement instrument determines the attenuation applied to the offset or noise.
Applications of OPAMP:
Operational amplifiers can be used to perform mathematical operations on voltage signals such as inversion, addition, subtraction, integration, differentiation, and multiplication by a constant
Inverting amplifier:
Inverts and amplifies a voltage (multiplies by a negative constant)
Zin = Rin (because V − is a virtual ground)
Expression for gain:
Assuming that the input difference is small, we can write KCL at the inverting node: (Notice the little red dot at the inverting node in the circuit diagram.) (Note also, that we have defined two voltages, V1 and Vout that are both measured with respect to the ground.)
[pic]
Here's the KCL equation using the assumption that the voltage at the amplifier input - at the input node - is zero.
I1 + I0 = 0
Technically, we can write KCL in terms of all the voltages involved (taking V+ and V- as the voltages - with respect to ground - at the "+" and "-" terminals respectively). Doing that we obtain:
( V1 - V- )/R1 + ( Vout - V- )/R0 = 0
However, since we assume that there is no voltage difference between V+ and V-, we can replace V- with V+ and we have the inverting input terminal connected to ground, so V- = 0. That means we get:
V1/R1 + Vout / R0 = 0
Note that the situation where V+ ” 0 happens so often that it has a common name. The non-inverting terminal in a connection like this - where the inverting input terminal is connected to ground - is called a virtual ground.
Vout = - V1 R0 / R1
There are two things to note about this expression for the output voltage.
The input voltage is multiplied by a constant that depends only upon the two resistors, R0 and R1. Properties of the amplifier that are used in the argument for this expression are:
Very large gain (approaching infinity) Very large input resistance between the two input terminals
Non-inverting amplifier:
Amplifies a voltage (multiplies by a constant greater than 1)
[pic](realistically, the input impedance of the op-amp itself, 1 MΩ to 10 TΩ)
10
Expression for gain [pic] and [pic]
From these calculations, we can see that the effective voltage gain of the noninverting amplifier is still set by the resistance ratio Rf/Rin, but is one greater than this ratio. Thus, if the two resistors are of equal value, the non-inverting gain will be 2, rather than 1. To get a non-inverting gain of 1, we can simply eliminate both Rf and Rin, and connect the output directly to the (-) input. We would eliminate Rs at the same time, or else use equal resistances in series with the two inputs.
Voltage follower:
Used as a buffer amplifier to eliminate loading effects or to interface impedances (connecting a device with a high source impedance to a device with a low input impedance)
[pic] (realistically, the differential input impedance of the op-amp itself, 1 MΩ to 1 TΩ)
Summing amplifier:
Sums several (weighted) voltages
When [pic], and Rf independent
[pic]
When [pic]
[pic]
Output is inverted, Input impedance Zn = Rn, for each input (V − is a virtual ground)
Subtractor:
The subtractor provides an output which is equal to the difference of the two input signals or proportional to their difference . For minimum offset error R1 || R2 = R3 || R4
Integrator:
Integrates the (inverted) signal over time
(where Vin and Vout are functions of time, V initial is the output voltage of the integrator at time t = 0.) Note that this can also be viewed as a type of electronic filter
Differentiators:
Differentiate the (inverted) signal over time.
(where Vin and Vout are functions of time)
Comparator :
Compares two voltages and outputs one of two states depending on which is greater
[pic]
Problems:
1. Determine the gain of the amplifier shown in fig below given R0=100Ώ R1=4.7k Ώ
2. For the circuit of non inverting amplifier with R1=10 k Ώ and R0=100k Ώ determine
i) Closed loop gain Af ii) output voltage Vo
3.In this circuit, you have it set up for a gain of -10. The input voltage is 0.24V. What is the output voltage?
4.For the same conditions as in Problem 2, the input is changed to -0.35 volts. What is the output voltage now?
3
4
5
6
Op-amp voltage comparator
[pic]
A simple op-amp comparator
An operational amplifier (op-amp) has a well balanced difference input and a very high gain. The parallels in the characteristics allows the op-amps to serve as comparators in some functions.[1]
A standard op-amp operating in open loop configuration (without negative feedback) can be used as a comparator. When the non-inverting input (V+) is at a higher voltage than the inverting input (V-), the high gain of the op-amp causes it to output the most positive voltage it can. When the non-inverting input (V+) drops below the inverting input (V-), the op-amp outputs the most negative voltage it can. Since the output voltage is limited by the supply voltage, for an op-amp that uses a balanced, split supply, (powered by ± VS) this action can be written:
Vout = Ao(V1 − V2)
A comparator is designed to produce well limited output voltages that easily interface with digital logic. Compatibility with digital logic must be verified while using an op-amp as a comparator.
Schmitt trigger:
Schmitt trigger is a comparator circuit that incorporates positive feedback.In the non-inverting configuration, when the input is higher than a certain chosen threshold, the output is high; when the input is below a different (lower) chosen threshold, the output is low; when the input is between the two, the output retains its value. The trigger is so named because the output retains its value until the input changes sufficiently to trigger a change. This dual threshold action is called hysteresis, and implies that the Schmitt trigger has some memory. In fact, the Schmitt trigger is a bistable multivibrator.
The symbol for Schmitt triggers in circuit diagrams is a triangle with an inverting or non-inverting hysteresis symbol. The symbol depicts the corresponding ideal hysteresis curve.
|[pic] | |[pic] |
|Standard Schmitt trigger | |Inverting Schmitt trigger |
Schmitt triggers are commonly implemented using a comparator] connected to have positive feedback (i.e., instead of the usual negative feedback used in operational amplifier circuits). For this circuit, the switching occurs near ground, with the amount of hysteresis controlled by the resistances of R1 and R2:
[pic]
The comparator extracts the sign of the difference between its two inputs. When the non-inverting (+) input is at a higher voltage than the inverting (−) input, the comparator output switches to +VS, which is its high supply voltage. When the non-inverting (+) input is at a lower voltage than the inverting (−) input, the comparator output switches to -VS, which is its low supply voltage. In this case, the inverting (−) input is grounded, and so the comparator implements the sign function – its 2-state output (i.e., either high or low) always has the same sign as the continuous input at its non-inverting (+) terminal.
Because of the resistor network connecting the Schmitt trigger input, the non-inverting (+) terminal of the comparator, and the comparator output, the Schmitt trigger acts like a comparator that switches at a different point depending on whether the output of the comparator is high or low. For very negative inputs, the output will be low, and for very positive inputs, the output will be high, and so this is an implementation of a "non-inverting" Schmitt trigger. However, for intermediate inputs, the state of the output depends on both the input and the output. For instance, if the Schmitt trigger is currently in the high state, the output will be at the positive power supply rail (+VS). V+ is then a voltage divider between Vin and +VS. The comparator will switch when V+=0 (ground). Current conservation shows that this requires
[pic]
and so Vin must drop below [pic] to get the output to switch. Once the comparator output has switched to −VS, the threshold becomes [pic] to switch back to high.
Typical hysteresis curve (which matches the curve shown on a Schmitt trigger symbol)
So this circuit creates a switching band centered around zero, with trigger levels [pic]. The input voltage must rise above the top of the band, and then below the bottom of the band, for the output to switch on and then back off. If R1 is zero or R2 is infinity (i.e., an open circuit), the band collapses to zero width, and it behaves as a standard comparator. The output characteristic is shown in the picture on the right. The value of the threshold T is given by [pic] and the maximum value of the output M is the power supply rail.
A practical Schmitt trigger configuration is shown below.
[pic]
The output characteristic has exactly the same shape of the previous basic configuration, and the threshold values are the same as well. On the other hand, in the previous case, the output voltage was depending on the power supply, while now it is defined by the Zener diodes. In this configuration, the output levels can be modified by appropriate choice of Zener diode, and these levels are resistant to power supply fluctuations (i.e., they increase the PSRR of the comparator). The resistor R3 is there to limit the current through the diodes, and the resistor R4 minimizes the input voltage offset caused by the comparator's input leakage currents.
Feedback concepts
Introduction:
Feedback plays an important role in electronic circuits and the basic parameters such as input resistance, output resistance, current gain or voltage gain and bandwidth
may be considerably changed by the use of feedback for a given amplifier.
Feedback The process of combining a fraction of the output back to its input is called feedback. The network coupling employed for the process of feedback is called feedback network.
Basic feedback amplifier is as shown
Input Vi Output
Vs
βVo
It consist of an amplifier with a gain A and a feedback network with feedback fraction β and drives an error signal β Vo. Depending upon whether the feedback energy aids or opposes the input signal, there are two basic types of feed backs in amplifiers. They are positive feedback and negative feedback.
Positive feedback:
When the feedback is in phase to the input the input signal increases this type of feedback is called positive feedback.
Here Vi=Vs+Vf or Ii= Is+If
V s, is source signals
Vi , I i input signals to amplifiers
Vf, if feedback signals
Positive feedback increases the gain of amplifier and also increases noise, distortion and reduces stability of an amplifier. Because of these disadvantages, +ve feedback is seldom used in amplifiers. But +ve feedback is used in oscillators.
Negative feedback:
When the feedback is in opposition to the input, the input signal reduces this type of feedback is called Negative feedback or degenerative feedback.
Here Vi = Vs – Vf or Ii = Is - If
Negative feedback reduces gain of the amplifier. It also reduces noise, distortion and instability and increases the bandwidth. Due to these advantages negative feedback is used in amplifiers.
Gain of feedback amplifier
I/P Is O/P
The output quantity (current or voltage) is sampled by a suitable sampler which is of two types current or voltage, and fed to the feedback network. The output of the feedback network is combined with source signal through a mixer and fed to the basic amplifier. Mixer also known as comparator is of two types, namely series mixer and shunt mixer.
A -------> gain of the basic amplifier = Io/Ii
(Open loop gain)
B ------->feedback ratio = If/Io
Af ------->gain of the feedback amplifier = Io/Is
Is ------>AC signal in the input (current or voltage)
If ------->feedback signal (V or I)
For positive feedback:
Af = Io/Is = Io/Ii – If [[pic]Ii = Is + If ]
= [pic] = [pic] = A/1 – Aβ
Aβ ------> called loop gain
| Af | > |A|
When |Aβ| =1 , Af = ∞
That is amp. given output without input amplifier acts as an oscillator.
For negative feedback:
Af = Io/Is = Io/Ii + If [[pic]Ic = Is - If ]
= [pic] = [pic] = A/(1 + Aβ)
Difference between +ve and -ve feedback
|Positive feedback |Negative feedback |
|Gain increases |Gain decreases |
|Noise increases |Noise decreases |
|Distortion increases |Distortion decreases |
|Bandwidth decreases |Bandwidth increases |
|Stability decreases |Stability increases |
|Input and output resistance changes |Input and output resistance changes |
|Used in oscillators |Used in amplifiers |
OSCILLATORS
An oscillator is a circuit that produces an AC signal without any externally applied input signal or an oscillator is a circuit which converts DC energy into AC energy a desired frequency.
Oscillations whose amplitude keeps decreasing with time are called damped oscillations and oscillators whose amplitude remains constant are called undamped or sustained oscillations. Oscillators use positive feedback for producing sustained oscillations.
Essential components of an oscillator are
1) Tank / oscillatory circuit
2) Amplifier
3) Feedback circuit
Tank / oscillatory circuit consist of an inductor (or resistor) in parallel with a capacitor. The frequency of oscillations in the circuit depends upon the values of L, C or R, C [f=1/2π√LC or f = 1 / 2πRC].
Amplifier receives DC power from the battery and converts it into AC power for supplying it to the tank circuit. Oscillations of that tank circuit are fed to the amplifiers which are amplified due to the active devices amplifying action.
Feedback circuit supplies a part of the output energy to the tank circuit in correct phase to meet the losses in order to produce undamped oscillations.
Types of oscillators:
The oscillators may be classified in the following ways:
1) According to the waveform generated:
a) Sinusoidal ―generates sine
b) Non sinusoidal / relaxation oscillators ―like square, triangular, sweep etc.
2) According to the fundamental mechanism involved :
a) Feedback oscillator ―utilize positive feedback
b) Negative resistance oscillator ―A negative resistance is produced by suitably operating the active device to neutralize the positive resistance of the oscillating circuit.
3) According to the type of circuitry :
a) LC oscillators / Tuned circuit oscillators
b) RC oscillators
c) Crystal oscillators
4) According to the frequency generated :
a) Audio frequency Oscillators [AFO] ; up to 20 KHz
b) Radio frequency oscillators [RFO] ; 20 KHz to 30 MHz
c) Very high frequency oscillators [VHF] ; 30 MHz to 300 MHz
d) Ultra high frequency oscillators [UHF] ; 300 MHz to 3 GHz
e) Micro wave frequency oscillators ; above 3 GHz
Barkhausen Criterion for oscillations
The conditions for a circuit to produce undamped (sustained) oscillations are
a) The feedback must be positive
b) The loop gain must be equal to one with zero phase shift
i.e. Avβ = 1
The second condition is called Barkhausen criterion for oscillations.
In general Av and Avβ are complex quantities
(Avβ) real = 1 ―decides the condition for oscillations
(Avβ) Img = 0 ―determines the frequency of oscillations.
555 Timer
The 8-pin 555 timer must be one of the most useful ICs ever made and it is used in many projects. With just a few external components it can be used to build many circuits, not all of them involve timing.
The 555 can be used with a supply voltage (Vs) in the range 4.5 to 15V (18V absolute maximum).
Square wave generator:
Square wave outputs are generated when the op-amp is forced to operate in saturation region. That is the output of the op-amp repeatedly swings between positive (+Vsat ≈ +VCC) and negative saturation (-Vsat ≈ -VEE), resulting in a square wave output. This square wave generator is also known as free-running or astable multivibrator. The output of the op-amp will be either positive or negative depending on whether the differential voltage vid is negative or positive respectively.
[pic][pic]
Fig : (a)Square Wave generator (b) waveform across output and capacitor
Triangular wave generator:
The output of a integrator is triangular wave for a square wave input. This means a triangular wave generator can be formed by simply connecting an integrator to a square wave generator.
[pic]
Fig: Triangular waveform generator
Filters:
An electric filter is often a frequency selective circuit that passes a particular band of frequencies and blocks or attenuates the signals of frequencies outside this band.
Filters can be classified as
1. Analog or Digital: depending on if they are designed to process analog or digital signals.
2. Audio (AF) or Radio frequency (RF).
3. Passive or active: depending on the elements used in the filter circuit.
A passive filter uses only passive elements such as resistors, capacitors and inductors. Active filters on the other hand use transistors and op-amps in addition to the passive elements. The elements used dictate the operating frequency range of the filters. In audio frequencies, inductors are not often used as they are large, costly and may dissipate more power. Also inductors emit magnetic field.
An active filter has following advantages over passive filters
1. Gain and frequency adjustment flexibility: Since the op-amp is providing some gain the input signal is not attenuated as in case of the passive filters. Aslo they are easier to tune and adjust.
2. No loading problem: Because of high input resistance and low output resistance the active filter does not cause loading of the input source and the output load.
3. Cost: Typically, they are cheaper due to availability of cheap op-amps and the absence of inductors in the circuit.
Although active filters are most extensively used in the field of communications and signal processing, they are employed in one form or another in almost all sophisticated electronic systems. Radio, television, telephone, radar, space satellites, and biomedical equipment are but a few systems that employ active filters. The most commonly used filters are these:
Low-pass filter - allows low frequencies to pass and attenuates high frequencies
High pass filter - allows high frequencies to pass and attenuates low frequencies
Band pass filter - allows a range of frequencies to pass
Band stop filter - attenuates a range of frequencies and allows all frequencies not within the range to pass
A low-pass filter has constant gain for low frequency signals but attenuates signals with frequencies higher than the cutoff frequency fH. At fH the gain is down 3dB and decreases further as frequency increases. The frequencies between 0 Hz and fH are known as passband frequencies while the range of frequencies beyond fH are attenuated and are therefore called the stop-band frequencies.
High Pass Filter:
A high-pass filter with a stopband 0 < f < fL and a passband f > fL is shown in figure.b. Here fL is the lower cut-off frequency and f is the operating frequency.
Band Pass Filter:
A band-pass filter has a passband between two cut-off frequencies fH and fL where fH > fL and two stopbands at 0 < f < fL and f > fH. The bandwidth of the band-pass filter is, therefore, equal to fH – fL.
Band Stop Filter:
Band-stop filter is exactly opposite to the band-pass filter in performance i.e., it has a bandstop between two cut-off frequencies fH and fL and two passbands, 0 < f < fL and f > fH..
All Pass Filter:
This filter passes all frequencies equally well (i.e. the output and input voltages are equal in magnitude for all frequencies) but with the phase shift between the two; phase shift being a function of the input frequency. The highest frequency up to which the magnitudes of the input and output remain equal depends on the unity gain BW of the op-amp. At this frequency, however, the phase shift between the input and output is maximum.
First-order low-pass Butterworth filter:
Fig shows first-order low-pass Butterworth filter that uses an RC network for filtering. Note that the op-amp is used in non-inverting configuration and hence it does not load down the RC network. Resistirs R1 and RF determine the gain of the filter.
[pic]
Fig:First-order low-pass Butterworth filter
The output voltage vo is given by,
[pic]
Where AF = [pic] the passband gain of the filter.
f = frequency of the input signal fH is the high (or upper) cutoff frequency of the filter.
fH = [pic]
The gain magnitude and phase angle equations for the filter can be obtained as
[pic]
[pic]
The operation of the low-pass filter can be verified from the gain magnitude equation:
1. At very low frequencies that is f < fH ,
[pic]
2. At cut-off frequency, that is f = fH,
[pic]
3. At higher frequencies that is f > fH
[pic]
First Order High Pass Butterworth Filter
Fig shows a first-order high-pass filter that uses an RC network for filtering. The circuit is formed by interchanging the positions of R and C from the low-pass filter circuit.
[pic]
First-order High-pass Butterworth filter
The output voltage vo is given by,
[pic]
Where AF = [pic] the pass band gain of the filter.
f = frequency of the input signal and fL is the lower cutoff frequency of the filter.
fL = [pic]
The gain magnitude for the filter can be obtained as
[pic]
Band-pass filter:
A band pass filter has a passband frequency between two cutoff frequencies fH and fL such that fH > fL. Any input frequency outside the passband frequencies is attenuated. Basically there are two types of band-pass filters: 1. Narrow band-pass and 2.wide band-pass filters. Unfortunately, there is no set dividing line between the two.
However, a band-pass filter is defined as a wide band-pass if its figure of merit or quality factor Q is less than 10 while the band-pass filters with Q > 10 are called the narrow band-pass filters. Thus Q is a measure of selectivity, meaning the higher the value of Q the more selective is the filter, or the narrower is the bandwidth (BW). The relationship between Q, 3-db bandwidth, and the centre frequency fC is given by
[pic]
For a wide band-pass filter the centre frequency can be defined as.[pic]
In a narrow band-pass filter, the output voltage peaks at the centre frequency fc.
[pic]
A wide band-pass filter can be formed by simply cascading high-pass and low-pass sections and is generally the choice for simplicity of design and performance though such a circuit can be realized by a number of possible circuits. To form a ± 20 db/ decade band-pass filter, a first-order high-pass and a first-order low-pass sections are cascaded; for a ± 40 db/decade band-pass filter, second-order high- pass filter and a second-order low-pass filter are connected in series, and so on. It means that, the order of the band-pass filter is governed by the order of the high-pass and low-pass filters
.[pic]
Narrow band-pass filter
[pic]
A narrow band-pass filter employing multiple feedbacks is depicted in figure. This filter employs only one op-amp, as shown in the figure. In comparison to all the filters discussed so far, this filter has some unique features that are given below.
1. It has two feedback paths, and this is the reason that it is called a multiple-feedback filter.
2. The op-amp is used in the inverting mode.
The frequency response of a narrow band-pass filter is shown in fig(b).
Generally, the narrow band-pass filter is designed for specific values of centre frequency fc and Q or fc and BW. The circuit components are determined from the following relationships. For simplification of design calculations each of C1 and C2 may be taken equal to C.
R1 = Q/2π fc CAf
R2 =Q/2π fc C(2Q2-Af)
and R3 = Q / π fc C
where Af, is the gain at centre frequency and is given as
Af = R3 / 2R1
The gain Af however must satisfy the condition Af < 2 Q2.
The centre frequency fc of the multiple feedback filter can be changed to a new frequency fc‘ without changing, the gain or bandwidth. This is achieved simply by changing R2 to R’2 so that
R’2 = R2 [fc/f’c]2
Narrow Band-Stop Filter
[pic][pic]
This is also called a notch filter. It is commonly used for attenuation of a single frequency such as 60 Hz power line frequency hum. The most widely used notch filter is the twin-T network illustrated in fig. (a). This is a passive filter composed of two T-shaped networks. One T-network is made up of two resistors and a capacitor, while the other is made of two capacitors and a resistor.One drawback of above notch filter (passive twin-T network) is that it has relatively low figure of merit Q. However, Q of the network can be increased significantly if it is used with the voltage follower, as illustrated in fig. (a). Here the output of the voltage follower is supplied back to the junction of R/2 and 2 C. The frequency response of the active notch filter is shown in fig (b).
[pic]
Notch filters are most commonly used in communications and biomedical instruments for eliminating the undesired frequencies.
A mathematical analysis of this circuit shows that it acts as a lead-lag circuit with a phase angle, shown in fig. (b). Again, there is a frequency fc at which the phase shift is equal to 0°. In fig. (c), the voltage gain is equal to 1 at low and high frequencies. In between, there is a frequency fc at which voltage gain drops to zero. Thus such a filter notches out, or blocks frequencies near fc. The frequency at which maximum attenuation occurs is called the notch-out frequency given by
fn = Fc = 2πRC
Notice that two upper capacitors are C while the capacitor in the centre of the network is 2 C. Similarly, the two lower resistors are R but the resistor in the centre of the network is 1/2 R. This relationship must always be maintained.
All-pass filter is that which passes all frequency components of the input signal without attenuation but provides predictable phase shifts for different frequencies of the input signals. The all-pass filters are also called delay equalizers or phase correctors. An all-pass filter with the output lagging behind the input is illustrated in figure.
[pic]
The output voltage Vout, of the filter circuit shown in fig, can be obtained by using the superposition theorem
Vout = Vin [-1 +( 2/ j2πRfc)]
or Vout / Vin = 1- j2∏Rfc/1+ j2πRfc
where / is the frequency of the input signal in Hz.
From equations given above it is obvious that the amplitude of vout / vin is unity, that is |vout | = |vin| throughout the useful frequency range and the phase shift between the input and output voltages is a function of frequency.
By interchanging the positions of R and C in the circuit, the output can be made leading the input. These filters are most commonly used in communications. For instance, when signals are transmitted over transmission lines (such as telephone wires) from one point to another point, they undergo change in phase. To compensate for such phase changes, all-pass filters are employed.
Chapter 4
DIGITAL ELECTRONICS
In analog system, the output can be continuously controlled by the input & the output is linearly proportional to the input. In digital system, the digital logic used only two values, either HIGH or LOW. i.e. they have only two discrete values and are called BINARY. The binary may be either logic 0 or logic ‘1’. A logic value of ‘0’ or ‘1’ is often called as BINARY DIGIT or BIT.
Number System: Many number systems are used in digital technology. Most common are binary, decimal, octal & hexadecimal system.
Binary Number system: A number system that uses only two digits ‘0’&’1’ is called binary number system. The binary umber system is also called as Base 2 system or Radix 2 system.
Examples: (100010)2
(0.1011)2
Convert the given binary number into decimal equivalent number
1. (100010)2=0×20+1×21+0×22+0×23+0×24+1×25
=0+2+0+0+0+32
=(34)10
2. (0.1011)2=1×2-1+0×2-2+1×2-3+1×2-4
=0.5+0+0.125+0.0625
=(0.6875)10
3. (10101.011)2
Integer part: (10101)2=1×20+0×21+1×22+0×23+1×24
=1+0+4+0+16 = (21)10
Decimal part: (0.011)2 =0×2-1+1×2-2+1×2-3
= (0.375)10
= (21.375)10
Octal Number System: A number system that uses 8 digit (0-7) is called an octal number system. It has base 8. Example: (723)8, (676)8
Hexadecimal Number System: The hexadecimal number system has base 16. It has 16 distinct digit symbols. It uses the digits 0-9 & letters A,B,C,D,E,F as 16 digit symbols.
|Hexadecimal number system |Equivalent binary number |
| |8 4 2 1 (weights) |
|0 |0 0 0 0 |
|1 |0 0 0 1 |
|2 |0 0 1 0 |
|3 |0 0 1 1 |
|4 |0 1 0 0 |
|5 |0 1 0 1 |
|6 |0 1 1 0 |
|7 |0 1 1 1 |
|8 |1 0 0 0 |
|9 |1 0 0 1 |
|10 |1 0 1 0 = A |
|11 |1 0 1 1 = B |
|12 |1 1 0 0 = C |
|13 |1 1 0 1 = D |
|14 |1 1 1 0 = E |
|15 |1 1 1 1 = F |
|Octal Numbers |Binary Equivalent number |
| |4 2 1 (weights) |
|0 |0 0 0 |
|1 |0 0 1 |
|2 |0 1 0 |
|3 |0 1 1 |
|4 |1 0 0 |
|5 |1 0 1 |
|6 |1 1 0 |
|7 |1 1 1 |
Convert the following octal number into decimal number system
1. (2376)8 = (?)10
= 2×83+3×82+7×81+6×80
= 1024+192+56+6
= (1278)10
2. (1234.567)8=1×83+2×82+3×81+4×80 +5×8-1+6×8-2+7×8-3
=512+128+24+4+0.625+0.09375+0.01367
= (668.7324219)10
Convert the following hexadecimal number into decimal number system
1. (269)16=2×162+6×161+9×160
= 2×256+96+9
= (617)10
2. 2B8D.E2)16=2×163+11×162+8×161+13×160 +14×16-1+2×16-2
= 8192+2816+128+13+0.875+0.0078125
= (11149.88281)10
Conversion form Decimal number system to Binary number system:
The given decimal number is repeatedly divided by 2, which is the base number of binary system till quotient becomes ‘0’ and collect the remainder from bottom to top.
To convert the fractional part into binary, multiply fraction by 2 repeatedly, record any carry in integer place. The string of integer obtained from top to bottom gives the equivalent fraction in binary number system.
1. (734)10=(X)2
[pic]
Take the numbers from bottom to top,
(734)10 = ( 1011011110)2
2. (0.705)10
0.705×2=1.410 ---1
0.410×2=0.820 ---0
0.82×2= 1.64------1
0.64×2= 1.28------1
0.28×2= 0.56------0
0.56×2=1.12-------1
0.12×2=0.24-------0
0.24×2=0.48-------0
0.48×2=0.96-------0
0.96×2=1.92-------1
Take the number from top to bottom, (0.705)10 = (0.1011010001)2
3.(41.915)10
(41)10 = (101001)2
0.915×2=1.830---1
0.830×2=1.660---1
0.660×2=1.320---1
0.32×2=0.64------0
0.64×2= 1.28-----1
(0.915)10 = (11101)2
(41.915)10= (101001.11101)2
Conversion form Decimal number system to Octal number system:
To convert a decimal number (integer) into a octal equivalent, repeatedly divide by 8 and take the remainder string from bottom to top.
For traction part repeatedly multiplied by 8, record carry in integer place & take the string of integer from top to bottom.
1.(2003)10=(X)8
[pic][pic]
Take the numbers from bottom to top, (2003)10= (3723)8
2.(0.12)10 = (X)8
0.12×8=0.96---0
0.96×8=7.68---7
0.68×8=5.44---5
0.44×8=3.52---3
0.52×8=4.16---4
(0.12)10=(0.07534)8
3. (632.97) 10=(?)8
[pic]
(632) 10=(1170)8
0.97×8=7.76---7
0.76×8=6.08---6
0.08×8=0.64---0
0.64×8=5.12---5
0.12×8=0.96---0
(0.97)10 =(0.76050) 8
(632.97)10= (1170.76050)8
Decimal number system to Hexadecimal number system:
To convert a decimal number (integer) into a hexadecimal equivalent, repeatedly divide by 16 and take the remainder string from bottom to top.
For traction part repeatedly multiplied by 16, record carry in integer place & take the string of integer from top to bottom.
1. (0.368)10
0.368×16=5.888---5
0.888×16=14.208-14-E
0.208×16=3.328---3
0.328×16=5.248---5
0.248×16=3.968---3
(0.368)10=(0.5E353)16
2. (22.64)10= (?)8
[pic]
(22)10= (16)16
0.64×16=10.24---10-A
0.24×16=3.84-----3
0.84×16=13.44—13-D
0.44×16=7.04---7
0.04×16=0.64---0
(22.64)10=(16.A3D70)16
Conversion from Octal number system into Binary number system:
When an octal number is to be converted to its equivalent binary number, each of its digits is replaced by equivalent group of three binary digits.
1. (632)8
|6 |3 |2 |
|110 |011 |010 |
So, (632)8=(110011010)2
2. (7423.245)8
|7 |4 |2 |3 |. |2 |4 |5 |
|111 |100 |010 |011 |. |010 |100 |101 |
(7423.245)8= (111100010011.010100101)2
Conversion from Binary number system to Octal number system:
To convert, Starting from the binary point, the binary digits are arranged in groups of three on both sides. Each in group of binary digit is replaced by its octal equivalent.
Note: 0’s can be added on either side, if needed to complete a group of three.
1. (011101.110)2=(?)8
|011 |101 |. |110 |
|3 |5 |. |6 |
(011101.110)2= (35.6)8
2. (11101101110.11111)2
|011 |101 |101 |110 |. |111 |110 |
|3 |5 |5 |6 |. |7 |6 |
(11101101110.11111)2 =(3556.72)8
Conversion from Hexadecimal number system to Binary number system
When a hexadecimal number is to be converted its equivalent binary number, each of its digits is replaced by equivalent group of 4 binary digits.
1.(347.28)16
|3 |4 |7 |. |2 |8 |
|0011 |0100 |0111 |. |0010 |1000 |
(347.28)16= (001101000111.00101000)2
2. (8BE6.7A)16
|8 |B |E |6 |. |7 |A |
|1000 |1011 |1110 |0110 |. |0111 |1010 |
(8BE6.7A) 16 = (1000101111100110.01111010)2
Conversion from Binary number system to Hexadecimal number system:
To convert, Starting from the binary point, the binary digits are arranged in groups of four on both sides. Each in group of binary digit is replaced by its hexadecimal equivalent. Note: 0’s can be added on either side, if needed to complete a group of four.
1.(1011011110111110.11100011)2= (?)16
|1011 |0111 |1011 |1110 |. |1110 |0011 |
|B |7 |B |E |. |E |3 |
(1011011110111110.11100011)2= (B7BE.E3)16
2. (110111101.01)2=(?)16
|0001 |1011 |1101 |. |0100 |
|1 |B |D |. |4 |
(110111101.01)2=(1BD.4)16
Conversion from Octal number system to Hexadecimal number system:
Write down the three bit binary equivalent of octal digit and then rearranging into group of four bits with ‘0’s added on either side of decimal point, if needed to complete the group of four.
1.(46) 8 = (?)16
|Octal equivalent | 4 6 |
| |100 110 |
|Hexadecimal equivalent |0010 0110 |
| |2 6 |
(46) 8 = (26)16
2. (764.352) 8 = (?)16
|Octal equivalent | 7 6 4 . 3 5 2 |
| |111 110 100.011 101 010 |
|Hexadecimal equivalent |0001 1111 0100.0111 0101 0000 |
| |1 F 4 . 7 5 0 |
(764.352) 8 = (1F4.750)16
Conversion from Hexadecimal number system to Octal number system:
First write down the 4 bit binary equivalent of hexadecimal digit and then rearranging into group of three bit each.
1.(2AB.9) 16 = (?)8
|Hexadecimal equivalent | 2 A B . 9 |
| |0010 1010 1011 . 1001 |
|Octal equivalent |001 010 101 011 . 100 100 |
| |1 2 5 3 . 4 4 |
(2AB.9) 16 = (1253.44)8
2. (3FC.82) 16 = (?)8
|Hexadecimal equivalent | 3 F C . 8 2 |
| |0011 1111 1100 . 1000 0010 |
|Octal equivalent |001 111 111 100 . 100 000 100 |
| |1 7 7 4 . 4 0 4 |
(3FC.82) 16 = (1774.404)8
BCD Numbers:
The Binary Coded Decimal (BCD) is a combination of four binary digits that represent decimal numbers. It is also called 8421 code. It has four bits and represents the decimal digits 0 to 9. Below table gives the BCD codes for the decimal number 0 to 15.
|Decimal number |BCD number |
|0 |0000 |
|1 |0001 |
|2 |0010 |
|3 |0011 |
|4 |0100 |
|5 |0101 |
|6 |0110 |
|7 |0111 |
|8 |1000 |
|9 |1001 |
|10 |0001 0000 |
|11 |0001 0001 |
|12 |0001 0010 |
|13 |0001 0011 |
|14 |0001 0100 |
|15 |0001 0101 |
Represent the (743.3)10 in BCD
|7 |4 |3 |. |6 |
|0111 |0100 |0011 |. |0110 |
(743.3)10=(0111010000110110) BCD
Convert the following BCD into Decimal:
11011100001001
|0011 |0111 |0000 |1001 |
|3 |7 |0 |9 |
(11011100001001) BCD=(3709)10
Binary Addition: The rules adopted for binary additions are
|0 |0 |1 |1 |
|+0 |+1 |+0 |+1 |
|C=0 |S=0 |C=0 |S=1 |C=0 |S=1 |C=1 |S=0 |
The sum of two 1’s gives binary ‘10’ i.e.2, there is a carry. The carry is taken to the next higher column.
1.(1010)2+(0111)2
| 1010 =10 |
|+0111 =7 |
| 10001 =17 |
(1010)2+(0111)2=(10001)2
2. (101)2+(011)2
| 101=5 |
|+011=3 |
|1000=8 |
(101)2+(011)2=(1000)2
Addition in Octal number System: Add the digit in each column in decimal and convert this sum into octal. Write the sum in that column and carry the carry term to the next higher significant column.
Add ( 334.65)8 to (671.14) 8
|3 |3 |4 |. |6 |5 |
|6 |7 |1 |. |1 |4 |
|10 |10 |6 |. |8 |9 |
|C=1 |S=2 |C=1 |S=2 |C=0 |S=6 |
|1 |5 |C |. |7 |1 |
|9 |16 |23 |. |13 |8 |
|C=0 |S=9 |
|10101 |01010 |
|11100 |00011 |
|1111 |0000 |
1’s complement subtraction:
Step1: Add minuend to the 1’s complement of the subtrahend.
Step2: Inspect the result obtained in step1 for an end carry. (a) If an end carry occurs, add 1 to the least significant bit. (end round carry) (b) If an end carry doesn’t occur, take 1’s complement of the number obtained in step1 and place a negative sign in front of it.
1. ( 1000)2 from (1101)2
1101—minuend
1000— subtrahend
1’s complement of subtrahend = 0111
Add minuend and 1’s complement of subtrahend,
| |1 |1 |0 |1 |
|+ |0 |1 |1 |1 |
|1 |0 |1 |0 |0 |
|End carry |Add to LSB | | |+1 |
| |0 |1 |0 |1 |
(1101)2 - ( 1000)2= (0101)2
2. ( 0101)2 from (1111)2
1111—minuend
0101— subtrahend
1’s complement of subtrahend = 1010
Add minuend and 1’s complement of subtrahend,
| |1 |1 |1 |1 |
|+ |1 |0 |1 |0 |
|1 |1 |0 |0 |1 |
|End carry |Add to LSB | | |+1 |
| |1 |0 |1 |0 |
(1111)2 - ( 0101)2= (1010)2
3. (6)10-(14)10
6=0110—minuend
14=1110— subtrahend
1’s complement of subtrahend = 0001
Add minuend and 1’s complement of subtrahend,
| |0 |1 |1 |0 |
|+ |0 |0 |0 |1 |
|No End carry |0 |1 |1 |1 |
Take 1’s complement of the 0111 & place negative sign in front of it =-1000
(0110)2 - ( 1110)2= -(1000)2
2’s complement:
To find the 2’s form of any binary number, obtain the 1’s complement of the given number and then add ‘1’ to the LSB.
(100100)2
Take 1’s complement of the number = 011011
Add ‘1’ to LSB to get 2’s complement = 011011
+1
011100
2’s complement = (011100)2
2’s complement subtraction:
Step1: find 2’s complement of subtrahend
Step2: Add minuend and 2’s complement subtrahend
Step3: (a) If an end carry occurs, discard it. (b) If an end carry doesn’t occur, take 2’s complement of the number obtained in step2 and place a negative sign in front of it.
1.(1111)2-(1100)2
1111—minuend
1100— subtrahend
2’s complement of subtrahend = 0100
Add minuend and 2’s complement of subtrahend,
| |1 |1 |1 |1 |
|+ |0 |1 |0 |0 |
|1 |0 |0 |1 |1 |
|Neglect end carry| | | | |
(1111)2-(1100)2=(0011)2
2.(15)10-(31)10
(1111)2-(11111)2
1111—minuend
11111— subtrahend
2’s complement of subtrahend = 00001
Add minuend and 2’s complement of subtrahend,
| |0 |1 |1 |1 |1 |
|+ |0 |0 |0 |0 |1 |
|No end carry |1 |0 |0 |0 |0 |
So, take the 2’s complement of the answer and place negative sign in front of it,
i.e.= -(10000)2
(1111)2-(11111)2= -(10000)2
9’s complement:
The 9’s complement of a decimal number is formed by subtracting each digit form 9.
Find the 9’s complement of the number (8147)10
|9 |9 |9 |9 |
|8 |1 |4 |7 |
|1 |8 |5 |2 |
9’s complement of (8147)10 is (1852)10
9’s complement subtraction:
Step1: Add minuend to the 9’s complement of the subtrahend.
Step2: Inspect the result obtained in step1 for an end carry. (a) If an end carry occurs, add 1 to the least significant bit. (end round carry) (b) If an end carry doesn’t occur, take 1’s complement of the number obtained in step1 and place a negative sign in front of it.
1. ( 487)10 - (354)10
487—minuend
354— subtrahend
9’s complement of subtrahend = 645
Add minuend and 9’s complement of subtrahend,
| |4 |8 |7 |
|+ |6 |4 |5 |
|1 |1 |3 |2 |
|End carry |Add to LSB | |+1 |
| |1 |3 |3 |
( 487)10 - (354)10 = (133)10
2.( 213)10 - (546)10
213—minuend
546— subtrahend
9’s complement of subtrahend = 453
Add minuend and 9’s complement of subtrahend,
| |2 |1 |3 |
|+ |4 |5 |3 |
|No |6 |6 |6 |
|End carry | | | |
Take the 9’s complement of the answer (666)10 and place the negative sign in front of it.
i.e.= -(333)10
( 213)10 - (546)10= -(333)10
10’s complements:
The 10’s complement of the decimal number is equal to 9’s complement of number plus 1.
Find 10’s complement of ( 731)10
| 999 |
|-731 |
| 268 9’s complement |
| +1 |
|269 10’s complement |
10’s complement of ( 731)10is( 269)10
10’s complement subtraction:
Step1: find 10’s complement of subtrahend
Step2: Add minuend and 10’s complement subtrahend
Step3: (a) If an end carry occurs, discard it. (b) If an end carry doesn’t occur, take 10’s complement of the number obtained in step2 and place a negative sign in front of it.
1. (347)10-(265)10
347—minuend
265— subtrahend
10’s complement of subtrahend = 735
Add minuend and 10’s complement of subtrahend,
| |3 |4 |7 |
|+ |7 |3 |5 |
|1 |0 |8 |2 |
|Neglect end carry | | | |
(347)10-(265)10=(082)10
2. (23)10-(64)10
23—minuend
64— subtrahend
10’s complement of subtrahend = 36
Add minuend and 10’s complement of subtrahend,
| |2 |3 |
|+ |3 |6 |
|No end carry |5 |9 |
So, take the10’s complement of the answer and place negative sign in front of it, i.e.= -(41)10
Problems:
1. Subtract using 1’s complement
a. (1101) 2-(11001) 2
b. (1111) 2-(1011) 2
c. (110011) 2-(100101) 2
d. (10001) 2from(10011) 2
2. Subtract using 2’s complement
a. (1101) 2-(11001) 2
b. 125 and -68
c. -83 and +16
d. (1111) 2-(1101) 2
e. (10111) 2-(10011) 2
f. (1101) 2-(1001) 2
3. Subtract using 7’s and 8’s complement method
a. (4317.64) 8from(42.345) 8
b. (2447.15) 8 from (6573.16) 8
4. Subtract using 9’s and 10’s complement method
a. (8437) 10 –( 27) 10
b. (308) 10-(1333) 10
c. (320.3 44) 10-(1048.05) 10
5. Subtract using 15’s and 16’s complement method
a. (A47) 16-(843) 16
b. (1B76) 16-(4A) 16
c. (231.AC) 16-(22.AB) 16
BOOLEAN ALGEBRA
George Boole in 1854 invented a new kind of algebra known as Boolean algebra. It is sometimes called switching algebra. Boolean algebra is the mathematical frame work on which logic design based. It is used in synthesis & analysis of binary logical function.
Basic Laws of Boolean algebra:
1. Laws of complementation: The term complement means invert. i.e. to change 0’s to 1’s and 1’ to 0’s. The following are the laws of complement.[pic]=1; [pic] = 0; [pic]=A.
2. “ OR” laws
0+0=0; 0+1=1; 1+0=1;1+1=1
1+A=1; A+[pic]=1; A+A=A; 1+[pic]=1
3. “ AND’ laws
0.0=0; 0.1=0;1.0=0; 1.1=1; A. [pic]=0; A.A=A
Commutative Law:
Property 1: This states that the ord3r in which the variables OR’ed makes no difference in output. i.e. A+B=B+A
|A |B |A+B | |B |A |B+A |
|0 |0 |0 | |0 |0 |0 |
|0 |1 |1 |= |1 |0 |1 |
|1 |0 |1 | |0 |1 |1 |
|1 |1 |1 | |1 |1 |1 |
Property 2: This property of multiplication states that the order in which the variables are AND’ed makes no difference in the output. i.e. A.B=B.A
|A |B |A.B | |B |A |B.A |
|0 |0 |0 | |0 |0 |0 |
|0 |1 |0 |= |1 |0 |0 |
|1 |0 |0 | |0 |1 |0 |
|1 |1 |1 | |1 |1 |1 |
Associative property:
Property1: This property states that in the OR’ing of the several variables, the result is same regardless of grouping of variables. For three variables i.e.(A OR’ed with B)or’ed with C is same as A OR’ed with (B OR’ed with C)
i.e. (A+B)+C = A+(B+C)
|A |B |C |A+B |B+C |(A+B)+C | |A+(B+C) |
|0 |0 |0 |0 |0 |0 | |0 |
|0 |0 |1 |0 |1 |1 | |1 |
|0 |1 |0 |1 |1 |1 | |1 |
|0 |1 |1 |1 |1 |1 |= |1 |
|1 |0 |0 |1 |0 |1 | |1 |
|1 |0 |1 |1 |1 |1 | |1 |
|1 |1 |0 |1 |1 |1 | |1 |
|1 |1 |1 |1 |1 |1 | |1 |
Property2: The associative property of multiplication states that, it makes no difference in what order the variables are grouped when AND’ing several variables. For three variables(A AND’ed B)AND’ed C is same as A AND’ed (B AND’ed C)
i.e. (A.B)C = A(B.C)
|[pic]A |B |C |A.B |B.C |(A.B)C | |A(B.C) |
|0 |0 |0 |0 |0 |0 | |0 |
|0 |0 |1 |0 |0 |0 | |0 |
|0 |1 |0 |0 |0 |0 | |0 |
|0 |1 |1 |0 |1 |0 |= |0 |
|1 |0 |0 |0 |0 |0 | |0 |
|1 |0 |1 |0 |0 |0 | |0 |
|1 |1 |0 |1 |0 |0 | |0 |
|1 |1 |1 |1 |1 |1 | |1 |
Distributive property:
Property 1: A(B+C) = A.B + A.C
|1 |2 |3 |4 |5 |6 |7 |8 |
|A |B |C |B+C |A(B+C) |A.B |A.C |A.B+A.C |
|0 |0 |0 |0 |0 |0 |0 |0 |
|0 |0 |1 |1 |0 |0 |0 |0 |
|0 |1 |0 |1 |0 |0 |0 |0 |
|0 |1 |1 |1 |0 |0 |0 |0 |
|1 |0 |0 |0 |0 |0 |0 |0 |
|1 |0 |1 |1 |1 |0 |1 |1 |
|1 |1 |0 |1 |1 |1 |0 |1 |
|1 |1 |1 |1 |1 |1 |1 |1 |
Column number 5= Column number 8, hence the proof.
Property 2: A+[pic]B = A+B
|A |B |[pic] |[pic]B |A+[pic]B | |A+B |
|0 |0 |1 |0 |0 | |0 |
|0 |1 |1 |1 |1 |= |1 |
|1 |0 |0 |0 |1 | |1 |
|1 |1 |0 |0 |1 | |1 |
Duality:
The important property to Boolean algebra is called Duality principle. The Dual of any expression can be obtained easily by the following rules.
1. Change all 0’s to 1’s
2. Change all 1’s to 0’s
3. .’s (dot’s) are replaced by +’s (plus)
4. +’s (plus) are replaced by .’s (dot’s)
Examples:
[pic]=1≡ [pic]=0
X +0=X ≡ X .1=X
X+Y=Y+X ≡ X.Y=Y.X
X+1=0 ≡ X.0=1
De Morgon’s Theorems:
It is one of the important properties of Boolean algebra. It is extensively useful in simplifying complex Boolean expression.
De Morgon’s First Theorem:
It states that “ the complements of product of two variables equal to sum of the complements of individual variable”.
i.e. [pic] = [pic]+[pic]
|A |B |[pic] |[pic] |A.B |[pic] | |[pic]+[pic] |
|0 |0 |1 |1 |0 |1 | |1 |
|0 |1 |1 |0 |0 |1 |≡ |1 |
|1 |0 |0 |1 |0 |1 | |1 |
|1 |1 |0 |0 |1 |0 | |0 |
De Morgon’s Second Theorem:
It states that complement of sum of two variables is equal to product of complement of two individual variables.
i.e.[pic]= [pic].[pic]
|A |B |[pic] |[pic] |A+B |[pic] | |[pic].[pic] |
|0 |0 |1 |1 |0 |1 | |1 |
|0 |1 |1 |0 |1 |0 |≡ |0 |
|1 |0 |0 |1 |1 |0 | |0 |
|1 |1 |0 |0 |1 |0 | |0 |
Simplify the Boolean expression
1. [pic][pic]Z+ [pic]YZ
=[pic]Z[[pic]+Y]
=[pic]Z[1]= [pic]Z
2. f=X([pic]+Y)
=X[pic]+XY = 0+XY= XY
3. f = B(A+C)+C
=BA+BC+C
=BA+C(1+B)
=BA+C
4.XY+XYZ+XY[pic]+[pic]YZ
=XY(Z+[pic])+XYZ+XY[pic]+[pic]YZ
XYZ+XY[pic]+XY[pic]+[pic]YZ+XYZ
XYZ(1+1)+XY[pic](1+1)+ [pic]YZ
XYZ+XY[pic]+[pic]YZ
XY(Z+[pic])+[pic]YZ
XY+[pic]YZ
Y(X+[pic]Z)
Y(X+Z)
5.XYZ+[pic]Y + XY[pic]
=Y([pic] + X[pic])+ XY[pic]
= Y([pic] + [pic])+ XY[pic]
= Y[pic] +Y[pic]+ XY[pic]
=Y[pic] +Y(Z+ X[pic])
=Y[pic] +Y(Z+ X)
=Y(Z+[pic]+X)
=Y(Z+1)
=Y
6. Y(W[pic]+WZ)+XY
=YW[pic]+YWZ+XY
=YW([pic]+Z)+XY
=YW+XY
=Y(W+X)
7. ABC+[pic]BC+A[pic]C+AB[pic]=AB+BC+CA
LHS: ABC+[pic]BC+A[pic]C+AB[pic]
BC[A+[pic]]+A[pic]C+AB[pic]
=BC+A[pic]C+AB[pic]
=C[B+[pic]A]+AB[pic]
=C[B+A]+AB[pic]
BC+AC=AB[pic]
=BC+A[C+[pic]B]
=BC+A[C+B]
= AB+BC+CA = RHS
8. (A+B)(A+C)=A+BC
(A+B)(A+C)= A.A+A.C+B.A+B.C
=A+AC+A.B+B.C
=A(1+C)+BA+BC
= A.1+BA+BC
=A(1+B)+BC
= A+BC
Logic Gates:
It is an electronic circuit, which makes logic decisions. A logic gate is a digital circuit with one or more input signal and only one output signal. All input or output signals either low voltage or high voltage. A digital circuit is referred to as logic gate for simple reason i.e. it can be analyzed based on Boolean algebra.
To make logical decisions, three gates are used. They are OR, AND and NOT gate. These logic gates are building blocks, which are available in the form of IC.
The input and output of the binary variables for each gate can be represented in a tabular column or truth table.
OR Gate:
The OR gate performs logical additions commonly known as OR function. The OR gate has two or more inputs and only one output. The operation of OR gate is such that a HIGH(1) on the output is produced when any of the input is HIGH. The output is LOW(0) only when all the inputs are LOW.
If A & B are the input variables of an OR gate and c is its output, then A+B. similarly for more than two variables, the OR function can be expressed as Y=A+B+C.
2
3 Logical Symbol: Two Input OR gate
[pic]
Truth table for two input OR gate:
|Input |Output |
|A |B |Y= A+B |
|0 |0 |0 |
|0 |1 |1 |
|1 |0 |1 |
|1 |1 |1 |
Realization of OR gate using diodes:
Two input OR gate using "diode-resistor" logic is shown in figure below. Where X, Y are the inputs and F is the output.
[pic]
• If X = 0 and Y = 0, the both the diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off and thus F is low.
• If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus pulling F to HIGH
• If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulling F to HIGH.
• If X = 1 and Y = 1, the both the diodes D1 and D2 are forward biased and thus both the diodes conduct and thus F is HIGH
AND Gate:
The AND gate performs logical multiplication, commonly known as AND function. The AND gate has two or more inputs and a single output. The output of an AND gate is HIGH only when all the inputs are HIGH. Even if any one of the input is LOW, the output will be LOW. If a & b are input variables of an AND gate and c is its output, then Y=A.B
4 Logical Symbol: Two input AND gate
[pic]
Truth table for two input AND gate:
|Input |Output |
|A |B |Y=A.B |
|0 |0 |0 |
|0 |1 |0 |
|1 |0 |0 |
|1 |1 |1 |
Realization of AND gate using diodes:
Two input AND gate using "diode-resistor" logic is shown in figure below. Where X, Y are inputs and F is the output.
[pic]
• If X = 0 and Y = 0, the both the diodes D1 and D2 are forward biased and thus both the diodes conduct and pulling F to LOW.
• If X = 0 and Y = 1, D1 is reverse biased, thus does not conduct. But D2 is forward biased, thus conducts and thus pulling F to LOW.
• If X = 1 and Y = 0, D2 is reverse biased, thus does not conduct. But D1 is forward biased, thus conducts and thus pulling F to LOW.
• If X = 1 and Y = 1, the both the diodes D1 and D2 are reverse biased and thus both the diodes are in cut-off and thus there is no drop in voltage at F. Thus F is HIGH.
Not Gate (Inverter):
The NOT gate performs the basic logical function called inversion or complementation. The purpose of his gate is to convert one logic level into the opposite logic level. It has one input and one output. When a HIGH level is applied to an inverter, a LOW level appears at the output and vice-versa.
Logical Symbol:
[pic]
Truth Table:
|Input |output |
|A |Y=[pic] |
|0 |1 |
|1 |0 |
Realization of NOT gate using Transistors:
A NOT gate using a transistor is shown in below figure. ‘A’ represents the input and ‘F’ represents the output. When the input is HIGH, the transistor is in the ON state and the output is LOW. If the input is LOW, the transistor is in the OFF state and the output F is HIGH.
[pic]
• If A = 0, then the transistor is OFF thus pulling F to HIGH.
• If A = 1, then the transistor is ON thus driving F to HIGH.
NAND Gate:
The output of a NAND gate is LOW only when all inputs are HIGH and output of the NAND is HIGH if one or more inputs are LOW.
Logical Symbol: Two input AND gate
[pic]
Truth Table:
|Input |Output |
|A |B |Y = [pic] |
|0 |0 |1 |
|0 |1 |1 |
|1 |0 |1 |
|1 |1 |0 |
NOR Gate:
The output of the NOR gate is HIGH only when all the inputs are LOW.
5
6 Logical Symbol: Two input NOR Gate
[pic]
Truth Table:
|Input |Output |
|A |B |Y =[pic] |
|0 |0 |1 |
|0 |1 |0 |
|1 |0 |0 |
|1 |1 |0 |
XOR Gate or Exclusive OR gate:
In this gate output is HIGH only when any one of the input is HIGH. The circuit is also called as inequality comparator, because it produces output when two inputs are different.
7 Logical Symbol: Two input XOR Gate
[pic]
Truth Table:
|Input |Output |
|A |B |Y =[pic] |
|0 |0 |0 |
|0 |1 |1 |
|1 |0 |1 |
|1 |1 |0 |
Y=[pic]=A[pic]+[pic]B
XNOR Gate or Exclusive NOR Gate:
An XNOR gate is a gate with two or more inputs and one output. XNOR operation is complementary of XOR operation. i.e. The output of XNOR gate is High, when all the inputs are identical; otherwise it is low.
Logical Symbol: Two input XNOR Gate:
[pic]
Truth Table:
|Input |Output |
|A |B |Y =[pic][pic]+AB |
|0 |0 |1 |
|0 |1 |0 |
|1 |0 |0 |
|1 |1 |1 |
Universal Logic Gate:
NAND and NOR gates are called Universal gates or Universal building blocks, because both can be used to implement any gate like AND,OR an NOT gates or any combination of these basic gates.
NAND gate as Universal gate
1. NOT operation:
[pic]
2. AND operation:
[pic]
3. OR operation:
[pic]
4. NOR operation:
[pic]
NOR gate as Universal gate:
1. NOT operation:
[pic]
2. AND operation:
[pic]
3. OR operation:
[pic]
4. NAND operation:
[pic]
Examples:
Draw the logic circuit for the Boolean expression.Y=[pic]BC+A[pic]C+ABC.
[pic]
Types of Digital Circuits:
Basically digital circuits can be classified into two types.
• Sequential Digital Circuits
• Combinational Digital Circuits
Sequential Digital Circuits:
The logic circuits whose output at any instant of time depend not only on the present input but also on the past outputs are called Sequential Circuits.
In sequential circuits, the output signals are feedback to the input side. Thus, an output signal is a function of present input signals and a sequences of the past input signal. i.e. the output signals.
Combinational Digital Circuits:
The logic circuits whose output at any instant of time are entirely dependent upon the input signals present at that time are known as combinational digital circuits. In particular, the output of the combinational circuit doesn’t depend upon any past input or output So that the circuit doesn’t possess any memory. The output signals of combinational circuits are not feedback to any other part of the circuit. Combinational circuit are faster, since the operation don’t have to be performed in sequences.
Combinational circuits can be constructed using sum of products (SOP) or product of sums (POS). Sum is logically OR operation of different literals or signals. Product is logically AND operation of different literals or signals.
SOP: It is sum of many products. That is literals are ORed first then those outputs are ANDed.
Eg: F1 = YZ +Z +XY
F2 = XYZ + W
POS: It is the product of many sums. That is literals are ANDed first then those outputs are ORed.
Eg: F1 = (Y+ Z)( + Z)(X+Y)
F2 = (X+Y+Z)W
Half Adder:
An electronic combinational circuit which performs the arithmetic addition of two binary digits is called Half Adder. In the half adder circuit, there are two inputs, one is addend and augend and two outputs are Sum and Carry.
|[pic] | |
| |Input |
| |Output |
|Logical Symbol | |
| |A |
| |B |
| |Sum |
| |Carry |
| | |
| |0 |
| |0 |
| |0 |
| |0 |
| | |
| |0 |
| |1 |
| |1 |
| |0 |
| | |
| |1 |
| |0 |
| |1 |
| |0 |
| | |
| |1 |
| |1 |
| |0 |
| |1 |
| | |
| |Truth Table for Half Adder |
Sum= [pic]B+A[pic]=A[pic]
Carry= A.B
The circuit for Half Adder using Basic Gates is as follows:
[pic]
The circuit for Half Adder using XOR gate:
[pic]
Full Adder:
The full adder is a combinational circuit that performs the arithmetic sum of three input bits.It consists of three inputs and two outputs. Two of the inputs are variables, denoted by A and B, represent the two significant bit to be added The third input Cin represents carry form the previous lower significant position.
Logical Symbol:
[pic]
Truth Table for Full Adder
|Input |Output |
|A |B |Cin |Sum |Carry |
|0 |0 |0 |0 |0 |
|0 |0 |1 |1 |0 |
|0 |1 |0 |1 |0 |
|0 |1 |1 |0 |1 |
|1 |0 |0 |1 |0 |
|1 |0 |1 |0 |1 |
|1 |1 |0 |0 |1 |
|1 |1 |1 |1 |1 |
Sum=[pic][pic]Cin+[pic]B[pic]+A[pic][pic]+ABCin
= [pic][[pic]Cin+ B[pic]]+A[[pic][pic]+BCin]
= [pic][B[pic]Cin]+A[[pic]]
= A[pic]B[pic]Cin
Carry = [pic]BCin+A[pic]Cin+AB[pic]+ABCin
= [pic]BCin+A[pic]Cin+AB([pic]+Cin)
= [pic]BCin+A[pic]Cin+AB
= [pic]BCin+A([pic]Cin+B)
= [pic]BCin+AB+ACin
= B([pic]Cin+A)+ACin
=B(A+Cin)+ACin
= AB+BCin+ACin
Implementation of Full Adder:
[pic]
8
9 Problems
1. Realize NOR and NAND gate using discrete components
2. Realize NOR and NAND gate using Basic gates
3. Implement Full Adder using Basic gates
4. Simplify and realize using only NAND gates
XYZ+XYZ+YZ+[pic]
(A+ [pic]+C) ([pic]+B+[pic])(A+[pic])
5. Simplify and realize using only NOR gates
Y=A[pic][pic]+[pic][pic][pic]+[pic][pic]+A[pic]
K Map:-
Karnaugh maps generally become more cluttered and hard to interpret when adding more variables. A general rule is that Karnaugh maps work well for up to four variables, and shouldn't be used at all for more than six variables. For expressions with larger numbers of variables, the Quine–McCluskey algorithm can be used. Nowadays in general the minimization process is carried out by computer, for which the Espresso heuristic logic minimizer has become the standard minimization program.
Procedures
The K-Map method may theoretically be applied for the simplification of any boolean expression regardless of its number of variables, but is most often used when there are fewer than six variables because K-Maps of expressions with more than six variables are complex and tedious to simplify. Each variable contributes two possibilities: the initial value, and its inverse; it therefore organizes all possibilities of the system. The variables are arranged in Gray code in which only one variable changes between two adjacent grid boxes.
Once the variables have been defined, the output possibilities are transcribed according to the grid location provided by the variables. Thus for every possibility of a boolean input or variable the output possibility is defined.
When the Karnaugh map has been completed, to derive a minimized function the "1s" or desired outputs are grouped into the largest possible rectangular groups in which the number of grid boxes (output possibilities) in the groups must be equal to a power of 2. For example, the groups may be 4 boxes in a line, 2 boxes high by 4 boxes long, 2 boxes by 2 boxes, and so on. "Don't care(s)" possibilities (generally represented by a "X") are grouped only if the group created is larger than the group with "Don't care" is excluded. The boxes can be used more than once only if it generates the least number of groups. Each "1" or desired output possibilities must be contained within at least one grouping.
The groups generated are then converted to a boolean expression by: locating and transcribing the variable possibility attributed to the box, and by the axiom laws of boolean algebra—in which if the (initial) variable possibility and its inverse are contained within the same group the variable term is removed. Each group provides a "product" to create a "sum-of-products" in the boolean expression.To determine the inverse of the Karnaugh map, the "0s" are grouped instead of the "1s". The two expressions are non-complementary
. Size of map
The size of the Karnaugh map with n Boolean variables is determined by 2n. The size of the group within a Karnaugh map with n Boolean variables and k number of terms in the resulting Boolean expression is determined by 2nk. Common sized maps are of 2 variables which is a 2×2 map, 3 variables which is a 2×4 map, and 4 variables which is a 4×4 map.
[pic]
[pic]
K-map of the given truth table will be as follows:
[pic]
Follwing are the examples for K-map optimization:
[pic][pic][pic]
Basic Flip-Flop Circuit
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are shown in Figure 2 and Figure 3. Each flip-flop has two outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is referred to as an SR flip-flop or SR latch. The flip-flop in Figure 2 has two useful states. When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and complement outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal output.
When a 1 is applied to both the set and reset inputs of the flip-flop in Figure 2, both Q and Q' outputs go to 0. This condition violates the fact that both outputs are complements of each other. In normal operation this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.
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(a) Logic diagram
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(b) Truth table
Figure 2. Basic flip-flop circuit with NOR gates
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(a) Logic diagram
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(b) Truth table
Figure 3. Basic flip-flop circuit with NAND gates
The NAND basic flip-flop circuit in Figure 3(a) operates with inputs normally at 1 unless the state of the flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition should be avoided in normal operation.
Clocked SR Flip-Flop: The clocked SR flip-flop shown in Figure 4 consists of a basic NOR flip-flop and two AND gates. The outputs of the two AND gates remain at 0 as long as the clock pulse (or CP) is 0, regardless of the S and R input values. When the clock pulse goes to 1, information from the S and R inputs passes through to the basic flip-flop. With both S=1 and R=1, the occurrence of a clock pulse causes both outputs to momentarily go to 0. When the pulse is removed, the state of the flip-flop is indeterminate, ie., either state may result, depending on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at the end of the pulse.
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(a) Logic diagram
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(b) Truth table
Figure 4. Clocked SR flip-flop
D Flip-Flop
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.
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(a) Logic diagram with NAND gates
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(b) Graphical symbol
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(c) Transition table
Figure 5. Clocked D flip-flop
JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop is set with a clock pulse only if Q' was previously 1.
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T flip-flop presented next.
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(a) Logic diagram
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(b) Graphical symbol
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(c) Transition table
Figure 6. Clocked JK flip-flop
COUNTERS:
In Figure 2, four Negative-Edge-Triggered J-K Flip-flops are connected in a cascade mode (the output Q of one Flip-flop is connected to the input CLOCK of the next Flip-flop) to form a Binary Counter. Inputs J and K of each Flip-flop are always 1, according to the Truth-Table, the Flip-flop changes its state upon each H to L transition of its CLOCK.
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Figure 1: Timing Diagram of the J-K Flip-flop Counter
In this Binary Counter, outputs A to D represent a 4-bit Binary Number, in which A is the LSB and D is the MSB.The 4-bit Binary Number is increased by one on each CLOCK cycle. The count goes from (0)10 to (15)10 and then cycles back to (0)10, Table 3.
|Decimal |Binary |
| |D |C |B |A |
| 0 |0 |0 |0 |0 |
|1 |0 |0 |0 |1 |
|2 |0 |0 |1 |0 |
|3 |0 |0 |1 |1 |
|4 |0 |1 |0 |0 |
|5 |0 |1 |0 |1 |
|6 |0 |1 |1 |0 |
|7 |0 |1 |1 |1 |
|8 |1 |0 |0 |0 |
|9 |1 |0 |0 |1 |
|10 |1 |0 |1 |0 |
|11 |1 |0 |1 |1 |
|12 |1 |1 |0 |0 |
|13 |1 |1 |0 |1 |
|14 |1 |1 |1 |0 |
|15 |1 |1 |1 |1 |
Table 3: Truth-Table of a 4-bit Binary Counter
Ripple counter
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Fig. Output waveforms
The basic idea behind this is when J and K inputs are high in a JK filpflops the output value gets toggled.
Assume that A, B, C, and D are lamps and that all the FFs are reset. The lamps will all be out, and the count indicated will be 00002. The negative-going pulse of clock pulse 1 causes FF1 to set. This lights lamp A, and we have a count of 00012. The negative-going pulse of clock pulse 2 toggles FF1, causing it to reset. This negative-going input to FF2 causes it to set and causes B to light. The count after two clock pulses is 00102, or 210. Clock pulse 3 causes FF1 to set and lights lamp A. The setting of FF1 does not affect FF2, and lamp B stays lit. After three clock pulses, the indicated count is 00112. Clock pulse 4 causes FF1 to reset, which causes FF2 to reset, which causes FF3 to set, giving us a count of 01002. This step shows the ripple effect. This setting and resetting of the FFs will continue until all the FFs are set and all the lamps are lit. At that time the count will be 11112 or 1510. Clock pulse 16 will cause FF1 to reset and lamp A to go out. This will cause FF2 through FF4 to reset, in order, and will extinguish lamps B, C, and D. The counter would then start at 00012 on clock pulse 17. To display a count of 1610 or 100002, we would need to add another FF. The ripple counter is also called an ASYNCHRONOUS counter. Asynchronous means that the events (setting and resetting of FFs) occur one after the other rather than all at once. Because the ripple count is asynchronous, it can produce erroneous indications when the clock speed is high. A high-speed clock can cause the lower stage FFs to change state before the upper stages have reacted to the previous clock pulse. The errors are produced by the FFs’ inability to keep up with the clock.
Ripple Up/down counter
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Here And-Or logic is used to implement Up down counter. When Up/down signal is high all upper and gates enabled. So all Q values are considered and it upcounts. When When Up/down signal is low all lower And gates enabled. So all Q bar values are considered and it downcounts.
SHIFT REGISTER
The term register can be used in a variety of specific applications, but in all cases it refers to a group of flip-flops operating as a coherent unit to hold data. This is different from a counter, which is a group of flip-flops operating to generate new data by tabulating it.
In this context, a counter can be viewed as a specialized kind of register, which counts events and thereby generates data, rather than just holding the data or changing the way it is handled. More commonly, however, counters are treated separately from registers. The two are then handled as separate concepts which work together in many applications, and which have some features in common.
The demonstration circuit below is known as a shift register because data is shifted through it, from flip-flop to flip-flop. If you apply one byte (8 bits) of data to the initial data input one bit at a time, and apply one clock pulse to the circuit after setting each bit of data, you will find the entire byte present at the flip-flop outputs in parallel format. Therefore, this circuit is known as a serial-in, parallel-out shift register. It is also known sometimes as a shift-in register, or as a serial-to-parallel shift register.
By standardized convention, the least significant bit (LSB) of the byte is shifted in first.
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IC555 and timers
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Figure 555 timer
The 555 timer consists of two voltage comparators, a bistable flip-flop, a discharge transistor, and a resistor divider network. To understand the basic concept of the timer let’s first examine the timer in block form as in Figure. The resistive divider network is used to set the comparator levels. Since all three resistors are of equal value, the threshold comparator is referenced internally at 2/3 of supply voltage level and the trigger comparator is referenced at 1/3 of supply voltage. The outputs of the comparators are tied to the bistable flip-flop. When the trigger voltage is moved below 1/3 of the supply, the comparator changes state and sets the flip-flop driving the output to a high state. The threshold pin normally monitors the capacitor voltage of the RC timing network. When the capacitor voltage exceeds 2/3 of the supply, the threshold comparator resets the flip flop which in turn drives the output to a low state. When the output is in a low state, the discharge transistor is “on”, thereby discharging the external timing capacitor. Once the capacitor is discharged, the timer will await another trigger pulse, the timing cycle having been completed.
Astable multivibrator
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Fig. Astable multivibrator
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Fig. Waveforms at the output and capacitor.
With the output high (+Vs) the capacitor C1 is charged by current flowing through R1 and R2. The threshold and trigger inputs monitor the capacitor voltage and when it reaches 2/3Vs (threshold voltage) the output becomes low and the discharge pin is connected to 0V.
The capacitor now discharges with current flowing through R2 into the discharge pin. When the voltage falls to 1/3Vs (trigger voltage) the output becomes high again and the discharge pin is disconnected, allowing the capacitor to start charging again.
This cycle repeats continuously unless the reset input is connected to 0V which forces the output low while reset is 0V.
An astable can be used to provide the clock signal for circuits such as counters.
A low frequency astable ( ................
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