ARMv7-M Architecture Reference Manual

[Pages:716]ARM?v7-M Architecture Reference Manual

Copyright ? 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3 (ID021910)

ARMv7-M Architecture Reference Manual

Copyright ? 2006-2010 ARM Limited. All rights reserved.

Release Information The following changes have been made to this document.

Change history

Date

Issue

Confidentiality

Change

June 2006

A

Non-confidential

Initial release

July 2007

B

Non-confidential

Second release, errata and changes documented separately

September 2008 C

Non-confidential, Restricted Access Options for additional watchpoint based trace in the DWT, plus errata updates and clarifications.

July 2009

C_errata

Non-confidential

Marked-up errata PDF, see page iii for more information.

February 2010 C_errata_v3 Non-confidential

Additional marked-up errata PDF, see page iii for more information.

Proprietary Notice

This ARM Architecture Reference Manual is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this ARM Architecture Reference Manual may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this ARM Architecture Reference Manual.

Your access to the information in this ARM Architecture Reference Manual is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture infringe any third party patents.

This ARM Architecture Reference Manual is provided "as is". ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this ARM Architecture Reference Manual is suitable for any particular purpose or that any practice or implementation of the contents of the ARM Architecture Reference Manual will not infringe any third party patents, copyrights, trade secrets, or other rights.

This ARM Architecture Reference Manual may include technical inaccuracies or typographical errors.

To the extent not prohibited by law, in no event will ARM be liable for any damages, including without limitation any direct loss, lost revenue, lost profits or data, special, indirect, consequential, incidental or punitive damages, however caused and regardless of the theory of liability, arising out of or related to any furnishing, practicing, modifying or any use of this ARM Architecture Reference Manual, even if ARM has been advised of the possibility of such damages.

Words and logos marked with ? or TM are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Copyright ? 2006-2010 ARM Limited

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Copyright ? 2006-2010 ARM Limited. All rights reserved. ARM DDI 0403C_errata_v3

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Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. This document is Non-Confidential but any disclosure by you is subject to you providing notice to and the acceptance by the recipient of, the conditions set out above.

In this document, where the term ARM is used to refer to the company it means "ARM or any of its subsidiaries as appropriate".

Note

The term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way.

Note

?

This errata PDF is regenerated from the source files of issue C of this document, but:

-- Some pseudocode examples, that are imported into the document, have been updated. Markups highlight significant changes in these pseudocode inserts.

Other pseudocode updates are made using the standard Acrobat editing tools.

-- Pages ii and iii of the PDF have been replaced, by an edit to the PDF, to include an updated Proprietary Notice.

With these exceptions, this PDF corresponds to the released PDF of issue C of the document, with errata indicated by markups to the PDF:

-- the original errata markups, issued June 2009, are identified as ARM_2009_Q2

-- additional errata markups, issued February 2010, are identified as ARM_2009_Q4.

?

In the revised pseudocode, the function BadReg(x) is replaced by a new construct, x IN {13,15}, that can be used

in other contexts. This is a format change only.

?

From February 2010, issue C of the ARMv7-M ARM is superseded by issue D of the document. ARM strongly

recommends you to use issue D of the document in preference to using this errata PDF.

ARM DDI 0403C_errata_v3 Copyright ? 2006-2010 ARM Limited. All rights reserved.

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Contents ARMv7-M Architecture Reference Manual

Part A

Chapter A1 Chapter A2

Chapter A3

Preface

About this manual .............................................................................. xviii Using this manual ............................................................................... xix Conventions ....................................................................................... xxii Further reading .................................................................................. xxiii Feedback .......................................................................................... xxiv

Application Level Architecture

Introduction

A1.1 The ARM Architecture ? M profile .................................................... A1-2

Application Level Programmers' Model

A2.1 About the Application level programmers' model ............................. A2-2 A2.2 ARM core data types and arithmetic ................................................ A2-3 A2.3 Registers and execution state ........................................................ A2-11 A2.4 Exceptions, faults and interrupts .................................................... A2-15 A2.5 Coprocessor support ...................................................................... A2-16

ARM Architecture Memory Model

A3.1 Address space ................................................................................. A3-2

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Contents

Chapter A4

Chapter A5 Chapter A6

Part B

Chapter B1 Chapter B2

A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8

Alignment support ............................................................................ A3-3 Endian support ................................................................................. A3-5 Synchronization and semaphores .................................................... A3-8 Memory types and attributes and the memory order model .......... A3-18 Access rights .................................................................................. A3-28 Memory access order .................................................................... A3-30 Caches and memory hierarchy ...................................................... A3-38

The ARMv7-M Instruction Set

A4.1 About the instruction set .................................................................. A4-2 A4.2 Unified Assembler Language ........................................................... A4-4 A4.3 Branch instructions .......................................................................... A4-7 A4.4 Data-processing instructions ............................................................ A4-8 A4.5 Status register access instructions ................................................ A4-15 A4.6 Load and store instructions ............................................................ A4-16 A4.7 Load/store multiple instructions ..................................................... A4-19 A4.8 Miscellaneous instructions ............................................................. A4-20 A4.9 Exception-generating instructions .................................................. A4-21 A4.10 Coprocessor instructions ............................................................... A4-22

Thumb Instruction Set Encoding

A5.1 Thumb instruction set encoding ....................................................... A5-2 A5.2 16-bit Thumb instruction encoding ................................................... A5-5 A5.3 32-bit Thumb instruction encoding ................................................. A5-13

Thumb Instruction Details

A6.1 Format of instruction descriptions .................................................... A6-2 A6.2 Standard assembler syntax fields .................................................... A6-7 A6.3 Conditional execution ....................................................................... A6-8 A6.4 Shifts applied to a register ............................................................. A6-12 A6.5 Memory accesses .......................................................................... A6-15 A6.6 Hint Instructions ............................................................................. A6-16 A6.7 Alphabetical list of ARMv7-M Thumb instructions .......................... A6-17

System Level Architecture

System Level Programmers' Model

B1.1 Introduction to the system level ....................................................... B1-2 B1.2 ARMv7-M: a memory mapped architecture ..................................... B1-3 B1.3 System level operation and terminology overview ........................... B1-4 B1.4 Registers .......................................................................................... B1-8 B1.5 Exception model ............................................................................ B1-14

System Memory Model

B2.1 Introduction ...................................................................................... B2-2

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Contents

Chapter B3 Chapter B4

Part C

Chapter C1

Appendix A

Appendix B Appendix C

B2.2 Pseudocode details of general memory system operations ............. B2-3

System Address Map

B3.1 The system address map ................................................................. B3-2 B3.2 System Control Space (SCS) ........................................................... B3-6 B3.3 System timer - SysTick .................................................................. B3-24 B3.4 Nested Vectored Interrupt Controller (NVIC) ................................. B3-28 B3.5 Protected Memory System Architecture (PMSAv7) ....................... B3-35

ARMv7-M System Instructions

B4.1 Alphabetical list of ARMv7-M system instructions ............................ B4-2

Debug Architecture

ARMv7-M Debug

C1.1 Introduction to debug ....................................................................... C1-2 C1.2 The Debug Access Port (DAP) ........................................................ C1-4 C1.3 Overview of the ARMv7-M debug features ...................................... C1-8 C1.4 Debug and reset ............................................................................ C1-13 C1.5 Debug event behavior .................................................................... C1-14 C1.6 Debug register support in the SCS ................................................ C1-19 C1.7 Instrumentation Trace Macrocell (ITM) support ............................. C1-27 C1.8 Data Watchpoint and Trace (DWT) support ................................... C1-33 C1.9 Embedded Trace (ETM) support .................................................... C1-56 C1.10 Trace Port Interface Unit (TPIU) .................................................... C1-57 C1.11 Flash Patch and Breakpoint (FPB) support .................................... C1-61

CPUID

A.1 Core Feature ID Registers ......................................................... AppxA-2 A.2 Processor Feature register0 (ID_PFR0) .................................... AppxA-4 A.3 Processor Feature register1 (ID_PFR1) .................................... AppxA-5 A.4 Debug Features register0 (ID_DFR0) ........................................ AppxA-6 A.5 Auxiliary Features register0 (ID_AFR0) ..................................... AppxA-7 A.6 Memory Model Feature registers ............................................... AppxA-8 A.7 Instruction Set Attribute registers ? background information ... AppxA-10 A.8 Instruction Set Attribute registers ? details ............................... AppxA-12

ARMv7-M infrastructure IDs

Legacy Instruction Mnemonics

C.1 Thumb instruction mnemonics ................................................... AppxC-2 C.2 Pre-UAL pseudo-instruction NOP .............................................. AppxC-6

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Contents

Appendix D Appendix E Appendix F Appendix G

Appendix H Appendix I

Deprecated Features in ARMv7-M

Debug ITM and DWT packet protocol

E.1 Packet Types ............................................................................. AppxE-2 E.2 DWT packet formats .................................................................. AppxE-8

ARMv7-R differences

F.1 Endian support ........................................................................... AppxF-2 F.2 Application level support ............................................................ AppxF-3 F.3 System level support .................................................................. AppxF-4 F.4 Debug support ........................................................................... AppxF-5

Pseudocode definition

G.1 Instruction encoding diagrams and pseudocode ...................... AppxG-2 G.2 Limitations of pseudocode ........................................................ AppxG-4 G.3 Data Types ................................................................................ AppxG-5 G.4 Expressions .............................................................................. AppxG-9 G.5 Operators and built-in functions .............................................. AppxG-11 G.6 Statements and program structure ......................................... AppxG-17 G.7 Miscellaneous helper procedures and functions ..................... AppxG-22

Pseudocode Index

H.1 Pseudocode operators and keywords ........................................ AppxH-2 H.2 Pseudocode functions and procedures ...................................... AppxH-5

Register Index

I.1

ARM core registers ..................................................................... AppxI-2

I.2

Memory mapped system registers .............................................. AppxI-3

I.3

Memory mapped debug registers ............................................... AppxI-5

Glossary

viii

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