Timing Constraints Lab - Rice University
Clean Start Lab
Clean Start Lab
Introduction
The purpose of this lab is to demonstrate a complete design starting from a “clean sheet”. The design is intended to be relatively simple.
Objective
After completing this lab, students will be able to:
• Create a completely new design from a “clean sheet” start to download.
Understand the basic design flow, as composed of Design Entry, Design Implementation, and in-system verification.
Procedure
Creating a new design with Xilinx Foundation Series Schematic
Start Foundation Series: Start ( Programs ( Xilinx Foundation Series ( Xilinx Foundation Project Manager.
In the Name edit box, type “mycount”, since this will be your counter design.
Under Directory, either type or Browse… to “C:\F14_LABS”.
Type should be “XACTstep M1”.
As necessary, change Family, Part, and Speed to “XC4000XL”, “4005XLPC84”, and “3”, respectively. Click .
1) A new project is created for you. Click on the Schematic Editor button on the right side. The Schematic Editor will appear with a clear sheet.
Creating a new schematic design in Foundation Express
Now you want to create a design that looks like this:
[pic]
Figure 1
2) First, click on the Symbols Toolbox icon [pic]. A window appears containing hundreds of symbols to choose from.
3) Type X74_160. This is a 4 bit counter TTL device. Highlight the correct macro, and then move your cursor onto the clean sheet, and click once to place the X74_160 macro.
4) Now you can start adding the other symbols – IPAD, IBUF, INV, AND2, OSC4, OBUF, OPAD.
5) Once you have added and positioned the various symbols, click again on the Symbols Toolbox icon, and the SC Symbols box will disappear.
6) Add wires, or nets, by clicking on the Draw Wires [pic] icon.
7) Label wires by double-clicking on the nets as shown in the schematic diagram above. Label macros by double-clicking on them and renaming the existing computer generated reference entries.
8) Add pin locations as attributes to the I/O pads. Do this by double-clicking each input and output pad, so that the Symbol Properties dialog box appears. Start with the input pad labelled A1 as shown in the schematic in Figure 1. Under Name, type “LOC“, for pin location. Under Description, type the appropriate pin number. For A1, using the X40 and XSTEND board, it is “P7”. Click on Add to add this attribute. Then double-click this entry twice so that two asterisks (**) appear by “LOC=P7”, as in the diagram below. This will make the full attribute text visible. Click Apply, then Move. This will apply the attribute and allow you to move the text to a comfortable location near the IO Pad.
[pic]
Once you finish creating the desired schematic, make sure to save it. Click File ( Save. Then return to the Foundation Project Manager ( Press + to task switch.)
9) The design entry is finished. Notice that “MYCOUNT1.SCH” has been added to the MYCOUNT Project Description File (PDF).
10) Now we must implement this design. Click on the Implement M1 button. Select “Yes” to update the netlist based on the last saved design. The software converts Foundation schematic files into an EDIF 2.0.0 netlist and opens up the Xilinx Design Manager.
11) Project mycount is highlighted. Select Design ( Implement... Make sure that the part selected is “XC4005XL-3-PC84”. Note also that this will be version ‘ver1’ and revision ‘rev1’. Click Run.
12) The M1 Implementation Tools will open the Flow Manager. This will Translate, Map, Place & Route, and create a bitstream for your design. This should take between 1 to 5 minutes.
[pic]
Flow Engine
Downloading Your Design
13) If you are using a Xilinx XChecker cable and the UW-FPGABOARD, then you would use the Hardware Debugger utility that comes with the Foundation or Alliance software. However, downloading to a Xilinx PLD can be done in many ways. All we are really doing is sending a bitstream to a chip.
With the XESS® XS40 and XS95 boards, this download is done via a basic parallel cable and the utility download software that comes with these boards.
14) Go to a DOS prompt. Start ( Programs ( Command Prompt (Note: The XS40/95 downloading utilities will soon be Windows based.)
15) Type “cd \f14_labs\mycount” and hit .
16) Make sure the cable is plugged in from the PC parallel port to the XS40-005XL board, the power is supplied to the board, and the jumpers on the XSTEND board are set up properly.
17) Type “xsload mycount.bit”. This will download the bitstream into the FPGA. (The 8031 and RAM are not used or accessed in this design.)
Immediately after downloading, the ‘clean’ design is operational. To get the LEDs to light up, toggle the DIPSWITCH SW1 and SW2 to the ON (‘1’), position to enable the counter.
Congratulations! You have created and implemented a new project on your own.
-----------------------
[pic]
[pic]
................
................
In order to avoid copyright disputes, this page is only a partial summary.
To fulfill the demand for quickly locating and searching documents.
It is intelligent file search solution for home and business.
Related searches
- flu shot timing 2019
- 4 0 sohc timing chain diagram
- trid loan estimate timing requirements
- facts assumptions constraints limitations army
- mdmp constraints and limitations
- constraints vs limitations mission analysis
- constraints vs restraints military planning
- army constraints and limitations
- army doctrine constraints and limitations
- military constraints and restraints
- military constraints and restraints examples
- timing belt measurement