ARM Memory Management Unit

ARM Memory Management Unit

Confidential

June 6, 2008 SW2G-SW4team Roy, Kang

Contents

Outline Memory access sequence Translation process Access permissions Domains Aborts CP15 registers Reference Q/A

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Outline ? Memory Management Unit?

Call to "MMU" (ARMX2X) Properties:

? Virtual to physical address mapping ? Memory access permissions ? Cachability and bufferability (C and B)

Composition (H/W)

? Translation Lookaside Buffer (TLB) ? Access control logic ? Translation table walking logic

? Translation table walk : the process of doing a full translation table lookup

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Outline ? Translation Lookaside Table?

Call to "TLB" Following information cached:

? Virtual to physical address mapping ? Access permissions

TLB does not contain an entry for the virtual address:

? Translation table walk H/W is invoked to retrieve the translation and access permission information from the translation table held in main memory.

Once the TLB entry for a memory access is obtained:

? Access control logic H/W is decided to access memory :

? Allow : Translation virtual address to physical address (Translation table walk H/W) ? Deny : Generate ,,Abort signal and send to ARM core

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Outline ? MMU and translation address

ARM core

I-cache D-cache

MMU

I-TLB

PA AP C B

D-TLB

PA AP C B

TLB TLB management

System Memory Instruction Data

Translation table

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Virtual address

Physical address

4

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