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ISLAMIC UNIVERSITY OF GAZA
COMPUTER ENGINEERING DEPARTMENT
Digital Logic Design LAB
QUIZ # 5
Name: Number:
Q1) Choose the correct answer :
1- The PRE and CLR (preset & clear) inputs of a master/slave JK flip-flop overide the JK inputs
1) Unconditionally.
2) Only after the clock input goes high.
3) Only after the clock input goes low.
4) Only if J = 0 and K = 0.
5) Only if J and K are not connected to anything.
2- Which of the following will correctly complete the JK flip-flop truth table shown below?
J K Qn | Qn+1
-------|-----
1) 0 2) 0 3) 0 4) 0 5) 1 0 0 0 | ?
1 1 0 0 1 0 1 1 | ?
1 0 1 1 0 1 0 1 | ?
0 0 1 0 1 1 1 1 | ?
3- Which of the following will correctly complete the D flip-flop truth table shown below?
D Qn | Qn+1
------|-----
1) 1 2) 1 3) 0 4) 0 5) 0 0 0 | ?
1 1 0 1 0 0 1 | ?
1 0 0 0 1 1 0 | ?
1 1 1 1 1 1 1 | ?
4- Which of the following will correctly complete the JK flip-flop truth table shown below?
J K Qn | Qn+1
-------|-----
1) 0 2) 0 3) 0 4) 0 5) 1 0 0 0 | ?
1 1 0 0 1 0 1 0 | ?
1 0 1 1 0 1 0 0 | ?
0 0 1 0 1 1 1 0 | ?
5- The timing diagram corresponds to:
|[pic]D latch |[pic] |
|[pic]positive edge triggered D flip flop | |
|[pic]negative edge triggered D flip flop | |
|[pic]none of them | |
6- The timing diagram corresponds to:
|[pic]D latch |[pic] |
|[pic]negative edge triggered flip flop | |
|[pic]positive edge triggered | |
|[pic]None of them | |
Q2) Design the 74x93 as a divided by 6 counter (to count 0,1,2,…..,5) without any SSI logic.
Connect Q0 to CP1
Connect CP0 to CLK
Connect (Q0,Q1,Q2,Q3) to Leds
Connect Q1 to MR1
Connect Q2 to MR2
Q3) Design the 74x160 as a divided by 5 and program the counter to have the sequence 2,3,4,5,2,3,….. .
Connect *R' to VCC
Connect (P0,P1,P2,P3) to (0,1,0,0)
Connect (Q0,Q1,Q2,Q3) to Leds
Connect CP to CLK
Connect (Q0,Q2) to NAND gate then to PE
Connect CEP,CET to switches
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[pic]
[pic]
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