ECE 4260/5260 Mixed Signal IC Design



ECE 4260/5260 Mixed Signal IC Design. Name _________________________

Answer all the questions. Show your work.

1 a) Explain with diagram the concept of bilinear transformation in discrete filter design.

b) A first order discrete time filter has a pole at 0.7 and a zero at -1. What is the transfer function if the DC gain =5.

c) Determine the 3db frequency using Z=ejω where ω ’ 2πf/fs where fs is the sampling frequency.

d) Using the bilinear transform, find a first order transfer function for a filter with a 3db frequency at fs/20 and a zero at -1 and dc gain of 1.

e) Determine the gain at (f/ fs) =0.2

II. a) Design a first order switched capacitor filter with a DC gain of 1 and a zero at -1,

3db frequency of 5 kHz when a clock frequency of 100 kHz is used. Assume a feed back capacitor to be 10pf. What is the gain at 25 kHz.

b) Show that for an opamp of gain A, the transfer function for the discrete-time integrator is given by

Vo (z)/ Vi(z) = -(C1/C2)[1/{z(1+C1/AC2)-1}]

III. a) An ideal 8 bit D/A converter has Vref=8V. Find the VLSB and the output voltage for input (00010001)

b) For a 3 bit D/A converter in which reference voltage is 4V with the following measured voltage values:

{ 0.009 : 0.507: 1.002: 1.501: 1.997: 2.495: 2.997: 3.491}

1) Find the offset and gain errors in terms of LSBs.

2) Find the INL (endpoint) and DNL errors (in units of LSBs)

3) Find the effective number of bits of absolute accuracy.

4) Find the effective number of bits of realative accuracy.

c) 1) Why do you get quantization noise in A/D converter. If Vref=4V, find the quantization noise for 12 bit A/D converter.

2) Define sampling uncertainty for A/D converter. What is the sampling uncertainty that can be tolerated for this 12 bit A/D operating with an input signal 10MHz.

IV. a) Give the architecture of a resistor string 4 bit D/A converter.

b) If the resistance of each resistor in a resistor string is 1kohm and the capacitance

at each node is 0.2pf, determine the time constant associated with RC network.

c) If the resistor tolerance is 1%, determine the number of bits that can be implemented

with INL of 0.5VLSB.

d) Give the architecture of multiple ring 6 bit D/A converter and explain its operation

for a digital input of 011101.

e) Give the architecture of R-2R based D/A converter. What are its advantages over simple resistor string converter.

f) Give the architecture of 4 bit charge redistribution D/A converter and explain its operation.

g) Give the schematics of a 3 bit D/A converter based on single resistor string and digital decoding. What is the tolerance needed for resistors for an INL of =0.5VLSB.

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