Www.secs.oakland.edu



Reference:

The main FPGA vendors in the world are

• Xilinx and their University Program

• Altera and their University Program

• Lattice and their University Program

• Actel

• QuickLogic

Other links

• A repository of many FPGA-FAQs, created from the comp.arch.fpga newsgroup.

• Lots of FPGA links on this ePanarama page. The page has a nasty popup though.

• The site, with its growing collection of projects.

• Some nice conference papers and articles from Andraka's site, plus other nice pages like Multiplication in FPGAs and Distributed Arithmetic.

• The FPGA Arcade site, with old popular games recreated in FPGAs.

• Build your own FPGA-based Logic Analyzer. Also from the same author, FreePCB freeware PCB layout software.

• The OpenCollector Database, a compilation of open hardware tools & designs.

• The Alien Slaughter II video game on an FPGA.

• MyHDL, an open source package that lets you use Python as an hardware description and verification language.

The latest fun is to put a custom CPU inside an FPGA.

Broad subject. Try these links:

• The FPGA CPU web site, and their XSOC CPU project.

• The CD16 soft CPU core, a synthesizable 16-bit CPU with development tools.

• A nice list of Open IPs / Open Cores.

• The Leon-2 SPARC core.

• The Nios-II CPU, with many projects and links from the Cornell University.

Music box

Here we teach our FPGA how to play sounds and music.

We start by generating a single tone. Then slowly more fun stuff like producing a police siren and play a tune.

You can listen to the sound produced by clicking on the speaker icon. For example here's the "police siren" [pic].

The hardware

A Pluto board, a speaker and a 1KΩ resistor are used for this project.

[pic]

A more formal representation looks like this:

[pic]

The oscillator provides a fixed frequency to the FPGA. The FPGA divides the fixed frequency to drive an IO. The IO is connected to a speaker through a 1KΩ resistor. By changing the IO frequency, the FPGA produces different sounds.

The HDL design

Simple beep [pic]

FPGAs can easily implement binary counters. Let's start with a 16-bits counter.

Starting from the 25MHz clock, we can simply "divide the clock" using the counter. A 16 bits counter counts from 0 to 65535 (65536 different values). The highest bit of the counter toggles at a frequency of 25000000/65536=381Hz.

The Verilog HDL code looks like this:

|module music(clk, speaker); |

|input clk; |

|output speaker; |

| |

|// Binary counter, 16-bits wide |

|reg [15:0] counter; |

|always @(posedge clk) counter ................
................

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