Introduction - University of California, Berkeley



Novel spread spectrum clock generator

Subramaniam Venkatraman, Matthew Leslie

Department of Electrical Engineering and Computer Science

University of California, Berkeley

Abstract

Spread spectrum clock generators are used to reduce the electromagnetic radiation from high-speed digital systems. We review the different methods used for spread spectrum clock generation and suggest a novel method which employs simpler circuitry and should yield greater reduction in electromagnetic interference.

I. INTRODUCTION

In modern integrated circuits, the greatest amount of electromagnetic radiation is created by the digital clock and signals derived from the clock. This is due to the nature of the clock signal, which is periodic with the highest frequency. Therefore, the energy concentrated at discrete frequencies (odd harmonics of this clock) is radiated off-chip. Electromagnetic Interferences (EMI) are subject to very strict regulations by US (FCC) and other international regulatory bodies (EN, etc.) [1]. These regulations aim at limiting the amount of EMI electronic devices emit, and at preventing interference between electronic devices, and possible damages to the human body.

While conventional EMI reduction methods (shielding, special coating, filtering components, etc.) are still common practice, the tightness of EMI regulations and the cost sensitivity of their impact have led to the development of alternative and less expensive solutions. By altering the spectral profile of the digital clock, the electromagnetic radiation at the clock frequencies can be significantly reduced. In this manner, the clock becomes composed of a greater range of frequencies of lesser amplitude, essentially the clock gets broadbanded and its energy gets spread over a larger bandwidth.

II. SPREAD SPECTRUM CLOCKS

There are two fundamentally different ways to spread the spectrum of a digital clock signal. In clock scrambling, or suppressed carrier clocking, the clock signal is directly mixed with a modulation signal, usually via an XOR gate. The more prevalent technique for clock signal conditioning involves modulating the clock frequency with a waveform to spread its energy. Both scrambling and clock frequency modulation (herein referred to as spread spectrum clocking) are described in detail below.

A. Suppressed Carrier Clocking

Clock scrambling involves mixing the clock signal with a modulating signal, which is much lower in frequency. The mixing is most readily accomplished in a digital fashion with an XOR gate [2], [3].

Figure 1 Time domain representation of suppressed carrier clocking scheme

In theory, suppressed carrier clocking does not introduce jitter. The attenuation of the fundamental is slightly greater than 10dB. However, there are important drawbacks to clock scrambling. When the modulating signal transitions, the transition on the suppressed clock is lost. This equates to lost computation time for a digital system. To obviate this problem, the scrambled signal can be demodulated at the various ends of the clock distribution network but this adds demodulation circuitry. Moreover, this implies that only the signal in the clock distribution network has suppressed EMI wheras the signal in the rest of the chip emits radiation at the clock frequencies and its harmonics.

This issue is not mentioned in the previous papers on the subject and poses a significant limitation. It would be interesting to investigate how much of the radiated emission from a chip is from the clock distribution network and how much from the rest of the chip. Yet another problem is the introduction of even clock harmonics into the spectrum which are not suppressed via scrambling.

B. Spread Spectrum Clock Generation

Spread spectrum clock generation (SSCG) is equivalent to adding jitter to the clock signal. By deviating the period of the clock signal from its fundamental by a small percentage and in a predictable fashion, the energy of the clock is spread to a larger bandwidth and the peak emission can be significantly attenuated [4]. The greater the deviation, and slower the frequency of the frequency modulating signal, the greater the attenuation can be. Obviously, the timing constraints of the digital systems being clocked will provide a practical limit to the amount of deviation that is tolerable.

[pic] (1)

At the architecture level, there are two fundamentally different ways of obtaining a spread spectrum clock signal. The first method is to directly modulate the clock’s frequency. Usually, a voltage controlled oscillator (VCO) has its input voltage controlled by a modulation waveform. The industry-wide accepted solution to EMI reduction is a PLL based SSCG. Lexmark markets several chips for the PCB designer, and also has a patented modulation profile which provides the optimal flatness to the spread spectrum clock [4]. A simpler technique is to use a triangular modulation profile [5] which reduces efficiency but simplifies the circuitry involved. Either of these techniques adds a number of peripheral blocks including a phase-frequency detector (PFD) with charge pump output and a VCO.

Another technique involves controlling the transitions of the digital clock. By controlling the temporal spacing of the edges, the clock’s frequency is indirectly controlled. This is the delay cell approach. [6] Employing significantly simpler circuitry, the delay cell approach uses single or multiple delay elements to control the speed of the clock signal. The delay cell approach gives an identical waveform to the PLL based technique except that it manages to achieve the same with reduced jitter.

Existing work on delay cell spread spectrum clocks uses many delay elements in series, each of which is programmable to one of two possible delay states [7]. As the clock signal progresses through the delay chain, each edge encounters a specified number of unit delays. The accumulation of these delays allows for the shaping of the clock signal into a spread spectrum clock signal.

III. IMPLEMENTATION

Conventional SSC, implemented using PLLs suffers from the drawback of reduction in maximum achievable EMI reduction due to the inherent jitter of the circuitry. This random jitter exists due to thermal noise, shot noise or flicker noise and poses critical limitation on performance of the conventional SSCG based on modulation of the period jitter of the PLL. PLL based systems show additional jitter as compared to a delay cell based system due a phenomenon called accumulation jitter.

Accumulation jitter is exhibited by autonomous systems, such as oscillators, that generate a stream of spontaneous output transitions. In the PLL, the oscillator and VCO exhibit accumulation jitter. Accumulation jitter is characterized by an undesired variation in the time since the previous output transition, thus the uncertainty of when a transition occurs accumulates with every transition [8].

Consider a delay cell array and a PLL based on the same delay element which shows a jitter of variance J. Each transition of the PLL is relative to the previous transition, and the variation in the length of each period is independent, so the variance in the time of each transition accumulates. Therefore variance of the jitter of the PLL after the signal has passed through k times is kJ. This effect holds until the feedback loop of the PLL takes effect (slow due to low pass filter of the PLL) and corrects for the jitter on the clock. The delay cell array on the other hand shows a variance of the jitter only equal to J. This reduction in variance of unintentional jitter is key to the delay cell array technique being able to achieve greater reduction in EMI using spread spectrum techniques.

It is essential for the delay cell array to be simple and low jitter for this implementation to succeed. Previous implementations have used a digital delay cell array with 200 elements. This large circuitry in itself is a large source of jitter. We plan to use a differential current starved inverter based delay cell which is a simple circuit to implement. The current flowing through the inverter can be controlled using a counter to create a triangular modulation waveform. The clock frequency is set to 100MHz to enable comparison with the work in [7] and the modulating frequency is set to 50 KHz.

|[pic][pic] |

|Figure 2 Simulation of EMI reduction by spread spectrum modulation of a 100MHz clock |

The previous implementation of a delay cell array based spread spectrum clock [7] shows an unnatural clock waveform with maximum power at the 4th harmonic. A clean square clock with 50% duty cycle should have very low power in the 4th harmonic so this clock is apparently not the natural clock used. Therefore, the reported results are hard to understand and replicate. We plan to implement a similar system with a delay cell array with low jitter and prove that the theory discussed will in fact give significant reduction of clock radiation. The expected EMI reduction of the 5th harmonic for this implementation was simulated using Matlab and is shown in Fig. 2.

IV. CONCLUSION

We plan to implement a low jitter spread spectrum clock generation technique using a delay cell array. This technique is expected to provide greater EMI reduction that PLL based techniques while using a simpler circuit. We plan to simulate this circuit using 0.35 micron technology and verify the reduction in EMI.

REFERENCES

1)Using spread spectrum technology to reduce emi and lower costs. Phaselink corporation application note EMI-01

2) D. Arnett, “Suppressed carrier digital clocks,” IEEE International Symposium on Electromagnetic Compatibility, 1999, pp. 816-821.

3) Suppressed Carrier Clock for Reduction of Electromagnetic Radiated Emission from High-speed Digital System; Dong Gun Kam, Jonghoon Kim and Joungho Kim Piljung Jun, 2003 IEEE Symposium on EMC

4) Spread Spectrum Clock Generation for the Reduction of Radiated Emissions, Keith B. Hardin John T. Fessler Donald R. Bush

5) A Spread-Spectrum Clock Generator With Triangular Modulation Hsiang-Hui Chang, Student Member, IEEE, I-Hui Hua, and Shen-Iuan Liu, IEEE journal of solid-state circuits, vol. 38, no. 4, april 2003

6) Dithered timing spread spectrum clock generation for reduction of electromagnetic radiated emission from high speed digital system, Jonghoon Kim, Joungho Kim, Piljung Jun

7) Spread spectrum clock generator with delay cell array to reduce the EMI from a high-speed digital system, Jonghoon Kim, Joungho Kim, Dong Gun Kam

8) Modeling Jitter in PLL-based Frequency Synthesizers Ken Kundert, The Designer’s Guide Community

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Suppressed carrier clock

Modulating signal

Input clock

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