University of California, Berkeley College of …

[Pages:11]University of California, Berkeley College of Engineering

Department of Electrical Engineering and Computer Science

EE240B Spring 2018 Eric Chang, Prof. Elad Alon

Virtuoso/ADEXL/BAG tutorial

This tutorial covers the following topics: 1. How to run Virtuoso on the instructional machines. 2. How to setup an ADEXL simulation and perform parametric sweeps. 3. (Optional) How to create new testbenches and run simulations in Python using BAG.

Using BAG will require you to know Python and Numpy/Scipy. For Python, this website has many helpful material depending on your previous programming experiences:

Numpy and Scipy both have very comprehensive documentation online. A great place to start is here: .

For learning/experimenting with Python, you can use the start_bag.sh script in the workspace directory. As a last tip, remember Google and StackOverflow are your best friends.

0. Account setup/remote login/Virtuoso basics If you need a class account for logging into instructional machines, you can request one at . You should log into the servers hpse-X.eecs.berkeley.edu, where X is a number between 9 to 15, both inclusive. For instructions on how to log into the servers remotely using X2Go, and also a basic Virtuoso tutorial, see the Software section on the course website.

1. Virtuoso setup To start Virtuoso, on the instructional machine, do the following:

1. Log into the instructional machine, and open a terminal.

2. Create the folder ee240b in your home directory, and cd into it: mkdir ee240b cd ee240b

3. In the terminal, type the following: git clone cd bag_workspace_gpdk045 git submodule init git submodule update

This will setup the Virtuoso workspace directory.

4. Type the following to start Virtuoso: source .bashrc virtuoso & This will start the Virtuoso program. Whenever you open a new terminal, just cd to your work directory and run the above two commands again to start working.

2. ADEXL setup Next, we will learn how to use ADEXL to run parameteric sweeps, using HW1 Problem 2 part A as an example.

1. Create a new library named ee240b_mos_char, and attach the technology library gpdk045 to it. 2. Create a new schematic in this library named tb_mos_ibias. Add voltage sources, ground, and transistor

nmos4_standard (which is the same as nmos4_svt) in the BAG_prim library, so you get the following schematic:

Set the voltage sources DC voltage values to vds, vgs, and 0, respectively. If you wish to use Python for automation later, it is important that you put transistor separately on the right, with connections only made through labels, as shown in the picture above. Wire labels can be created with the hotkey L. It is also important for you to name the transistor XDUT. You can change the transistor name by modifying the "Instance Name" field in the property window. Set the transistor properties l=45n, nf=20, and w=0.5u. After you're done, check-and-save the schematic by pressing the save button with a green check mark next to it. 3. In the schematic window, select Launch/ADE XL, in the pop-up window, select the "Create new View" radio button, then press OK. Press OK again when the "Create new ADE (G)XL view" dialog pop up. A new adexl tab should open.

4. In the left pane window "Data View", under "Tests", click on the grey line "Click to add test". An "ADE XL Test Editor" will pop up along with a "Choose Design" dialog. Click OK on the dialog window. Now, close the Test Editor, and then re-open it by clicking the new entry under "Tests".

5. Click Variables/Copy From Cellview to copy the vds and vgs variables. Set them to the nominal value of 500m.

6. Setup DC analysis with a linear sweep on vgs, with starting value of VAR("vgs_start") and stopping value of VAR("vgs_stop"). The analysis form should look like the screenshot below (Step size should be 0.05 instead). Then press OK.

7. Two new variables vgs_start and vgs_stop should be created. Set them to 0 and 1.2, respectively. Then, select Outputs/To Be Saved/Select on Design. The schematic window should appear. Select the negative terminal of the drain voltage source, an ellipse should appear circling that terminal. Press Escape when done. In the end, a new "VDS/MINUS" output should appear in the Test Editor Outputs window.

8. Select Outputs/Setup..., a new "Setting Outputs" dialog will show up. Fill in the form according to the instruction below. This will define a new output expression ibias which measures the DC current flowing into the negative terminal of VDS. When you're done, press OK, and check both the "Plot" and "Save" checkboxes of the ibias output.

9. Now you're finished setting up the DC simulation. The final Test Editor window should look like the following:

10. Close the test editor, and click on the adexl tab to bring back the ADEXL view. In the Data View window, expand the "Global Variables" section, and double click on the value field of vds. Click on the "..." button that shows up on the right. A "Parameterize" dialog will show up.

11. Click on "Delete Spec" to delete the existing setup. Then in the "Add Specification" combo box, select "From/To". In the form, set "Step Type" to Linear, and set the sweep from 0 to 1.2, with step size of 0.1, as shown in the screenshot below (the step size is wrong). When you're done, press OK.

12. You are done setting up the ADEXL state, click on the save button to save this state. In summary, you setup a DC analysis which sweeps vgs, and on top of that analysis you set a sweep on vds. We chose to sweep vgs on the inner loop because the inner sweep is usually faster, and we have more vgs points because transistor bias current is more sensitive to vgs. Once you're done, click on the green start button on towards upper-right to start the simulation. You should see a list of analysis running in the main ADEXL window, with a progress bar on the lower left.

13. When simulation finish, press the graph icon button to plot the results. You should see something like the following:

If you wish to do all simulations and data-processing manually, you can now select Trace/Export... to export these waveforms to a csv or a matlab .m file. You can then use whatever program you like to parse these data and complete the rest of the problem. To simulate other transistor types, just replace the transistor and repeat the procedure. Remember that when characterizing a PMOS, vgs and vds have to be negative.

However, if you want to use Python and BAG to automate simulation, continue reading.

14. First of all, we need to start BAG on Virtuoso. To do so, select the Virtuoso Log Window, and type the following command: load("start_bag.il")

Wait until you see the message "*INFO* BAG skill server started." In the Log Window, as shown below:

15. Now, we have a testbench schematic, and we want to be able to modify this schematic through Python so that we can characterize different transistors. To do so, we need to import our schematics into Python. Go back to the terminal you used to start Virtuoso, and type the following command: ./start_bag.sh

This will start an IPython interpreter. In the interpreter, type the following commands: import bag prj = bag.BagProject() prj.import_design_library("ee240b_mos_char") exit

You should see outputs similar to below:

16. Now, open the file BagModules/ee240b_mos_char/tb_mos_ibias.py in your workspace. This file is created by the import command run in step 15. If you modified the schematic, you need to re-run the import process to update BAG about the changes. Don't worry; if you already have code in this file, it will not be overridden.

In this file, fill in the get_params_info() method according to the following screenshot. This method returns a Python dictionary from schematic parameter names to a brief description string of what that parameter is.

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