Vita - Iowa State University



Vita

Revised March 2018

(courses through Sprig 2018)

PERSONAL DATA

Name: Randall L. Geiger

Work Address: Department of Electrical and Computer Engineering

2133 Coover Hall

Iowa State University

Ames, IA 50011, 515-294-7745

Home Address: 2374 220th Street

Ames, IA 50014, 515-292-4421

EDUCATION

Ph.D. EE Colorado State University 1977

M.S. Math University of Nebraska 1973

B.S. EE University of Nebraska 1972

ACADEMIC EXPERIENCE

7/95 - Present Professor

(Tunc and Lale Doluca Professor since 2012)

Electrical & Computer Engineering Department

Iowa State University, Ames, IA

2/09 – Present Honorary Chair Professor

National Taiwan University of Science and Technology

Taipei, Taiwan

1/91 - 7/95 Professor and Chairman

Electrical Engineering & Computer Engineering Department

Iowa State University, Ames, IA

3/86 - 12/90 Professor

Texas A&M University, College Station, Texas 77843

9/81 - 2/86 Associate Professor

Texas A&M University, College Station, Texas 77843

9/77 - 8/81 Assistant Professor

Texas A&M University, College Station, Texas 77843

INDUSTRIAL AND OTHER NON-ACADEMIC EXPERIENCE

4/82 - 12/85 President, World Instruments, Inc.

HONORS AND AWARDS

2017 Nillson-Boast Undergraduate Teaching Award (ISU EcPE Dept)

2010 Warren Boast Undergraduate Teaching Award (ISU EcPE Dept)

2009 Appointed Honorary Chair Professor at National Taiwan University of Science and Technology

2003 Warren Boast Undergraduate Teaching Award (ISU EcPE Dept)

2000 IEEE Circuits and Systems Society Golden Jubilee Medal

2000 IEEE Millenium Medal

1996 Meritorious Service Award, IEEE Circuits and Systems Society

1990 Elected IEEE Fellow for "Contributions to Discrete and Integrated Analog Circuit Design"

August 1982 Myril B. Reed Best Paper Award, Switched Resistor Filters,

Midwest Symposium on Circuits and Systems

1972 B.S. Degree "With Distinction," University of Nebraska

Member: Sigma Xi, Eta Kappa Nu, Sigma Tau, Pi Mu Epsilon

ACADEMIC AREAS OF SPECIALIZATION

Teaching at ISU

Course Title Times Taught Level

(through /Spring 2017 )

EE 201 Introductory Circuits 2 Sophomore

EE 202 Advanced Circuits 1 Junior

CprE 210 Intro. to Digital Techniques 1 Sophomore

EE 231/333 Electronic Circuits 12 Junior

EE 230 Electronic Circuits and Systems 2 Junior

EE 330 Integrated Electronics 18 Junior

EE 203 Electronic Circuits 1 Sophmore

EE 434 Analog Integrated Circuits I 8 Senior

EE 435 Analog Integrated Circuits II 16 Senior

EE 501 Analog VLSI Circuit Design 6 Graduate

EE 505 Data Converter Design 6 Graduate

EE 508 Monolithic Filter Design 10 Graduate

Teaching at TAMU

Course Title Times Taught Level

Electrical Circuit Theory 3 Sophomore

Electronics 17 Junior

Operational Amplifier Applications 4 Senior

Active Filter Analysis and Design 1 Senior

Microelectronic Circuit Design 11 Senior

Network Theory 1 Graduate

Active Network Synthesis 2 Graduate

Digital Signal Processing 1 Graduate

Analog Integrated Circuit Design 3 Graduate

Special Topics-Memory Design and Application 1 Graduate

Research Interests

Hardware Security and Cyber Security

Civil Infrastructure Condition Assessment

Integrated Circuit (VLSI) Design

Analog/Mixed Signal Verification, Semiconductor Reliability

Testing and BIST

Analog Circuits

Active Filters

Electronics

Digital Signal Processing

Biotechnology

GRANTS AND CONTRACTS

Active Projects

“Robust Reliable and Practical High Performance References in Advanced Technologies”

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $237,000

PI: R.L. Geiger (Joint effort with Degang Chen)

Duration: Mar 2017- Feb 2020

Status: Ongoing

“Collaborative Research: Design and Calibration Methodologies for Power-Efficient, High-Resolution Successive Approximation Register Based Analog-to-Digital Converters for High Frequency Applications”

Sponsor: National Science Foundation

Project Total: $227,498 (ISU part, TAMU funding level the same)

PI: R.L. Geiger (Joint effort with Degang Chen, TAMU is collaborator)

Duration: Aug 2015- July 2018

Status: Ongoing

“Performance and Reliability Enhancement of Embedded ADCs with Value-Added BIST”

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $222,096

PI: R.L. Geiger (Joint Effort with Degang Chen)

Duration: Feb 2013-January 2016

Status: Completed (Final Report Delayed)

Completed

“Research in Mixed-Signal Circuit Design”

Sponsor: Broadcom

Project Total: $25,000

PI: R.L. Geiger

Duration: Nov 2013- Oct 2014

Status: Completed

“Precision Tests Without Precision Instruments

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $240,000

PI: D. Chen (Joint Effort with Randy Geiger)

Duration: Aug 2013 - July 2016

Status: Completed

“Verification of Multi-state Vulnerable AMS Circuits”

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $360,000

PI: R. L. Geiger (joint effort with Degang Chen)

Duration: April 2012-December 2015

Status: Complete

“Research in Mixed-Signal Circuit Design”

Sponsor: Broadcom

Project Total: $30,000

PI: R.L. Geiger

Duration: March 2012-April 2013

Status: Completed

“Ultra-Fast and Accurate BIST and Calibration of Embedded ADCs”

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $120,000

PI: D. Chen (Joint Effort with Randy Geiger)

Duration: Dec 2013 - Nov 2015

Status: Completed

" Sensing Skin for Automated Condition Assessment of Wind Turbine Blades"

Sponsor: IAWIND

Project Total: $256,698

PI: Simon LaFlamme (RG is a Co-PI)

Duration: Aug 2012 – July 2015

Status: Completed

“Lifetime Electrothermal Stress Management for Multi-core Systems”

Sponsor: Semiconductor Research Corporation

Project Total: $366,339

PI: R.L. Geiger (joint effort between RG and DC)

Duration: Aug 2009 – July 2013

Status: Completed

“Lifetime Electrothermal Stress Management for Multi-core Systems”

Sponsor: Semiconductor Research Corporation (SRC)

Project Total: $105,000

PI: R.L. Geiger (joint effort between RG and DC)

Duration: Aug 2009 – July 2013

Status: Completed

“Robust Design of Low Power Small Area Data Converters in Low Voltage Digital Processes”

Sponsor: Semiconductor Research Corporation

Project Total: $150,000

PI: R.L. Geiger (joint effort between RG and DC)

Duration: Aug 2008 – Dec 2011

Status: Completed

“Envirostabilized References for Applications in SoC Compatible Processes”

Sponsor: National Science Foundation

Project Total: $300,000

PI: R.L. Geiger (joint effort between RG and DC)

Duration: Aug 2004 – July 2008

Status: Completed

“Strategies for Reducing Test Costs and Enhancing Performance in Data Converters: Custom Funding”: National Semiconductor

Sponsor: Semiconductor Research Corporation

PI: Degang Chen (joint effort between RG and DC)

Project Total: $70,000

Duration: Feb 2004 – Jan 2006

Status: Completed

“Testing and Design for Calibration/BIST of High-Speed High-Resolution Data Converters

Sponsor: Semiconductor Research Corporation: Custom Funding: Texas Instr.

PI: Degang Chen (Joint effort between RG and DC)

Project Total: $70,000

Duration: Feb 2004 – Jan 2006

Status: Completed

“Test-Based Digital Calibration of 14 bit 100 MHz Pipelined ADCs”

Sponsor: Semiconductor Research Corporation: Custom Funding: Conexant

Project Total: $37,500

PI: Degang Chen (joint effort between RG and DC)

Duration: Feb 2004 – De. 2004

“An integrated Data Acquisition System”

Sponsor: Honeywell

Project Total: $34,760

Duration: June 2003 – December 2003

“Pipelined Data Converter Design Strategies for Sub-100nm Processes”

Co-principal investigator: Degang Chen

Sponsor: Semiconductor Research Corporation

Project Total: $150,000

Duration: August 2001 – July 2004

“Pipelined Data Converter Design Strategies for Sub-100nm Processes”

Co-principal investigator: Degang Chen

Sponsor: National Science Foundation

Project Total: $150,000

Duration: August 2001 – July 2004

“Analog and Mixed-Signal VLSI Design Interaction”

Sponsor: Dallas Semiconductor

Project Total: $225,000

Duration: October 2000 – September 2004

“A New Strategy for Built-in Self-Test of Mixed-signal Integrated Circuits”

Co-principal investigator: Degang Chen

Sponsor: Semiconductor Research Corporation

Project Total: $300,000

Duration: September 2001 – August 2004

“High-Speed Communication Circuits”

Sponsor: Xilinx (division that was formerly RocketChips)

Duration: January 2002 – June 2003

Project Total: $180,000

“Identification and Traceability for the Pork Industry”

Sponsor: National Pork Board

Co-principal Investigators: Randall Geiger and Dermot Hayes

Co-Investigators: Robert Weber, Tim Stahly, Steven Hoff, David Topel, Jim McKean and Brian Mennecke

Project Total: $40,000

“Integrated Multi-Channel Data Acquisition system with Serialized Output”

Sponsor: Honeywell

Project Total: $29, 989

Duration: March 2002-June 2002

“Design of Programmable Linear Finite Gain Amplifiers in Standard CMOS Processes”

Sponsor: National Semiconductor

Project Total: $60,000

Duration: October 2001 – Sept. 2002

“Gigabit Silicon Integrated Circuits”

Co-Investigators: W. Black, R. Geiger, M. Hassoun, E. Lee, D. Bergland, S. Sapatnekar, S. Tridandapani, and R. Weber

Project Total: $1,000,000

Sponsor: RocketChips

Duration: January 1997 - December 2001

"Analog and Mixed Signal VLSI Design Center Membership"

Co-Investigators: R. L. Geiger, W. Black, G. Tuttle and R. Weber

Project Total: $640,000

Sponsor: Texas Instruments Inc.

Duration: January 2001 - December 2002

“RF-CMOS Circuits for Wireless Communications”

Sponsor: National Semiconductor

Project Total: $40,000

Duration: June 2000 – May 2001

“High-Speed Communication Circuits Laboratory”

Co-principal Investigators: W. Black, R. Geiger, M. Hassoun and E. Lee

Sponsor: Roy J. Carver Trust

Carver Request: $500,000

Duration: Funded: June 1998

“Adaptive Equalizers for Ethernet, SONET and 1394 Standards”

Amount: $40,000

Sponsor: Texas Instruments Inc.

Duration: October 1999-Sept. 2000

"Analog and Mixed Signal VLSI Design Center Membership"

Co-Investigators: R. L. Geiger, W. Black, M. Hassoun, E. Lee

Project Total: $1,050,000

Sponsor: Texas Instruments Inc.

Duration: January 1998 - December 2000

"Analog and Mixed Signal VLSI Design Center Membership"

Co-Investigators: R. L. Geiger, W. Black, M. Hassoun, E. Lee

Project Total: $400,000

Sponsor: Texas Instruments Inc.

Duration: January 1996 - December 1997

“Design of Fast Amplifiers for Data Converters”

Co-Investigator: Edward Lee

Project Total: $20,000

Sponsor: Raytheon

Duration: June 1998 - June 1999

“DAC Circuit Design Strategies”

Princiipal Investigator: R.L. Geiger

Project Total: $16,500

Spronsor: Texas Instruments Inc.

Duration: Sept. 1997 - December 1997

“Analog and Mixed-Signal Center Membership”,

Co-investigators: R. Geiger, M. Hassoun, E. Lee, and W. Black

Sponsor: Rockwell International

Project Total: $300,000

Duration: August 1996-December 1999

“Restructuring Basic Electronic Circuits Education around Integrated Circuit Technology”

Co-Investigators: R. Geiger, W. Black, E. Lee, M. Hassoun and C. Wright

Sponsor: National Science Foundation

Project total: $240,000 ($40,000 Center matching)

Duration: July 1997 - June 1999

“Magnetoresistive Memories”

Co-investigators: W. Black, R. Geiger, M. Hassoun, and E. Lee

Project Total: $100,000

Sponsor: Honeywell

Duration: May 1996 - April 1997

"Very Fast Settling Amplifiers for Low Gain Applications"

Principal Investigator: R. L. Geiger

Project Total: $20,000

Sponsor: Texas Instruments Inc.

Duration: September 1995 - August 1996

"Low Voltage, High Precision Video CMOS Circuits and Precision Switch Charge Injection Modelling"

Principal Investigator: R. L. Geiger

Sponsor: Texas Instruments Inc.

Project Total: $20,000

Duration: March 1994 - February 1995

"High Performance Precision Amplifier Design"

Principal Investigator: R. L. Geiger

Sponsor: Texas Instruments Inc.

Project Total: $15,000

Duration:

"High Performance Analog Circuit Design,"

Principal Investigator: R. L. Geiger

Sponsor: Texas Instruments

Project Total: $25,000

Duration: March 1991 - December 1991

“Design, Modelling and Testing of High-Speed Pipelined Flash ADC's"

Principal Investigator: R. L. Geiger

Sponsor: Texas Instruments

Project Total: $39,950

Duration: July 1990 - June 1991

"Characterization of Silicon Chrome and Op Amp Design"

Principal Investigator: R. L. Geiger

Co-Investigator: Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $40,000

Duration: January 1990 - December 1990

"Robust Analog Signal Processors - The Analog Counterpart to the Microprocessor"

Co-Investigator: R. L. Geiger, William G. Bliss

Sponsor: Texas Advanced Technology Program

Project Total: $224,000

Duration: January 1990 - December 1991

"Flash A/D Converter Characterization of Design"

Co-Investigator: Peter VanPeteghem

Sponsor: Texas Instruments

Project Total: $30,000

Duration: July 1989 - December 1989

"Development of CAD Tools for Estimating Parasitic Resistance and Capacitances in Multi-Diffused Semiconductors"

Co-Investigators: Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $42,000

Duration: May 1989 - March 1990

"Precision Circuit Trimming and Design"

Co-Investigators: Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $35,000

Duration: January 1989 - December 1989

"High Temperature Superconductor Characterization and Instrumentation"

Co-Investigator: Henry Taylor

Sponsor: University of Alabama-Huntsville (SDIO)

Project Total: $80,000

Duration: February 1989 - September 1989

"High Temperature Superconducting Staring Focal Plane Array Development"

Co-Investigator: Henry Taylor

Sponsor: University of Alabama-Huntsville

Project Total: $38,000

Duration: June 1988 - October 1988

"Flash A/D Converter Design"

Co-Investigator: Peter VanPeteghem

Sponsor: Texas Instruments

Project Total: $30,000

Duration: February 1988 - December 1988

"Characterization of Silicon-Chrome on MOS-Phase IV"

Co-Investigators: Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $35,000

Duration: January 1988 - December 1988

"Instrumentation of Medical and Dental Implants"

Co-Investigator: Peter VanPeteghem

Sponsor: Dr. Brad Dean - Baylor College of Dentistry

Project Total: $5,240

Duration: December 1987 - May 1988

"Digitally Controlled Analog Signal Processing"

Co-Investigators: Edgar Sánchez-Sinencio

Sponsor: NOSC

Project Total: $100,000

Duration: November 1987 - September 1988

"Hitachi Semiconductor Grant"

Sponsor: Hitachi

Project Total: $400

Duration: October 1985

"A Very High Speed Digitally Controlled Continuous-Time Signal Processor"

Co-Investigators: Edgar Sánchez-Sinencio

Sponsor: NOSC

Project Total: $115,000

Duration: October 1986 - September 1987

"Characterization of Silicon-Chrome on MOS-Phase III"

Co-Investigators: Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $35,000

Duration: January 1987 - December 1987

"GAP Voltage Sensor Characterization"

Sponsor: AGIE Corporation

Project Total: $95,000

Duration: June 1986 - May 1987

"A Very High Speed Digitally Controlled Continuous-Time Signal Processor"

Co-Investigators: Edgar Sánchez-Sinencio

Sponsor: NOSC

Project Total: $65,000

Duration: April 1986 - December 1986

"Development of Standard Integrated Circuit Laboratory Chips"

(Initial Investigators: P. Allen and W. B. Jones)

Sponsor: Westinghouse

Project Total: $55,000

Duration: 1983-1986

"Characterization of Silicon-Chrome on MOS-Phase II"

Co-Investigators: Jaime Ramírez-Angulo and Edgar Sánchez-Sinencio

Sponsor: Texas Instruments

Project Total: $30,756

Duration: January 1986 - December 1986

"Engineering Considerations for Implantable Hearing Aids"

Co-Investigator: Edgar Sánchez-Sinencio,

Sponsor: Baylor College of Medicine

Project Total: $45,864

Duration: September 1985 - August 1986

"Characterization of Silicon-Chrome on MOS"

Co-Investigators: Edgar Sánchez-Sinencio, and Jaime Ramírez-Angulo

Sponsor: Texas Instruments

Project Total: $55,550

Duration: January 1985 - December 1986

"Mycotoxin Management in Peanuts by Prevention of Contamination and Monitoring"

Sponsor: Peanut Collaborative Support Program,

Principal Investigator: Robert Pettit

Co-Investigators: T. Phillips, R. Tabor and R. L. Geiger

Duration: February 1983-January 1988

Project total $1,135,824

TECHNICAL PUBLICATIONS

Refereed Journals

2010-2019

T. Chen, X. Jin, R.L. Geiger, and D. Chen, "USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-test", IEEE Trans. On Circuits and Systems I, pp. 1-11, Dec 2017 (will have a Dec 2018 final date).

A. Downey, A. D'Alessandro2, F. Ubertini, S. Laflamme and R. Geige, “Biphasic DC measurement approach for enhanced measurement stability and multi-channel sampling of self-sensing multi-functional structural materials doped with carbon-based additives”, Smart Materials and Structures, pp. 1-12, May 2017

Q. Wang and R.L. Geiger, 'Temperature signatures for performance assessment of circuits with undesired equilibrium states”, Electronic Letters, pp. 1756-1758, Oct. 2015.

Laflamme, S., Saleem, H.S., Vasan, B.K., Geiger, R.L., Chen, D., Kessler, M., and Rajan, K., “Soft Elastomeric Capacitor Network for Strain Sensing over Large Surfaces”, IEEE/ASME Trans. On Mechatronics, Vol. 18, Issue 6, pp. 1647-1654, 2013.

Vasan, B., Sudani, S., Chen, D., and Geiger, R.L., “Low Distortion Sine Wave Generation Using a Novel Harmonic Cancellation Technique”, IEEE Trans. On Circuits and Systems, pp. 1122-1134, May 2013.

Laflamme,S., Kollipara,V., Saleem, H., and Geiger, R.L., “Large-Scale Flexible Membrane for Automatic Strain Monitoring of Transportation Infrastructure”, International Journal of Pavement Research and Technology, 5 (5) pp. 343-346, 2012.

2000-2009

J. He, S. Zhan, D. Chen, and R.L. Geiger, “Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators”, IEEE Transactions on Circuits and Systems I, Vol. 56, pp. 911-919, May 2009.

R.L. Geiger, “Regions 1-7: Circuits and electronics - the past, present, and future?”, IEEE Circuits and Systems Magazine, Vol. 9, Issue 1, pp. 35-37, 2009.

L.Jin, D. Chen, and R.L. Geiger, “Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal”, IEEE Transactions on Instrumentation and Measurement, Vol. 58, pp. 2679-2685, August 2009.

H. Xing, H. Jiang, D. Chen, and R.L. Geiger, “High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy”, IEEE Transactions on Instrumentation and Measurement, Vol. 58, pp. 2697-2705, August 2009.

L. Jin, H. Haggag, R.L. Geiger, and D. Chen, “Testing of Precision DAC Using Low-Resolution ADC With Wobbling”, IEEE Transactions on Instrumentation and Measurement, Vol. 57, pp. 940-946, May 2008.

 

Jin, L., Chen, D. and Geiger, R.L . “SEIR Linearity Testing of Precision A/D Converters in Nonstationary Environments With Center-Symmetric Interleaving”, IEEE Trans on Instr. And Measurement, pp. 1776-1785, Oct. 2007.

Jiang, H., Olleta, B., Chen, D.J., and Geiger, R. L. “Testing High-Resolution ADCs with Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACs”, IEEE Trans on Instr. and Measurement, pp 1753-1762, Oct. 2007.

He, C. Jin, L., Chen, D. and Geiger, R.L. , “Robust High-Gain Amplifier Design Using Dynamical Systems and Bifurcation Theory With Digital Postprocessing Techniques”, IEEE Trans. on Circuits and Systems I, pp. 964-973, May 2007.

Oletta, B., Jiang, H. Chen, D.J. and Geiger, R.L. “A Deterministic Dynamic Element Matching Approach for Testing High Resolution ADCs with Low Accuracy Excitations”, IEEE Trans on Instr. and Measurement Vol. 55, no. 3. pp 902-915. June 2006.

Y. Lin, D. Chen and R.L. Geiger “Yield Enhancement With Optimal Area Allocation

for Ratio-Critical Analog Circuits”, IEEE Trans. on Circuits and Systems I, Vol 53, pp. 534-553, March 2006.

Y L. Jin, K. Parthasarathy, T. Kuyel, D. Chen and R.L. Geiger "Accurate Testing of Analog-to-Digital Converters Using Low Linearity Signals with Stimulus Error Identification and Removal", IEEE Trans on Instr. and Measurement, Vol 54, pp. 1188-1199, June 2005.

Cong and R. L. Geiger, "A 1.5-v 14-bit 100-MS/s self-calibrated DAC," IEEE Journal of Solid State Circuits, pp. 2051-2060, vol. 38, no. 12, December 2003.

Y. Lin and R. Geiger, "Area Allocation Strategies for Enhancing Yield of R-2R Ladders," Journal of Analog Integrated Circuits and Signal Processing, Volume 37, Number 2, pp 123-132, November 2003.

K. Parthasarathy, T. Kuyel, D. Price, L. Jin, D. Chen, and R. Geiger, "BIST and Production Testing of ADCs Using Imprecise Stimulus," ACM Trans. Design Automation of Electronic Systems, Vol. 8, No. 4, pp. 522-545, Oct 2003.

Y. Tang and R. Geiger, “Phase detector for PLL-based high-speed data recovery”. IEE Electronic Letters, pp. 1417-1419, Nov. 2002.

M. Schlarmann and R. Geiger, “A Simple CMOS Transresistor”, IEE Electronic Letters pp. 1386-1387, Dec 2001.

M. F. Lan, A. K. Tammineedi, and R. L. Geiger, "Current Mirror Layout Strategies for Enhancing Matching Performance," Journal of Analog Integrated Circuits and Signal Processing, Vol. 28, pp. 9-26, July 2001.

Y. Cong and R. L. Geiger, "Switching Sequence Optimization for Gradient Error Compensation in Thermometer Decoded DAC Arrays", IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp. 585-595, July, 2000.

1990-1999

M. Hassoun, W. Black, E. Lee, R. Geiger and A. Hurst, “Field programmable logic gates using GMR devices”, IEEE Transactions on Magnetics, September 1997.

Kim, J. Y. and Geiger, R. L., “Characterization of Linear MOS Active Attenuator and Amplifier,” Electronics Letters, Vol. 31, pp. 511-513, March 1995.

Soenen, E. and Geiger, R. L., "An Architecture and an Algorithm for Fully Digital Correction of Monolithic Pipelined ADC's," IEEE Trans. on Circuits and Systems II, pp. 143-153, March 1995.

Yu, C. G. and Geiger, R. L., "An Automatic Offset Compensation Scheme with Ping-Pong Control for CMOS Operational Amplifiers," IEEE Journal of Solid State Circuits, Vol. 29, No. 5, pp. 601-610, May 1994.

Kim, C. G. and Geiger, R. L., "Nonideality Consideration for High-Precision Amplifiers - Analysis of Random Common-Mode Rejection Ratio," IEEE Trans. on Circuits and Systems I, Vol. CAS-40, pp. 1-12, January 1993.

Loh, K. H., Hiser, D. L., Adams, W. J. and Geiger, R. L., "A Versatile, Digitally Controlled Continuous-Time Filter Structure with Wide-Range and Fine-Resolution Programmability," IEEE Trans. on Circuits and Systems II, Vol. CAS-39, pp 265-276, May 1992.

1980-1989

Reed, R., and Geiger, R. L., "A Multiple-Input OTA Circuit for Neural Networks," IEEE Trans. on Circuits and Systems, Vol. CAS-36, pp. 767-770, May 1989.

Kim, T. G. and Geiger, R. L., "A Monolithic Programmable RF Filter," Electronics Letters, Vol. 24, No. 25, pp. 1569-1571, December 1988.

Sánchez-Sinencio, E., Geiger, R. L., and Nevárez-Lozano, H., "Generation of Continuous-Time Two Integrator Loop OTA filter Structures," IEEE Trans. on Circuits and Systems, Vol. 35, pp. 936-946, August 1988.

Ramírez-Angulo, J., and Geiger, R. L., "New Laser-Trimmed Film Resister Structures for Very High Stability Requirements," IEEE Trans. on Electron Devices, Vol. ED-35, No. 4, pp. 516-518, April 1988.

Ramírez-Angulo, J., Geiger, R. L., and Sánchez-Sinencio, E., "A Computer Aided Approach to the Characterization, Evaluation and Comparison of Laser-Trimmed Film Resistors," IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, pp. 1177-1189, December 1987.

Qin, S. C. and Geiger, R. L., "A ± 5V CMOS Analog Multiplier," IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, pp. 1143-1146, December 1987.

Xuexiang, C. Z., Sánchez-Sinencio, E., and Geiger, R. L., "Pole-Zero Pairing Strategies for Area and Sensitivity Reduction in SC Circuits," Proceedings IEE - G Electronic Circuits and Systems, Vol. 134, pp. 199-204, August 1987.

Nedungadi, A. and Geiger, R. L., "High-Frequency Voltage-Controlled Continuous-Time Lowpass Filter Using Linearized CMOS Integrators," Electronics Letters, Vol. 22, pp. 729-730, July 1986.

Ramírez-Angulo, J., Geiger, R. L., and Sánchez-Sinencio, E., "Component Quantization Effects on Continuous-Time Filters," IEEE Trans. on Circuits and Systems, Vol. CAS-33, pp. 651-659, June 1986.

Peterson, K. and Geiger, R. L., "Area-Bandwidth Tradeoffs for CMOS Current Mirrors," IEEE Trans. on Circuits and Systems, Vol. CAS-33, pp. 667-669, June 1986.

Geiger, R. L. and Sánchez-Sinencio, E., "OTA Circuit Design and Applications : A Tutorial," IEEE Circuits and Devices Magazine, Vol. 1, pp. 20-32, March 1985.

Sánchez-Sinencio, E., Geiger, R. L., and Silva-Martine , J., "Tradeoffs Between Passive Sensitivity, Output Voltage Swing and Total Capacitance in Biquadratic SC Filters," IEEE Trans. on Circuits and Systems, Vol. CAS-31, pp. 984-987, November 1984.

Sánchez-Sinencio, E., Silva-Martine , J., and Geiger, R. L., "Biquadratic SC Filters with Small GB Effects," IEEE Trans. on Circuits and Systems, Vol. CAS-31, pp. 876-884, October 1984.

Geiger, R. L. and Bailey, G., "Integrator Design for High Frequency Active Filter Applications," IEEE Trans. on Circuits and Systems, Vol. CAS-29, pp. 595-603, September 1982.

Grignoux, P. and Geiger, R. L., "Modeling of MOS Transistors with Nonrectangular Gate Geometrics," IEEE Trans. on Electron Devices, Vol. ED-29, pp. 1261-1269, August 1982.

Geiger, R. L., Allen, P. E., and Ngo, T., "Switched Resistor Filters-A Continuous Time Approach to Monolithic MOS Filter Design," IEEE Trans. on Circuits and Systems, Vol. CAS-29, pp. 306-315, May 1982.

Allen, P. E., Strader, N. and Geiger, R. L., "Graduate and Undergraduate Educational Methods for Microelectronics," IEEE Trans. Components, Hybrids and Manufacturing Technology, Vol. CHMT-5, pp. 105-111, March 1982.

Geiger, R. L. and Sánchez-Sinencio, E., "Operational Amplifier Gain-Bandwidth Product Effects on the Performance of Switched-Capacitor Networks," IEEE Trans. on Circuits and Systems, Vol. CAS-29, pp. 96-106, February 1982.

Geiger, R. L. and Budak, A., "Design of Active Filters Independent of First-and-Second-Order Operational Amplifier Time Constant Effects," IEEE Trans. on Circuits and Systems, Vol. CAS-28, pp. 749-757, August 1981.

Budak, A., Wullink, G. and Geiger, R. L., "Active Filters with Zero Transfer Function Sensitivity with Respect to the Time Constants of Operational Amplifiers," IEEE Trans. on Circuits and Systems, Vol. CAS-27, pp. 849-854, October 1980.

Geiger, R. L., "Parasitic Pole Approximation Techniques for Active Filter Design," IEEE Trans. on Circuits and Systems, Vol. CAS-27, pp. 793-799, September 1980.

Before 1980

Geiger, R. L. and Budak, A., "Active Filters with Zero Amplifier Sensitivity," IEEE Trans. on Circuits and Systems, Vol. CAS-26, pp. 277-288, April 1979.

Geiger, R. L. and Budak, A., "A Grounded Constant Current Source with Improved Bandwidth," IEEE Trans. on Circuits and Systems, Vol. CAS-25, pp. 235-236, April 1978.

Geiger, R. L., "Amplifiers with Maximum Bandwidth," IEEE Trans. on Circuits and Systems, Vol. CAS-24, pp. 510-512, September 1977.

Referred Conference Proceedings

2018

Q. Wang, R.L. Geiger, and D. Chen, “Transparent Side Channel Trigger Mechanism on Analog Circuits with PAAST Hardware Trojans”, IEEE International Symposium on Circuits and Systems, Florence, May 2018.

H. Meng, R. L. Geiger, and D. Chen, “A High Constancy Rail-to-Rail Level Shift Generator for Seir-Based BIST Circuit for ADCs”, IEEE International Symposium on Circuits and Systems, Florence, May 2018.

2017

X. Jin, T. Chen, M. Jain, A. Barman, D. Kramer, D. Garrity, R. Geiger, and D. Chen, “ An on-chip ADC BIST solution and the BIST enabled calibration scheme”, IEEE International Test Conference (ITC), Nov. 2017.

Q. Wang and R. Geiger, “Visible but transparent hardware Trojans in clock generation circuits”,

IEEE National Aerospace and Electronics Conference (NAECON), pp. 354 – 357, July 2017.

Wang, Q., Chen, D., and Geiger, R.L., “Technique for generating timing skew resistant time-interleaved signals”, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. Aug. 2017.

Q. Wang, D. Chen, and R.L. Geiger, “Transparent Side Channel Triggers for Transparent Hardware Trojans –A Growing Threat to Trust and Security”, GOMAC-Tech 2017, March 2017.

2016

Q. Wang, D. Chen, and R.L. Geiger, “Transparent Analog Hardware Trojans - A Threat to Trust and Security”, GOMAC-Tech 2016, March 2016.

2015

Cao, X, Wang, Q, Geiger, R.L., Chen, D., “A hardware Trojan embedded in the inverse Widlar reference generator”, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 81-84, August 2015.

Wang,Y-T, Liu,Z., Li, Y., Chen,D., and Geiger, R.L., “Analog Hardware Trojan Threats, Detection, and Mitigation” IEEE National Aeronautics and Electronics Conference (NAECON), pp. 1-4, June 1015.

Qianqian Wang,Q., Chen, D., and Geiger,R. L., “Hardware Trojans Embedded in the Dynamic Operation of Analog and Mixed-Signal Circuits”, IEEE National Aeronautics and Electronics Conference (NAECON), pp. 1-4, June 1015.

Zhang,X., Cai,C., Meng,H., Sudani, S., Geiger, R.L., and Chen, D.“A Calibration Technique for SAR Analog-to-Digital Converter Based on INL Testing with Quantization Bits and Redundant Bit, ” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3024-3027, May 2015.

Wang,Y-T, Zhao, C., Chen, D., and Geiger, R. L. “Direct Temperature to Digital Converters with Low Supply Sensitivity for Power/Thermal Management,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1066-1069, May 2015.

Wang,Q., Chen, D., and Geiger, R.L., “A Programmable Temperature Trigger Circuit,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1070-1073, May 2015.

Liu, Z., Cao, X., Geiger, R.L., and Chen, D., “ Feedback Loops and Trojan States: Hardware Threats to Trusted Analog Circuits”, GOMAC-Tech, St. Louis, March 2015.

2014

Qianqian Wang ; Geiger, R.L. ; Chen, D.J, “. Challenges and opportunities for determining presence of multiple equilibrium points with circuit simulators”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 406-409, May 2014.

Zhiqiang Liu ; You Li ; Yan Duan ; Geiger, R.L. ; Degang Chen, “Identification and break of positive feedback loops in Trojan States Vulnerable Circuits”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 289-292, May 2014.

Yen-Ting Wang ; Degang Chen ; Geiger, R.L., “A CMOS supply-insensitive with 13ppm/°C temperature coefficient current reference”, IEEE Midwest Symposium on Circuits and Systems, pp. 475-478, Aug. 2014.

Zhiqiang Liu ; You Li ; Geiger, R.L. ; Degang Chen, “Auto-identification of positive feedback loops in multi-state vulnerable circuits”, VLSI Test Symposium (VTS), pp. 1-5, April 2014.

Patra, S. and Geiger, R.L., “Comparison of MOSFET mismatch models with random physical and random model variables”, IEEE Midwest Symposium on Circuits and Systems, pp. 278-281, Aug. 2014.

Shiya Liu, Randall L. Geiger, Degang Chen, “A Graphical Method for Identifying Positive Feedback Loops Automatically in Self-Biasing Circuit for Determining the Uniqueness of Operating Points”, IEEE National Aeronautics and Electronics Conference (NAECON), pp. 1-4, July 1014

Yen-Ting Wang, Qianqian Wang, Degang Chen, and Randy Geiger, “Hardware Trojan State Detection for Analog Circuit and Systems”, IEEE National Aeronautics and Electronics Conference (NAECON), pp. 1-4, July 1014.

2013

Chen, C-W, Geiger, R.L., and Huang, S-C, “A low-power supply-insensitive temperature sensor in 90nm CMOS process”, IEEE Midwest Symposium on Circuits and Systems (MWSCAS), pp. 979-982, Aug. 2013.

Wang, Y-T, Chen, D., and Geiger, R.L., “Effectiveness of circuit-level continuation methods for Trojan State Elimination Verification”, IEEE Midwest Symposium on Circuits and Systems, pp. 1043-1046, Aug. 2013.

Wang, Y-T, Chen, D., and Geiger, R.L., “Practical Methods for Verifying Removal of Trojan Stable Operating Points”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2658-2661, May 2013.

Chen, Z., Wang, Y-T, Genzer, D., Chen, D., and Geiger, R.L., “A CMOS on-Chip Temperature Sensor with -0.21°C/ 0.17 °C Inaccuracy from -20 °C to 100 °C”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2621-2625, May 2013.

Sudani,S., Chen, D., and Geiger, R.L., “High Resolution ADC Spectral Test with Known Impure Source and Non-Coherent Sampling”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2674-2677, May 2013.

Patra, S., Chen, D., and Geiger, R.L., “Reliability Degradation with Electrical, Thermal and Thermal Gradient Stress in Interconnects”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1063-1066, May 2013.

2012

Geiger, R.L., “Analog DFT From a Test Perspective”, Invited Presentation, International Test Conference, November 2012.

Laflamme,S., Saleem, H., Vasan, B., Geiger,R.L., Chaudhary,S., Kollosche,M., Kofod, G., Rajan. K., “ Novel Flexible Membrane for Structural Health Monitoring of Wind Turbine Blades - Feasibility Study”, Proc. Materials Challenges in Alternative & Renewable Energy, Clearwater, FL. 2012.

Wang,Y., Zhao,C., Geiger,R.L., Chen,D.and Huang, S. “Performance verification of start-up circuits in reference generators”, IEEE Midwest Symposium on Circuits and Systems, pp. 518 - 521, Aug. 2012.

Patra,S., Chen, D., and Geiger, R.L., “Reliability Modeling of Metal Interconnects with Time-Dependent Electrical and Thermal Stress”, IEEE Midwest Symposium on Circuits and Systems, pp. 514-517, Aug. 2012.

Wang, Y-T, Zhao,C., Chen, D., Huang, S. and Geiger, R.L., “An Ultra-small On-Chip Sensor for Temperature and Thermal Gradient Measurements”, Proc. IEEE National Aerospace and Electronics Conference (NAECON), pp. 154-157, July 2012.

Vasan, B., Sudani, S., Chen, D., and Geiger, R.L., “Sinusoidal Signal Generation for Production Testing and BIST Applications”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2601-2604, May 2012.

Zhao, C., Chen, D., and Geiger, R.L., “A Compact Low-Power Supply-Insensitive CMOS Current Reference” , IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2825-2828, May 2012.

Duan, J., Chen, D., and Geiger, R.L., “A Low Cost Method for Testing Offset and Gain Error for ADC BIST”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2023-2026, May 2012.

2011

Sudani, S., Wu, M., and Chen, D., “A novel robust and accurate spectral testing method for non-coherent sampling”, IEEE International Test Conference (ITC), pp. 1-10, Sept. 2011.

Sheng-Huang Lee, S.H., Zhao, C., Wang, Y.T., Chen, D., and Geiger, R.L., “ Multi-threshold transistors cell for Low Voltage temperature sensing applications”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1– 4, Aug. 2011

Wang, T., Chen, D., and Geiger, R.L., “Multi-site on-chip current sensor for electromigration monitoring”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp.1– 4, Aug. 2011.

Zhao, C., He, J., Lee, S.H., Peterson, K., Geiger, R.L., and Chen, D., “Linear vt-based temperature sensors with low process sensitivity and improved power supply headroom”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2553 – 2556, May 2011.

Sudani, S., Chen, D., and Geiger, R.L., “A 2-FFT method for on-chip spectral testing without requiring coherency”, IEEE, Instrumentation and Measurement Technology Conference (I2MTC), pp. 1-6, 2011.

Vasan, B.K., Chen, D.J., and Geiger, R.L, “ADC integral non-linearity testing with low linearity monotonic signals”, IEEE Instrumentation and Measurement Technology Conference (I2MTC), pp. 1-5, 2011.

2010

Geiger, R.L., “Conventional Wisdom – Benefits and Consequences of Annealing Understanding of Engineering Principles”, Keynote Address, IEEE Asian Pacific Conference on Circuits and Systems (APCAS), Kuala Lumpur, Dec. 2010.

Duan, J., Chen, D., and Geiger, R., “Phase control of triangular stimulus generator for ADC BIST “

Proc. IEEE International Symposium on Circuits and Systems, pp. 1935-1938, May 2010.

Duan, J., Chen, D., and Geiger, R., ”Sensorless temperature measurement based on ADC Input noise measurement”, Proc. IEEE National Aerospace and Electronics Conference (NAECON), pp. 208-211, July 2010.

Vasan, B., Duan, J., Zhao, C., Chen, D., and Geiger, R.L., “Built In Self Test (BIST) for Production and In-field Testing of High Performance Analog and Mixed-Signal Systems”. Proc. Government Microelectronics Applications and Technology Conference (GOMACTech), pp. 407-410, Reno, March 2010.

He, J., Chen, D. and Geiger, R.L., “ Systematic characterization of subthreshold- mosfets-based voltage references for ultra low power low voltage applications”, IEEE Midwest Symposium on Circuits and Systems, pp. 280-283, August 2010.

Zhao, C., He, J., Lee, S., Peterson, K., Geiger, R., and Chen, D., “A linear differential output of threshold-based CMOS temperature sensor with enhanced signal range”, IEEE Midwest Symposium on Circuits and Systems, pp. 316-319, August 2010.

Lee, S., Peterson, K., Geiger, R., and Chen, D., “Highly linear very compact untrimmed on-chip temperature sensor with second and third order temperature compensation”, IEEE Midwest Symposium on Circuits and Systems, pp. 288-291, August 2010.

Vasan, B.K., Chen, D.J., and Geiger, R.L, “Linearity testing of Analog-to-Digital Converters using imprecise sinusoidal excitations”, Proc. National Aerospace and Electronics Conference (NAECON), pp. 334 - 337 , July 2010.

He, J., Chen, D., and Geiger, R., “This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three low-resolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to a plusmn0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs. Read More»

Detailed analyses in prediction of capacitive-mismatch-induced offset in dynamic comparators”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2390-2393, May 2010.

Vasan, B.K.; Geiger, R.L.; Chen, D.J., “Linearity testing of ADCs using low linearity stimulus and Kalman filtering”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3032-3035, May 2010.

2009

T. Duong, D.Chen, and R. L. Geiger, “Optimal area and impedance allocation for dual - string DACs”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2741-2744, May 2009.

5118369 searchabstract

J. Duan, D. Chen, and R.L. Geiger, “Cost effective signal generators for ADC BIST”, IEEE International Symposium on Circuits and Systems, pp. 13-16, May 2009.

Y.Wang, R.L. Geiger, and S.Huang, “Threshold-based voltage reference with pn- junction temperature compensation”, IEEE Midwest Symposium on Circuits and Systems, pp. 156-159, August 2009.

B. Vasan, J. Duan, C. Zhao, R.L. Geiger, and D. Chen, “Signal generators for cost effective BIST of ADCs”, European Conference on Circuit Theory and Design (ECCTD), pp. 113-116, August 2009.

Duan, J., Vasan, B., Zhao, C., Chen, D., and Geiger, R., “Stimulus generator for SEIR method based ADC BIST”, National Aeorspace Electronics Conference (NAECON), pp. 251-255, July 2009.

(Verify title and conference) J. Duan, B. Vasan, C. Zho, D. Chen, and R.L. Geiger, “Signal Generator for Low Overhead ADC BIST”, National Aeorspace Electronics Conference (NAECON), Dayton, July 2009.

2008

H. Xing, D. Chen, and R.L. Geiger, “On-chip at-speed linearity testing of high-resolution high-speed DACs using DDEM ADCs with dithering”, IEEE International Conference on Electro/Information Technology, pp. 117-122, May 2008.

J. Sloat and R.L. Geiger, “An inexpensive microelectronic environmental test chamber”, IEEE International Conference on Electro/Information Technology, pp. 168-170, May 2008.

Y. Gai, R.L. Geiger, and D. Chen, “Noise analysis in hold phase for switched-capacitor circuits”,

IEEE Midwest Symposium on Circuits and Systems, pp. 45-48, August 2008.

J. He, R.L. Geiger, and D. Chen, “A detailed analysis of nonideal effects on high precision bandgap voltage references”, IEEE Midwest Symposium on Circuits and Systems, pp. 382-385, August 2008.

J. He, S. Zhan, D. Chen, and R.L. Geiger, “A simple and accurate method to predict offset voltage in dynamic comparators”, IEEE International Symposium on Circuits and Systems, pp. 1934-1937, May 2008.

V. Katyal, R.L. Geiger, and D. Chen, “Adjustable hysteresis CMOS Schmitt triggers”,

IEEE International Symposium on Circuits and Systems, pp. 1938-1941, May 2008.

H. Xing, D. Chen, R.L. Geiger, and L. Jin, “System identification -based reduced-code testing for pipeline ADCs’ linearity test”, IEEE International Symposium on Circuits and Systems, pp. 2402-2405, May 2008.

2007

L Jin, D. Chen, and R.L. Geiger,. “Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal”, IEEE VLSI Test Symposium, pp. 303-310, May 2007

H. Xing, H. Jiang, D. Chen, and R.L. Geiger, “A fully digital-compatible BIST strategy for ADC linearity testing”, IEEE International Test Conference, pp. 1-10, October 2007.

 Jin, L. Chen, D. and Geiger, R.L., “Code-Density Test of Analog-to-Digital Converters Using Single Low-Linearity Stimulus Signal”, IEEE VLSI Test Symposium, pp. 303-310, May 2007.

Fei, H. and Geiger, R.L., “Linear Current Division Principles”, IEEE Int. Symp. On Cirucits and Systems, pp. 2830-2833, May 2007.

H. Jiang, D. Chan, and R. L. Geiger, “Deterministic DEM DAC Performance Analysis”

IEEE International Symposium on Circuits and Systems, pp. 3860 – 3863, May 2007

2006

V. Katyal, D. Chen, and R.L. Geiger, “A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs”, IEEE Asian Pacific Conference on Circuits and Systems (APCAS), pp. 5-8, Dec. 2006.

H. Fei and R.L. Geiger, “Aggressive Area Scaling in Passive Transresistance Networks”, IEEE Midwest Symposium on Circuits and Systems, paper 3355, August 2006, San Juan, Puerto Rico.

L. Jin, D. Chen, and R. L. Geiger, "Testing of Precision DACs Using Low-Resolution ADCs with Dithering Testing of Precision DACs Using Low-Resolution ADCs with Dithering", IEEE International Test Conference, Paper 13.1, October 2006.

L. Jin, D. Chen, and R. L. Geiger, "Linearity Test of A/D Converters Using Kalman Filtering", IEEE International Test Conference, Paper 28.3, October 2006.

L. Jin, H. Xing, D. Chen, and R.L. Geiger, " A Self-Calibrated Bandgap Voltage Reference with 0.5 ppm/C Temperature Coefficients", IEEE International Symposium on Circuits and Systems, pp. 2853-2856, Kos, Greece, May 2006.

X. Xing, D. Chen and R. L. Geiger, "Linearity Test for High Resolution DACs Using Low-Accuracy DDEM Flash ADCs", IEEE International Symposium on Circuits and Systems, pp. 2469-2472, Kos, Greece, May 2006.

X. Xing, J. Jin, D. Chen, and R.L. Geiger, "Charaterization of a Current-Mode Bandgap Circuit Structure for High Precision Reference Applications", IEEE International Symposium on Circuits and Systems, pp. 569-572, Kos, Greece, May 2006.

X. Dai, D. Chen and R. L. Geiger, "Explicit Charaterization of Bandgap References",  IEEE International Symposium on Circuits and Systems, pp. 573-576, Kos, Greece, May 2006.

Y. Lin and R.L. Geiger, "Unit Resistor Characterization for Matching-Critical Circuit Design",  IEEE International Symposium on Circuits and Systems, pp. 2458-2861, Kos, Greece, May 2006

Chao, S.  and Geiger, R. L. "Dynamic Calibration of Current-Steering DACs", IEEE International Symposium on Circuits and Systems, pp. 117-120, Kos, Greece, May 2006.

 

K. Wada and R. L. Geiger, "Minimization of Total Area in Integrated Active RC Filters",  IEEE International Symposium on Circuits and Systems, pp. 433-436, Kos, Greece, May 2006.

2005

Yu Lin, Katyal, V and Geiger, R.L., “New over-range protection scheme in pipelined data converters”

IEEE Midwest Symposium on Circuits and Systems, pp. 283-286, Cincinnati, Ohio August 2005.

Amourah, M.M.; Malik, S.Q.; Geiger, R.L.; “A new design technique for rail-to-rail amplifiers”,

IEEE Midwest Symposium on Circuits and Systems, pp. 263-266, Cincinnati, Ohio August 2005.

Malik, S.Q.and Geiger, R.L., “Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs”, IEEE Midwest Symposium on Circuits and Systems, pp. 1015-1018, Cincinnati, Ohio August 2005.

Katyal, V., Yu Lin, Geiger, R.L. and Chen, D.J., “Statistical modeling of over-range protection requirement for a switched capacitor inter-stage gain amplifier”, IEEE Midwest Symposium on Circuits and Systems, pp. 1819-1822, Cincinnati, Ohio August 2005.

Soufi, B.; Malik, S.Q.; Geiger, R.L “A capacitor sharing technique for RSD cyclic ADC”, IEEE Midwest Symposium on Circuits and Systems, pp. 859-862, Cincinnati, Ohio August 2005.

Le Jin, Parthasarathy, K., Kuyel, T., Geiger, R and Degang Chen; “High-performance adc linearity test using low-precision signals in non-stationary environments”, IEEE International Test Conference, pp. 1182 – 1191, Nov 2005.

Parthasarathy, K.m Kuyel, T., Zhongjun Yu, Degang Chen and Geiger, R.L., ”A 16-bit resistor string dac with full-calibration at final test”, IEEE International Test Conference, pp. 66 –75, Nov 2005.

Chao Su, Xin Dai and Geiger, R.L., “A novel dynamic calibration approach for current-steering DACS”,

Proceedings of the IEEE International Workshop on VLSI Design and Video Technology, pp. 40- 43, Shanghai, May 2005.

V. Katyal, Y. Lin, and R.L. Geiger, “Power Dependence of Feedback Amplifiers on Op Amp Architecture”, IEEE International Symposium on Circuits and Systems, pp. 1618-1621, Kobe Japan, May 2005.

Y. Lin, V. Katyal, M. Schlarmann, and R.L. Geiger, “ kT/C Constrained Optimization of Power in Pipelined ADCs”, IEEE International Symposium on Circuits and Systems, pp. 1968-1971, Kobe Japan, May 2005.

X. Dai, D. Chen, and R.L. Geiger, “ A Cost-Effective Histogram Test-Based Algorithm for Digital Calibration of High-Precision Pipelined ADCs”, IEEE International Symposium on Circuits and Systems, pp. 4831- 4834, Kobe Japan, May 2005.

X. Dai, C. He, H. Xing, D. Chen, and R.L. Geiger, “ An n-th Order Central Symmetrical Layout Pattern for Nonlinear Gradient Cancellation”, IEEE International Symposium on Circuits and Systems, pp. 4835-4838. Kobe Japan, May 2005 .

H. Jiang, D. Chen, and R.L. Geiger, “ Dither Incorporated Deterministic Dynamic Element Matching for High Resolution ADC Test Using Extremely Low Resolution DACs, ” IEEE International Symposium on Circuits and Systems, pp. 4285-4288, Kobe Japan, May 2005.

L. Jin, D. Chen, and R.L. Geiger, “ A Digital Self-Calibration Algorithm for ADCs Based on Histogram Test Using Low-Linearity Input Signals”, IEEE International Symposium on Circuits and Systems, pp. 1378-1381, Kobe Japan, May 2005.

H. Jiang, B. Olleta, D. Chen, and R.L. Geiger, “ A Segmented Thermometer Coded DAC with Deterministic Dynamic Element Matching for High Resolution ADC Test”, IEEE International Symposium on Circuits and Systems, pp. 784-7887, Kobe Japan, May 2005.

W. Liu, H. Xing, L. Jin, R.L. Geiger, and D. Chen, “ A Test Strategy for Time-to-Digital Converters Using Dynamic Element Matching and Dithering”, pp. 3809-3812, IEEE International Symposium on Circuits and Systems, Kobe Japan, May 2005.

D. Chen, Z. Yu, and R.L. Geiger, “An Adaptive Truly Background Calibration Method for High Speed Pipeline ADC Design”, IEEE International Symposium on Circuits and Systems, pp. 6190-6193, Kobe Japan, May 2005.

Z. Yu, D. Chen, R.L. Geiger, and Y. Papantonopoulo, “Pipelined ADC Linearity Testing with Dramatically Reduced Capture Time ”, IEEE International Symposium on Circuits and Systems, pp. 792-795, Kobe Japan, May 2005.

H. Xing, D. Chen, and R.L. Geiger, ”A Two-Step DDEM ADC for Accurate and Cost Effective DAC Testing”, IEEE International Symposium on Circuits and Systems, pp. 4289-4292, Kobe Japan, May 2005.

S. Thoka and R.L. Geiger, “Fast-Switching Adaptive Bandwidth Frequency Synthesizer using a Loop Filter with Switched Zero-Resistor Array”, IEEE International Symposium on Circuits and Systems, pp. 5373-5376, Kobe Japan, May 2005.

2004

H. Jiang, B. Olleta, D. Chen and R. L. Geiger, "Testing High Resolution ADCs with Low Resolution/ Accuracy Deterministic Dynamic Element Matched DACs" Proceedings of the 2004 International Test Conference, pp. 1379-1388, Oct 2004.

Z. Yu, D. Chen, R.L. Geiger, "A Computationally Efficient Method for Accurate Spectral Testing without Requiring Coherent Sampling", Proceedings of the 2004 International Test Conference, pp. 1398-1407, Oct 2004.

H. Jiang, H. Fei, D. Chen and R.L. Geiger, “A Background Digital Self-calibration Scheme

for Pipelined ADCs Based on Transfer Curve Estimation”, IEEE International Symposium on Circuits and Systems, vol 1, pp 61-64, Vancouver, Canada, May 2004.

C. He, K. Yap, D. Chen, R.L. Geiger, “Nth Order Circular Symmetry Pattern and Hexagonal Tesselation: Two New Layout Techniques Canceling Nonlinear Gradient”, IEEE International Symposium on Circuits and Systems, vol 1, pp 237-240, Vancouver, Canada, May 2004.

Z. Yu, D. Chen, and R.L. Geiger,”The SRE/SRM Approach for Spectral Testing of AMS Circuits”,

IEEE International Symposium on Circuits and Systems, vol 1, pp 249-252, Vancouver, Canada, May 2004.

C. He, L. Jin, D. Chen, R.L. Geiger,” Robust Design of High Gain Amplifiers Using Dynamical Systems and Bifurcation Theory”, IEEE International Symposium on Circuits and Systems, vol 1, pp 481-484, Vancouver, Canada, May 2004.

Z. Yu, D. Chen, R.L. Geiger,”Accurate Testing of ADC’s Spectral Performance Using Imprecise

Sinusoidal Excitations”,IEEE International Symposium on Circuits and Systems, vol 1, pp 645-648, Vancouver, Canada, May 2004.

H. Fei, R. L. Geiger and D. Chen, ”Optimum Area Allocation for Resistors and Capacitors in Continuous-Time Monolithic Filters”, IEEE International Symposium on Circuits and Systems, vol 1, pp 865-868, Vancouver, Canada, May 2004.

B. Olleta, H. Jiang, D. Chen and R.L.Geiger,”Testing High Resolution ADCs Using Deterministic Dynamic Element Matching”, IEEE International Symposium on Circuits and Systems, vol 1, pp 920-923, Vancouver, Canada, May 2004.

H. Jiang, B. Olleta, D. Chen, R.L. Geiger,”Parameter Optimization of Deterministic Dynamic Element Matching DACs for Accurate and Cost-effective ADC Testing”,IEEE International Symposium on Circuits and Systems, vol 1, pp 924-927, Vancouver, Canada, May 2004.

L. Jin, C. He, D. Chen, and R.L. Geiger,” An SOC Compatible Linearity Test Approach for Precision ADCs using Easy-to-generate Sinusoidal Stimuli”,IEEE International Symposium on Circuits and Systems, vol 1, pp 928-931, Vancouver, Canada, May 2004.

L. Jin, C. He, D. Chen, and R.L. Geiger,”Fast Implementation of a Linearity Test Approach for Higher Resolution ADCs using Nonlinear Ramp Signals”, IEEE International Symposium on Circuits and Systems, vol 1, pp 932-935, Vancouver, Canada, May 2004.

2003

L. Jin, K. Parthasarathy, T. Kuyel, D. Chen and R. L. Geiger, "Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs," Proceedings of the 2003 International Test Conference, pp. 218-227, Oct 2003.

M. M. Amourah, H. Bilhan, F. Ying, L. Fang, G. Xu, R. Chandrasekaran, and R. L. Geiger, “A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifier,"  IEEE Custom Integrated Circuits Conference, pp. 421-424, Sep. 2003.

Y. Tang and R. L. Geiger, "High-frequency 750mV operational amplifier standard bulk CMOS process,"  IEEE Custom Integrated Circuits Conference, pp. 689-692, Sep. 2003.

Chengming He, Degang Chen, Randall Geiger, "A Low-Voltage Compatible Two-Stage Amplifier with >120dB Gain in Standard Digital CMOS", Proceeding of the 2003 International Symposium on Circuits and Systems, vol 1, pp 353-356, Bangkok, Thailand, May 25-28, 2003.

B. Olleta, L. Juffer, Degang Chen and R. L. Geiger, "A deterministic dynamic element matching approach to ADC testing," Proceedings of the 2003 International Symposium on Circuits and Systems, Bangkok, Thailand, May 25-28,2003.

K. Parthasarathy, L. Jin, T. Kuyel, D. Price, D. Chen, and R. Geiger, "Experimental evaluation and validation of a bist algorithm for characterization of A/D converter performance,"  Proceedings of the 2003 International Symposium on Circuits and Systems, Volume 5 , pp. 537 -540, Bangkok, Thailand, May 25-28, 2003.

C. Su, S. Thoka, K.C. Tiew, R.L. Geiger, "A 40 GHz Modified-Colpitts Voltage Controlled Oscillator with Increased Tuning Range", Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, vol. 1, pp 717-720, Bangkok, Thailand, May 2003.

K. C. Tiew, J. Cusey, and R. L. Geiger, "Inflection point correction for voltage references," Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, vol. 1, pp 649-652, Bangkok, Thailand, May 2003.

Z. Yu, D. Chen, and R. Geiger, "1-D and 2-D switching strategies achieving near optimal INL for thermometer-coded current steering DACs", Proceedings of the IEEE International Syposium on Circuits and Systems, 2003

Y. Cong and R. L. Geiger,"A 1.5 V 14 b 100 MS/s self-calibrated DAC," IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 128-129, Feb. 2003.

2002

S. Gondi, R. Geiger J. Liu, J. Bareither, S. Sterrantino, and E. Pace, “ A 2V Low-Power CMOS 125Mbaud Repeater Architecture for UTP5 Cables”, European Solid State Circuits Conference (ESSRIC), pp. 571-574, Sept. 2002.

K. C. Tiew and R. L. Geiger, "An Alternative Method for Characterizing Capacitor Matching,", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 247-250,Tulsa, Aug. 2002

C. He, L. Jin, H. Jiang, D. Chen and R. Geiger, “Equivalent Gain Analysis for Nonlinear Operational Amplifiers", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 101-104,Tulsa, Aug. 2002.

Y. Tang and R. Geiger, "A Highly Linear CMOS Amplifier for Variable Gain Amplifier Applications", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 109-112, Tulsa, Aug. 2002..

C. Su, S. Thoka, K.C. Tiew and R. Geiger, "Design of a Colpitts Oscillator Using Mico-Strip-Line Inductor Compensated for Low Q", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 120-123, Tulsa, Aug. 2002.

Y. Lin, S. Malik and R. Geiger, "Yield Enhanced Layout Strategies for Ratio Critical Analog Circuits", IEEE Midwest Symposium on Circuits and Systems, Vol. I, pp. 332-335, Tulsa, Aug. 2002.

H. Jiang, C. He, D. Chen and R. Geiger, "Optimal Loop Paramater Design of Charge Pump PLLs for Jitter Transfer Characteristic Optimization", IEEE Midwest Symposium on Circuits and Systems, Vol. I, pp. 344-347, Tulsa, Aug. 2002.

M. Schlarmann and R. Geiger, "Use of the Newton-Raphson Iteration to Eliminate Low Frequency Dipoles", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 535-538, Tulsa, Aug. 2002.

A. Hashim, M. Amourah and R. Geiger, "A High Gain Amplifier Using a Cascadeing Architecture", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 539-542, Tulsa, Aug. 2002.

M. Amourah, S. Malik and R. Geiger, "An MSB-First Monotonic Switched Capacitor Serial DAC", IEEE Midwest Symposium on Circuits and Systems, Vol I, pp. 571-574, Tulsa, Aug. 2002.

L. Jin, K. Parthasarathy, T. Kuyel, D. Chen and R. Geiger, "A Blind Identification Algorithm for Calibration of Pipelined ADC", IEEE Midwest Symposium on Circuits and Systems, Vol. II, pp. 278-281, Tulsa, Aug. 2002.

K. Parthasarathy, L. Jin, T. Kuyel, D. Chen and R. Geiger, "A Historgram-Based AM-BIST Algorithm for ADC Characterization Using Imprecise Stimulus", IEEE Midwest Symposium on Circuits and Systems, Vol II, pp. 274-277, Tulsa, Aug. 2002.

L. Boylston, K. Brown and R. Geiger, "Enhancing Performance of Interpolating Resistor String DACs", IEEE Midwest Symposium on Circuits and Systems, Vol. II, pp. 541-544, Tulsa, Aug. 2002.

B. Olleta, D. chen and R. Geiger, "A Dynamic Element Matching Approach to ADC Testing:", IEEE Midwest Symposium on Circuits and Systems, Vol II, pp. 549-552, Tulsa, Aug. 2002.

H. Fei and R. Geiger, "Low-Distortion Continuous-Time Integrated Filters for Low Frequency Applications", IEEE Midwest Symposium on Circuits and Systems, Vol III, pp. 356-359, Tulsa, Aug. 2002.

S. Thoka, C. Su and R. Geiger, "Technological Limitations of Monolithic High-Frequency Oscillators in MOS and Bipolar Processes", IEEE Midwest Symposium on Circuits and Systems, Vol III, pp. 556-559, Tulsa, Aug. 2002.

J. Yan and R.L. Geiger, “A High Gain CMOS Operational Amplifier With Negative Conductance Gain Enhancement”, IEEE Custom Integrated Circuits Conference, pp. 337-340, May 2002.

M. Amourah and R.Geiger, “All Digital Transistors High Gain Operational Amplifier Using Positive Feedback Techniques” IEEE International Symposium on Circuits and Systems, pp. I 701-704, Phoenix, May 2002.

A.E. Hashim and R. Geiger “An Amplifier Structure for High-Gain and Fast Settling Applications” ” IEEE International Symposium on Circuits and Systems, pp. II 823-826, Phoenix, May 2002.

Y. Lin and R. Geiger, “Resistor Layout for Enhancing Yield in R-2R DACs”, ” IEEE International Symposium on Circuits and Systems, pp. V 97-100, Phoenix, May 2002.

Y. Cong and R. Geiger, “Formulation of INL and DNL Yield Estimation in Current-Steering D/A Converters”, IEEE International Symposium on Circuits and Systems, pp. III 149-152, Phoenix, May 2002.

K.C. Tiew, J. Cusey and R. Geiger, “A Curvature Compensation Technique for Bandgap Voltage References Using Adaptive Reference Temperature “, IEEE International Symposium on Circuits and Systems, pp. IV 265-268, Phoenix, May 2002.

Y. Tang and R. Geiger, “Bit Error Rate Analysis of the Data Recovery System using Jitter Models”, IEEE International Symposium on Circuits and Systems, pp. III 185-188 Phoenix, May 2002.

Y. Tang and R. Geiger, “Analysis of the nonlinearity in feedback amplifiers”, IEEE International Symposium on Circuits and Systems, , pp. II 141-144, Phoenix, May 2002.

Y. Tang and R. Geiger, “A 0.6V Ultra-low voltage Operational Amplifier”, IEEE International Symposium on Circuits and Systems, pp. III 611-614Phoenix, May 2002.

M. Schlarmann, S. Malik and R. Geiger, “Positive Feedback Gain Enhancement Techniques for Amplifier Design”, IEEE International Symposium on Circuits and Systems, pp. II 37-40, Phoenix, May 2002.

L. Jin, K. Parthasarathy, D. Chen, and R. Geiger, “A Blind Identification Approach to Digital Calibration of Analog-to-Digital Converters for Built-In Self-Test”, IEEE International Symposium on Circuits and Systems, , pp. II 788-781, Phoenix, May 2002.

K. Parthasarathy, L. Jin, D. Chen, and R. Geiger, “A Modified Histogram Approach for Accurate Self-Characterization of Analog to Digital Converters”, IEEE International Symposium on Circuits and Systems, pp. II 376-379, Phoenix, May 2002.

2001

H. Chen and R.L. Geiger, “Transfer Characterization Of CMOS Ring Voltage Controlled Oscillators”, Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 66-70, Dayton OH, Aug. 2001.

M.E. Schlarmann and R. L. Geiger, “Technique to Eliminate Slow-Settling Components that Appear Due to Dipoles”, Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 74-77, Dayton OH, Aug. 2001.

Y. Lin and R.L. Geiger, “Resistor Layout Techniques for Enhancing Yield in Ratio-Critical Monolithic Applications”, ”, Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 259-262, Dayton OH, Aug. 2001.

K.L. Parthasarathy and R.L. Geiger, “Accurate Self Characterization And Correction Of A/D Converter Performance”, Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 276-279, Dayton OH, Aug. 2001.

J. Yan, K.C. Tiew, and R.L. Geiger, “Open Loop Pole Location Bounds for Partial Positive Feedback Gain Enhancement Operational Amplifiers ”, Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 425-428, Dayton OH, Aug. 2001.

M. Schlarmann, S. Malik and R. Geiger, “A Low Temperature Sensitivity Switched Capacitor Current Reference”, European Conference on Circuit Theory and Design, pp 269-272, Espoo Finland, August 2001.

M. Amourah, and R. L. Geiger, "A High Gain Strategy with Positive-Feedback Gain Enhancement Technique ," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 631-634, Sydney, May 2001.

M. F. Lan and R. L. Geiger, "Modeling of Random Channel Parameter Variations in MOS Transistors," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 85-88, Sydney, May 2001.

M. F. Lan and R. L. Geiger, "MOSGRAD - A Tool for Simulating the Effects of Systematic and Random Channel Parameter Variation," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 89-92, Sydney, May 2001.

M. E. Schlarmann and R. L. Geiger, "Prototype Implementation of a WWW-Based Analog Circuit Design Tool," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 97-100, Sydney, May 2001.

Y. Tang and R. L. Geiger, " A 2.5Gbit/s CMOS PLL for data/clock recovery without frequency divider," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 256-259, Sydney, May 2001.

J. Yan and Randall Geiger, "Fast-Settling CMOS Operational Amplifiers with Negative Conductance Voltage Gain Enhancement", Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 228-231, Sydney, May 2001.

M. M. Amourah, and R. L. Geiger, "Gain and Bandwidth Boosting Techniques for High-Speed Operational Amplifiers,"Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 232-235, Sydney, May 2001.

H. Chen, F. Whiteside, and R. L. Geiger, "Current Mirror Circuit with Accurate Mirror Gain for Low Transistors," Proceedings of 2001 IEEE International Symposium on Circuits and Systems, pp 536-539, Sydney, May 2001.

Y. Cong and R. L. Geiger, "Performance Association and Discrimination Between Current-Mode and Voltage-Mode Operation of Monolithic Linear Circuits", Proc. Southwest Symposium on Mixed-Signal Design, p131 (title only – text missing in proceedings), Austin, February 2001.

2000

Cong, Y. and Geiger, R. L. , “Current Mirrors with Low Input, Output and Supply Voltage Requirements”, IEEE Midwest Symposium on Circuits and Systems, pp 490-493, Aug. 2000.

Younis, A.A., Amourah, M.M. and Geiger, R.L., “A High Frequency CMOS 4th Order digitally programmable Bandpass Filter”, IEEE Midwest Symposium on Circuits and Systems, pp 212-215, Aug. 2000.

Chen, H. and Geiger, R.L., “Maximizing the Oscillation Frequency of CMOS VCOS”, IEEE Midwest Symposium on Circuits and Systems, pp 1248-1251, Aug. 2000.

Chen, H., Malik, S. and Geiger, R.L., “High Frequency VCO-derived filters” IEEE Midwest Symposium on Circuits and Systems, pp 208-211, Aug. 2000.

Yan, J., and Geiger, R.L., “A Negative Conductance Voltage Gain Enhancement Technique for Low Voltage High Speed CMOS Op Amp Design”, IEEE Midwest Symposium on Circuits and Systems, pp 502-505, Aug. 2000.

Parthasarathy, K. and Geiger, R.L., “Unambiguous characterization and specification of D/A converter performance”, IEEE Midwest Symposium on Circuits and Systems, pp 890-894, Aug. 2000.

Lan, M.F., and Geiger, R.L., “Impact of Model Errors on Predicting Performance of Matching Critical Circuits”, IEEE Midwest Symposium on Circuits and Systems, pp 1324-1328, Aug. 2000.

Malik, S.Q. and Geiger, R.L., “Minimization of Area in Low-Resistance MOS Switches” IEEE Midwest Symposium on Circuits and Systems, pp 1392-1395, Aug. 2000.

Sclarmann, M. and Geiger, R.L., “Relationship Between Amplifier Settling Time and

Pole-Zero Placements for Second-Order Systems “, IEEE Midwest Symposium on Circuits and Systems, pp 54-59, Aug. 2000.

Schlarmann, R.E. and Geiger, R.L., “A Simple Linear Transresistor” IEEE Midwest Symposium on Circuits and Systems” , pp 1252-1255, Aug. 2000.

Tang, Y. and Geiger, R.L., “A Non-sequential Phase Detector for PLL-based High-Speed Data/Clock Recovery” IEEE Midwest Symposium on Circuits and Systems, pp 428-431, Aug. 2000.

Lan, M.F. and Geiger, R. L., "Simulation of Matching-Critical Circuits with Laterally Distributed Process and Device Parameters", Ph.D. Forum, IEEE Design Automation Conference, June 2000.

Lan, M.F. and Geiger,R.L. "Gradient Sensitivity Reduction in Current Mirrors with Non-Rectangular Layout Structures," IEEE International Symposium on Circuits and Systems, Lusanne, Switzerland, pp. 687-690, May 2000.

1999

Lan, M.F., Tammineedi, A.K., and Geiger, R.L., “A New Current Mirror Layout Technique for Improved Matching Characteristics”, 1999 IEEE Midwest Symposium on Circuits and Systems, pp.1126-1129, August 1999.

Lee, Y. and Geiger, R. L., “Gain Error Correction Scheme for Multiply-By-Two Gain Amplifier in Pipelined ADC”, 1999 IEEE Midwest Symposium on Circuits and Systems, pp. 190-193, August 1999.

Chen, Y., Schlarmann, M., and Geiger, R.L., “An Improved Design Formulation suitable for Optimization of Operational Amplifiers”, 1999 IEEE Midwest Symposium on Circuits and Systems, pp. 72-75, August 1999..

Schlarmann, M. and Geiger, R.L., “Preliminary Discussion of a World-Wide-Web Based Analog Circuit Design Tool and Design Knowledge Repository”, International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 61-64, Puerto Vallarta, , July 1999.

Chen, Y., Schlarmann, M., and Geiger, R.L., “ Amplifier Design for Fast Settling Performance”, International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 52-56, Puerto Vallarta, July 1999.

Nagavarapu, S., Yan, J., Lee, E. and Geiger, R.L., “An Asynchronous Delay-Line Based Data Recovery/Retransmission system with Foreground DLL Calibration”, IEEE International Symposium on Circuits and Systems, pp. 354-357, Orlando, June 1999.

Schlarmann, M, Lee, E. and Geiger, R.l., “A New Multipath Amplifier Design Technique for Enhancing Gain and Bandwidth”, IEEE International Symposium on Circuits and Systems, pp. 610-615, Orlando, June 1999.

Wu, L., Chen, H., Nagavarapu, S., Geiger, R.L., Lee, E., and Black, W., “A Monolithic 1.25Gbit/sec CMOS Clock/Data Recovery Circuit for Fibre Channel Transceiver”, IEEE International Symposium on Circuits and Systems, pp. 565-568, Orlando, June 1999.

Chen, H, Lee, E. and Geiger, R.L., “A 2GHz VCO with Process and Temperature Compensation”, IEEE International Symposium on Circuits and Systems, pp. 569-572, Orlando, June 1999.

1998

Chen, Y., Koneru, S., Lee, E., and Geiger, R.L., “Effects of Random Jitter on High-Speed CMOS Oscillators”, IEEE International Symposium on Circuits and Systems, pp. 176-180, Monterey, June 1998.

S. Koneru, Y. Chen, R. Geiger, and E. Lee, “Deterministic Phase Jitter in Multi-Phase CMOS Ring Oscillators Due to Transistor Mismatches”, IEEE International Symposium on Circuits and Systems, Monterey, pp. 213-216, June 1998.

M. Amourah and R. Geiger, “A Modified Costas Loop for Clock Recovery and Frequency Synthesis”, IEEE International Symposium on Circuits and Systems, pp. 171-175, Monterey, June 1998.

M.F. Lan and R. Geiger, “Matching Performance of Current Mirrors with Arbitrary Paremeter Gradients through the Active Devices”, IEEE International Symposium on Circuits and Systems, Monterey, pp. 555-558, June 1998.

R. Geiger, E. Lee, Bill Black, M. Hassoun, and Charles Wright, “Restructureing Electronic Circuits Education Around Integrated Circuit Technology of the Year 2000”, National Information Workforce Convocation, Berkeley, January 1998 (Invited by NSF).

1997

Y. Chen, S. Koneru, E. Lee, and R. Geiger, “Simulation of Random Jitter in Ring Oscillators with SPICE”, IEEE Midwest Symposium on Circuits and Systems, pp. 1154-1157, Davis California, August 1997.

S. Nagavarapu, A. Iyer, and R. Geiger, “A 1.0625 Gbps PECL Line Driver”, IEEE Midwest Symposium on Circuits and Systems, pp. 1158-1160, Davis California, August 1997.

M. Hassoun, W. Black, E. lee, R. Geiger and A. Hurst, “Field programmable logic gates using GMR devices, Proc. IEEE Conference on Magnetics, INTERMAG 97, pp. 3307-3309, April 1997.

V.K. Navin, T. Ray, M. Hassoun, W. Black, E. Lee, E. Soenen and R. Geiger, “A simulation environment for pipelined analog-to-digital converters”, IEEE International Symposium on Circuits and Systems, pp. 1620-1623, Hong Kong, June 1997.

1995

Kim, J. Y. and Geiger, R. L., “A Charge Conserving Macromodel for MOSFETS”, 38th IEEE Midwest Symposium on Circuits and Systems, pp. 49-52, Rio de Janeiro, Brazil, August 1995.

1994

Yu, C. G. and Geiger, R. L., "An Accurate and Matching - Free Threshold Voltage Extraction Scheme for MOS Transistors," IEEE International Symposium on Circuits and Systems, London, pp. 115-118, June 1994.

Kim, J. Y. and Geiger, R. L., "MOS Active Attenuators for Analog Integrated Circuits and Their Application to Finite Gain Amplifiers," IEEE International Symposium on Circuits and Systems, pp. 701-704, London, June 1994.

1993

Soenen, E. G. and Geiger, R. L., "A Fully Digital Self-Calibration Method for High Resolution, Pipelined A/D Converters," IEEE Midwest Symposium on Circuits and Systems, pp. 228-231, Detroit, August 1993.

Kim, J. Y. and Geiger, R. L., "Performance Characterization of an Active Attenuator Using Two Cascaded MOSFETs," 36th IEEE Midwest Symposium on Circuits and Systems, Detroit, pp 716-720, 1993.

Spalding, G. R. and Geiger, R. L., "Digital Correction for Improved Spectral Response in Signal Generation Systems," IEEE International Symposium on Circuits and Systems, pp. 132-135, Chicago, IL, May 1993.

Yu, C. G. and Geiger, R. L., "Very Low Voltage Operational Amplifiers Using Floating Gate MOS Transistors," IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1152-1155, Chicago, IL, May 1993.

Kim, J. Y. and Geiger, R. L., "An Inverting MOS Active Attenuator for Monolithic Applications," Midwest Electrotechnology Conference, pp. 110-113, Ames, IA, April 1993.

Yu, C. G. and Geiger, R. L., "Frequency Response Measurement Algorithms," Second Annual Midwest Electrotechnology Conference, pp. 56-59, Ames, IA, April 1993.

1992

Yu, C. G. and Geiger, R. L., "Precision Offset Compensated OP-Amp with Ping-Pong Control," Government Microcircuit Applications Conference, pp.189-190, December 1992.

Bliss, W. G., Seaberg, C. E., and Geiger, R. L., "A Very Small Sub-Binery Radix DAC for Static Pseudo-Analog High-Precision Memory," 35th Midwest Symposium on Circuits and Systems, pp. 425-428, Washington, D.C., August 1992.

Yu, C. G. and Geiger, R. L., "Analysis of Random Common-Made Rejection Ratio in OP Amps," 35th Midwest Symposium on Circuits and Systems, pp. 949-952, Washington, D.C., August 1992.

1991

Soenen, E. and Geiger, R. L., "The Charge Amplifier, an Alternative for Switched-Capacitor Stages," GOMAC-91, Orlando, FL, November 1991.

Loh, Kou-Hung and Geiger, R. L., "Frequency Response Measurements of High-Frequency Systems by Least Squares Identification Techniques," IEE, European Conference on Circuit Theory and Design, Copenhagen, Denmark, September 1991.

Olympie, Florence E. and Geiger, Randall L., "Automatic Generation of Simple Parametric Models for Electronic Devices," IEE European Conference on Circuit Theory and Design, The House of DIF, Copenhagen, Denmark, September 2-6, 1991.

Yu, Chong-Gun, Bliss, William G., and Randall L. Geiger, "A Tuning Algorithm for Digitally Programmable Continuous Time Filters," IEEE International Symposium on Circuits and Systems, pp. 1436-1439, Singapore, June 11-14, 1991.

Loh, Kou-Hung and Geiger, Randall L., "A CMOS Transconductance-C Integrator Structure with Wide-Band Programmability and Phase Lead/Lag Compensations," IEEE International Symposium on Circuits and Systems, pp. 2248-2251, Singapore, June 11-14, 1991.

Yu, Chong-Gun, Bliss, William G., and Randall L. Geiger, "A Frequency Domain Parametric System Identification Algorithm for Continuous-Time Linear Filters," IEEE International Symposium on Circuits and Systems, pp. 1725-1728, Singapore, June 11-14, 1991.

Loh, Kou-Hung, and Geiger, Randall L., "Dynamic Range Performance of a MOS Active Attenuator," IEEE International Symposium on Circuits and Systems, pp. 1733-1736, Singapore, June 11-14, 1991.

Ramírez-Angulo, J., Wang, R., and Geiger, R. L., "Improvement of Laser Trimmed Film Resistor Stability by Selection of Optimal Trim Paths," IEEE International Symposium on Circuits and Systems, pp. 2188-2191, Singapore, June 1991.

Hiser, D. and Geiger, R. L., "A Programmable Digitally-tuned CMOS-OTA-C Bandpass Filter Architecture for High-Accuracy Applications," 34th Midwest Symposium on Circuits and Systems, Monterey, CA, May 14-17, 1991.

Yu, C-G., Bliss, W. G., and Geiger, R. L., "Performance of High-Precision Digital Tuning Algorithm," 34th Midwest Symposium on Circuits and Systems, Monterey, CA, May 14-17, 1991.

1990

Robinson, M. E., Nevárez-Lozano, H., Ramírez-Angulo, J., and Geiger, R. L., "Maximum Value of the Base Resistance of Vertical Bipolar Transistors," IEEE International Symposium on Circuits & Systems, pp. 3182-3185, New Orleans, LA, May 1990.

Hiser, D. and Geiger, R. L., "Impact on OTA Nonlinearities on the Performance of Continuous-Time OTA-C Bandpass Filters," IEEE International Symposium on Circuits & Systems, pp. 1167-1170, New Orleans, LA, May 1990.

Setty, P., VanPeteghem, P. and Geiger, R. L., "Compensation of Spectral Source Impurities in Dynamic Measurements of Flash Converters," IEEE International Symposium on Circuits & Systems, pp. 2236-2239, New Orleans, LA, May 1990.

1989

Sweeney, J. and Geiger, R. L., "Very High Precision Analog Trimming Using Floating Gate MOSFETS," ECCTD, pp. 652-655, London, England, September 1989.

Loh, K. H., Hiser, D., Adams, W. and Geiger, R. L., "A Robust Digitally Programmable and Reconfigurable Monolithic Filter Structure," IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 110-113, Portland, Oregon, May 1989.

Adams, W., Loh, K. H., Nedungadi, A., and Geiger, R. L., "Design of a Programmable OTA with Multi-Decade Transconductance Adjustment," IEEE International Symposium on Circuits and Systems, Vol. 1, pp. 663-666, Portland, Oregon, May 1989.

1988

Geiger, R. L., "Robust Analog Signal Processing-A Challenge to Simulation and Testing," SRC Workshop on Analog Design Automation, Melbourne, Florida, December 1988 (invited).

Kim, T. G. and Geiger, R. L., "A 10 MHz CMOS Continuous-Time Programmable Bandpass Filter," GOMAC-88, pp. 231-234, Las Vegas, November 1988.

Loh, K. H. and Geiger, R. L., "Dynamic Range Potential of Monolithic Transconductance Amplifier Capacitor Filters," 31st Midwest Symposium on Circuits and Systems, St. Louis, Missouri, August 1988.

1987

Geiger, R. L., Sánchez-Sinencio, E., Nedungadi, A. P., Hiser, D. L., Adams, W. J. and Peterson, K. D., "A Reconfigurable Biquadratic Building Block for Digitally-Controlled Continuous-Time Signal Processing," Government Microcircuit Applications Conference (GOMAC), pp. 157-160, Orlando, FL, October 1987.

Sánchez-Sinencio, E., Qin, S. C., Geiger, R. L. and Peterson, K. D., "Monolithic Programmable State-Variable Biquadratic OTA-Capacitor (TAC) Filters," Proceedings European Conference on Circuit Theory and Design (ECCTD), pp. 327-331, Paris, France, September 1987.

Peterson, K. D., Nedungadi, A. P. and Geiger, R. L., "Amplifier Design Considerations for High Frequency Monolithic Filters," Proceedings European Conference on Circuit Theory and Design (ECCTD), pp. 321-326, Paris, France, September 1987.

Qin, S. C. and Geiger, R. L., "A Linear Monolithic Active Attenuator with Multiple Output Taps," Proceedings 30th Midwest Symposium on Circuits and Systems, pp. 765-768, Syracuse, August 1987.

Kim, S. W. and Geiger, R. L., "Design of a CMOS Differential Amplifier Using a Source-Coupled Backgate Pair," Proceedings 30th Midwest Symposium on Circuits and Systems, pp. 929-932, Syracuse, August 1987.

Geiger, R. L. and Ramírez-Angulo, J., "Structures and Trimming Strategies for Improving the Practical Resolution of Laser-Trimmed Film Resistors," Linear Radiation Hardening Workshop, Anaheim, CA, June 1987.

Sánchez-Sinencio, E., Geiger, R. L. and Nevárez-Lozano, H., "Generation of Continuous-Time Two Integrator Loop OTA Filter Structures," IEEE International Symposium on Circuits and Systems, pp. 325-328, Philadelphia, PA, May 1987.

1986

Geiger, R. L., Sánchez-Sinencio, E., Nedungadi, Ashok, Hiser, Doug and Kim, Tae Guen, "Digitally Controlled Analog Signal Processing," GOMAC-86, pp. 267-270, San Diego, CA, November 1986.

Ramírez-Angulo, J., Sánchez-Sinencio, E. and Geiger, R. L., "A Program for the Characterization of RC-Distributed Elements Based on the Finite Elements Method," Paper 170 Mexicon 86, Mexico City, Mexico, October 1986.

Qin, S. C. and Geiger, R. L., "A CMOS OTA for Voltage-Controlled Signal Processing Applications," Proceedings 1986 International Conference on Semiconductor and Integrated Circuit Technology, pp. 572-574, Beijing, China, October 1986.

Reed, R. and Geiger, R. L., "An Operational Transconductance Amplifier with Multiple Inputs and a Wide Linear Range," 1986 Midwest Symposium on Circuits and Systems, pp. 368-371, Lincoln, NE, August 1986.

Peterson, K. and Geiger, R. L., "A Fully Balanced CMOS OTA for High Frequency Monolithic Filters," 1986 Midwest Symposium on Circuits and Systems, pp. 208-211, Lincoln, NE, August 1986.

Nedungadi, A. and Geiger, R. L., "A 1 MHz Voltage-Controlled Continuous-Time Bandpass/Lowpass Filter Using Linearized CMOS OTA's," 1986 Midwest Symposium on Circuits and Systems, pp. 204-207, Lincoln, NE, August 1986.

Sánchez-Sinencio, E., Ramírez-Angulo, J. and Geiger, R. L., "A Computer-Aided Design Program for Reduction of Total Capacitance in Cascade SC Filters," 1986 Midwest Symposium on Circuits and Systems, pp. 597-599, Lincoln, NE, August 1986.

Kim, S. W. and Geiger, R. L., "A Micropower Continuous-Time CMOS OTA Filter Operating in the Subthreshold Region," 1986 Midwest Symposium on Circuits and Systems, pp. 200-203, Lincoln, NE, August 1986.

Xuexiang, C. Z., Sánchez-Sinencio, E., and Geiger, R. L., "A Pole-Zero Pairing Strategy for Area and Sensitivity Reduction in Cascade SC Filters," Proceedings IEEE International Symposium on Circuits and Systems, pp. 609-611, San Jose, CA, May 1986.

Ramírez-Angulo, J., Geiger, R. L., and Sánchez-Sinencio, E., "A Circuit Analysis Approach to the Performance, Evaluation and Comparison of Laser-Trimmed Film Resistors," Proceedings IEEE International Symposium on Circuits and Systems, pp. 1201-1204, San Jose, CA, May 1986.

Ramírez-Angulo, J., Geiger, R. L., and Sánchez-Sinencio, E., "FIRE: A Computer Program to Predict the Performance of Laser-Trimmed Film Resistors," Proceedings 36th Electronics Components Conference, pp. 405-411, Seattle, WA, May 1986.

1985

Van Horn, M. and Geiger, R. L., "A CMOS OTA for Voltage-Controlled Analog Signal Processing," Proceedings 28th Midwest Symposium on Circuits and Systems, pp. 596-599, Louisville, Kentucky, August 1985.

Ramírez-Angulo, J., Geiger, R. L., and Sánchez-Sinencio, E. "Component Quantization Effects on Continuous-Time Filters," IEEE 1985 International Symposium on Circuits and Systems, pp. 1423-1426, Kyoto, Japan, June 1985.

1984

Peterson, K. and Geiger, R. L., "CMOS OTA Structures with Improved Linearity," Proceedings 27th Midwest Symposium on Circuits and Systems, pp. 63-66, Morgantown, West Virginia, June 1984.

Rybicki, M. and Geiger, R. L., "A Temperature Stable and Process Compensated MOS Active Filter," Proceedings 1984 IEEE International Symposium on Circuits and Systems, pp. 940-943, Montreal, Canada, May 1984.

Geiger, R. L., Sánchez-Sinencio, E. and Silva-Martinez, J. "Tradeoffs Between Passive Sensitivity, Output Voltage Swing and Total Capacitance in SC Filters," Proceedings 1984 IEEE International Symposium on Circuits and Systems, pp. 1062-1064, Montreal, Canada, May 1984.

1983

Bass, J. and Geiger, R. L., "Performance Characteristics of Switched Resistor Filters," Sixth European Conference on Circuit Theory and Design, pp. 114-116, West Germany, September 1983. (Invited Paper)

Fincher, J. and Geiger, R. L., "Monolithic Frequency Referenced Digitally Self-Tuned Filters," Proceedings 1983 Midwest Symposium on Circuits and Systems, pp. 522-525, Puebla, Mexico, August 1983.

Sánchez-Sinencio, E., Silva-Martinez, J. and Geiger, R. L., "General Second-Order SC Filters with Reduced GB Effects," 1983 IEEE International Symposium on Circuits and Systems, Newport Beach, May 1983.

Rybicki, M. and Geiger, R. L., "Laser Trimmable Temperature Compensation Technique for Monolithic NMOS Resistors," Proceedings 1983 IEEE International Symposium on Circuits and Systems, pp. 1363-1365, Newport Beach, May 1983.

Ferrell, J. and Geiger, R. L., "Voltage-Controlled Filter Design Using Operational Transconductance Amplifiers," Proceedings 1983 IEEE International Symposium on Circuits and Systems, pp. 594-597, Newport Beach, May 1983.

1982

Geiger, R. L., and Rybicki, M., "A High Frequency Temperature Invariant Active NMOS Active Filter," Proceedings 25th Midwest Symposium on Circuits and Systems, pp. 321-324, Houghton, MI, August 1982.

Bass, J. and Geiger, R. L., "A Monolithic Switched-Resistor Integrator Building Block," Proceedings 1982 IEEE International Symposium on Circuits and Systems, pp. 221-224, Rome, May 1982.

Sánchez-Sinencio, E., Geiger, R. L., Silva-Martinez, J., "Minimization of Gain-Bandwidth Products Effects in Switched-Capacitor Filters," Proceedings 1982 IEEE International Symposium on Circuits and Systems, pp. 468-471, Rome, May 1982.

1981

Silva-Martinez, J., Sánchez-Sinencio, E., and Geiger, R. L., "Simple Switched-Capacitor Circuits as Affected by the Op-Amp Gain-Bandwidth Product," Fifteenth Annual Asilomar Conference on Circuits, Systems, and Computers, Pacific Grove, CA, November 1981.

Geiger, R. L. and Allen, P. E., "Switched Resistor Filters," Proceedings 24th Midwest Symposium on Circuits and Systems, pp. 87-91, Albuquerque, NM, June 1981. (Invited)

Pettit, R. and Geiger, R. L., "Electromagnetic Properties of Aspergillus Flavus Invaded Peanut Kernels," Texas Ag. Exp. Station Progress Report 3826, 1981.

Allen, P. E., Strader, N. and Geiger, R. L., "Graduate and Undergraduate Educational Methods for Microelectronics," 4th UGIM Symposium, Mississippi, May 1981.

Geiger, R. L. and Sánchez-Sinencio, E., "Operational Amplifier Gain-Bandwidth Product Effects on the Performance of Switches-Capacitor Networks," Proceedings 1981 IEEE International Symposium on Circuits and Systems, pp. 37-40, Chicago, IL, April 1981.

1980

Geiger, R. L. and Sánchez-Sinencio, E., "A Comparison of Switched-Capacitor Integrators with Respect to the Operational Amplifier Gain-Bandwidth Product," Proceedings 23rd Midwest Symposium on Circuits and Systems, pp. 444-448, Toledo, August 1980.

Pettit, R. and Geiger, R. L., "Dielectric Properties of Mold and Mycotoxin Damaged Peanuts," Proceedings American Phytopathological Society Meeting, Phytopathology, Vol. 71, p. 429, Minneapolis, MN, August 1980.

Geiger, R. L., and Bailey, G., "A New Integrator with Reduced Amplifier Dependence for Use in Active RC-Filter Synthesis," Proceedings 1980 IEEE International Symposium on Circuits and Systems, pp. 87-90, Houston, TX, April 1980.

Budak, A. and Geiger, R. L., "Design of Active Filters Independent of First and Second Order Operational Amplifier Time Constant Effects," Proceedings 1980 IEEE International Symposium on Circuits and Systems, pp. 849-852, Houston, TX, April 1980.

1979

Geiger, R. L., "Approximation of Parasitic Roots of Active Transfer Functions," Proceedings 22nd Midwest Symposium on Circuits and Systems, pp. 576-581, Philadelphia, PA, June 1979.

1978

Budak, A. and Geiger, R. L., "Biquadratic Active Filters with Zero Amplifier Sensitivity," Proceedings 21st Midwest Symposium on Circuits and Systems, pp. 188-192, Ames, IA, August 1978.

Geiger, R. L., "Zero-Sensitivity Active Filters Employing Finite Gain Voltage Amplifiers," Proceedings 1978 International Symposium on Circuits and Systems, pp. 1064-1068, New York, NY, May 1978.

Books or Chapters of Books

Yu, C. G. and Geiger, R. L., "Low Voltage Analog Circuit Design," Chapter titled "Precision Low Voltage Circuit Techniques," IEEE Press, Edited by E. Sanchez-Sinencio. 1998.

Geiger, R. L., Allen P., and Strader, N., VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill, New York, 1990.

Geiger, R. L., RC Active Design Manual, Chapter 4, John Wiley and Sons, Edited by Dr. F. W. Stephenson, 1985.

RECENT TECHNICAL PRESENTATIONS

(See Refereed Journals and Proceeding Articles above)

EXTENSION/OUTREACH ACTIVITIES

Lectures and Short Courses (selected – most years I do not keep track of this information)

Geiger, R.L., “Testing and Calibration of Integrated Circuits”, 1st African Workshop on Emerging Trends in Circuits and Systems (WETCaS), Kumasi, Ghana, Africa, Nov. 2017.

Geiger, R.L., “Analog Hardware Trojans – Vulnerability and Mitigation, University of Minnesota, Dec. 2015.

Geiger, R.L., “On-Chip Thermal Management for Reliable Integrated Circuits” John Choma Commemorative Invited Lectures, ISCAS, Lisbon, Portugal, May 2015.

Geiger, R.L, “Verification of Mixed-Signal Circuits with Vulnerability to Multiple Analog Hardware”, Aptina/ON Semiconductor, San Jose, Feb. 2015.

Geiger, R.L, “Verification of Mixed-Signal Circuits with Vulnerability to Multiple Stable Equilibrium Points and Analog Hardware”, TxAce/SRC WEB Lecture, University of Texas at Dallas, Jan.2015

Geiger, R.L, “AMS Testing with Signal Processing Support: Strategies for Test-Cost reduction and AMS BIST”, TxAce/SRC WEB Lecture, University of Texas at Dallas, Jan.2012

Geiger, R.L, “Temperature Sensor Design for Power/Thermal Management in Emerging Processes”, Freescale, Tempe Arizona, Feb. 2012

Geiger, R.L., “AMS Testing with Signal Processing Support: methods for test-cost reduction and AMS BIST”, Texas Instruments, Tucson Arizona, Jan. 2011.

Geiger, R.L., “Temperature Sensor Design for Power/Thermal Management in Emerging Semiconductor Processes”, Fort Collins Chapter, IEEE Solid State Circuits Society, Ft. Collins, July 2011.

Geiger, R.L., “Threshold-based On-Chip Temperature Measurements”, Broadcom, Irvine California, June 2011

Geiger, R.L, “Temperature Sensor Design for Power/Thermal Management in Emerging Semiconductor Processes”, Fort Collins Chapter, IEEE Solid State Circuits Society, Ft. Collins, July 2011.

Geiger, R.L., “Conventional Wisdom – Benefits and Consequences of Annealing Understanding of Engineering Principles”, Keynote Address, IEEE Asian Pacific Conference on Circuits and Systems (APCAS), Kuala Lumpur, Dec. 2010.

Geiger, R. L., “Analog and Mixed-Signal Design for SOC in Emerging Digital Processes” (lecture), National Taiwan University of Science and Technology, Taiwan, November 2003.

Geiger, R. L., “Analog and Mixed-Signal Design for SOC in Emerging Digital Processes” (lecture), Kaohsiung University, Taiwan, March 2003.

Geiger, R. L., “Analog and Mixed-Signal Design for SOC in Emerging Digital Processes” (short course), Tatung University, Taiwan, March 2003.

Geiger, R. L., “Analog and Mixed-Signal Design for SOC in Emerging Digital Processes” (short course), Tamkang University, Taiwan, Dec. 2002.

Geiger, R.L., “Layout Techniques for Enhancing Yield in Monolithic Analog Circuits”, Tatung University, Taiwan, Dec. 2002.

Geiger, R.L., “Layout Techniques for Enhancing Yield in Monolithic Analog Circuits”, IEEE CAS Dallas Chapter, Dec. 2002.

Geiger, R.L. Panelist for Panel Discussion “Emerging Role of Circuits and Systems Technologies in Telecommunications”, IEEE Midwest Symposium on Circuits and Systems, East Lansing, August 2000.

Geiger, R.L., “Design Strategies for Low Voltage and Energy Efficient Pipelined Data Converters”, IEEE Dallas Workshop on Low Voltage Mixed Signal Circuits and Systems, Dallas Texas, March 2001

.

Geiger, R.L., “Analog and Digital Integrated Circuit Design – An Intense Short Course”, Allied Signal, Nov. 1999-January 2000

Geiger, R.L., “Analog Circuit Design”, IEEE Latin America Lecture Series, Argentina and Brazil, November 1999.

Geiger, R. L., "Introduction to VLSI Design," Short Course, University of Colima, Mexico, Guest Lecturer, October 1985. (with E. Sánchez-Sinencio)

Geiger, R. L., "Applications of the Transconductance Amplifier in VLSI Design," University of Nebraska, Lincoln, NE, Guest Lecturer, February 1987.

Geiger, R. L., "Applications of OTA's in Voltage Controlled Circuits," Nankai University, Tianjin, China, Guest Lecturer, October 1986.

Geiger, R. L., "Design of Monolithic Transconductance Amplifiers," Tsinghua University, Beijing, China, Guest Lecturer, October 1986.

Geiger, R. L., "Practical Considerations in Switched Capacitor Circuit Design," Tianjin University, Tianjin, China, Guest Lecturer, October 1986.

Geiger, R. L., "Introduction to VLSI Circuit Design," Short Course, Midwest Symposium on Circuits and Systems, Lincoln, NE, August 1986. (with E. Sánchez-Sinencio)

Geiger, R. L., "Digitally Controlled Analog Signal Processing," University of Rochester, Guest Lecturer, October 1985.

Geiger, R. L., "Monolithic High Frequency and Biomedical Integrated Circuit Design," University of Colima, Mexico, Guest Lecturer, October 1985.

Geiger, R. L., "Integrated Circuit Design with Applications to Switch-Capacitor Techniques," Short Course, George Washington University Continuing Education, Washington, D.C., July 1985. (with E. Sánchez-Sinencio)

Geiger, R. L., "Integrated Circuit Design with Applications to Switch-Capacitor Techniques," Short Course, George Washington University Continuing Education, Washington, D.C., January 1985. (with E. Sánchez-Sinencio)

Geiger, R. L., "Public Utility Short Course for Electrical Metermen-Analog IC Applications Section," TAMU, College Station, Texas, November '80, '81, \&'82, '83, '84, '85, '86, and '87.

Geiger, R. L., "Use of the Multiproject Chip in Microelectronics Education," Virginia Polytechnical Institute (VPI), Guest Lecturer, February 1983.

Geiger, R. L., "Analog IC Filters - Several Design Approaches," Instituto Nacional De Astrofísica, Optica y Electrónica, (INAOE) Puebla, Puebla, Mexico, November 1982.

Geiger, R. L., "Design of Switched-Resistor Filters," Instituto Nacional De Astrofísica, Optica y Electrónica, (INAOE) Puebla, Puebla, Mexico, November 1981.

Geiger, R. L., "Operational Amplifier Effects on SC and Active RC Filters," Instituto Nacional De Astrofísica, Optica y Electrónica, (INAOE) Puebla, Puebla, Mexico, November 1980.

PATENTS

S Laflamme, RL Geiger, “Tire sensing method for enhanced safety and controllability of vehicles”, US Patent 9,815,343, issued November 14, 2017.

R.L. Geiger, D.Chen, B. Olleta, and H. Jiang, "Method for Testing Analog and Mixed-Signal Circuits Using Dynamic Element Matching for Source Linearization." , US Patent 7,587,647, issued September 8, 2009.

R.L. Geiger, K. Parthasarathy, D. Chen, L. Jin, and Turker Kuyel, “Method for testing analog and mixed-signal circuits using functionally related excitations and functionally related measurements”, US Patent 7,129,734 issued October 31, 2006.

U.S. Patent No. 5,327,129, "Accuracy Bootstrapping," by E. G. Soenen and R. L. Geiger, July 1994.

GRADUATE STUDENTS

Current

Qianqian Wang Ph.D.

Srijita Patra Ph.D.

Palavi Ebenezer M.S.

Past

MS Year

Chin-Chen Chen 2017

Yunting Yin 2017

Wenbing Ma 2017

Xilu Wang 2017

Spurthi Nagulapally 2017

Chris Kranz 2016

Xing Cao 2015

Shiya Liu 2015

Dong Ding 2015

Rui Bai 2014

Guoyan Kai 2014

Srijita Patra 2014

Alex Lee 2011

Thu Duong 2009

Jake Sloat 2009

Yingkun Gai 2007

S. Thoka 2006

X. Dai 2006

K. Kyaw 2005

B. Olleta 2003

K.C. Tiew 2002

K. Parthasarathy 2002

S. Gondi 2002

P. Dagli 2001.

A. Ismail 2000

A. Joharapurkar 2000

J. Ye 2000

Y. Lee 1999

M. Amourah 1999

S. Nagavarapu 1999

A. Iyer 1998.

J. Zhou 1997

T. Brooks 1992

M. Hassan 1992

F. Olympie 1992

E. Seaberg 1991

T.S. Kim 1990

S. Narayan 1990

J. Sweeney 1989

R. Cook 1986

R. Reed 1986

R. Mallett 1985

M. Van Horn 1985

J. Fincher 1984

J. Bass 1983

J. Ferrell 1983

M. Rybicki 1983

P. Grignoux 1981

T. Ngo 1981

G. Bailey 1980

PhD Year

Tina Wang 2015

Chen Zhao 2014

Bharath Vasan 2013

Siva Sudani 2013

Jun He 2010

Vipul Katyal 2008

S. Chao 2007

H. Fei 2007

S Q. Malik 2006

Yu Lin 2006

H. Chen 2004

M. Schlarmann 2004

J. Yan 2002

M. Amourah 2002

Y. Tang 2002

Y. Cong 2002

M. Lan 2000.

J. Y. Kim 1995

G. Spalding 1994

C. G. Yu 1993

E. Soenen 1992

Y. Rong 1992

L. Loh 1991

D. Hiser 1990

T.-G. Kim 1988

A. Nedungadi 1987

K. Peterson 1987

PROFESSIONAL ACTIVITIES

IEEE CAS Society John Choma Teaching Award Committee (Chair, 2018)

EEE Kirchoff Awards Committee (Member 2012, Chair 2013,2014, Member 2015)

IEEE Periodical Products Council (Member 2007-2008)

IEEE Fellows Committee (Member, 2005-2007)

Institute of Electrical and Electronics Engineers (IEEE) (Fellow 1990)

Division I Representative on IEEE Publications Board and Periodicals Council (1990 - 1992)

IEEE Periodicals Council, (Member, 1993 - 1997, Chairman Transactions Committee, 1993 - 1997)

IEEE Publication Board, (Member, 1994 - 1996)

Audio Engineering Society (Member approx 1980-1990)

American Society for Engineering Education (Member, 1990 - 1997)

National Electrical Engineering Department Heads Association NEEDHA (Member 1990 - 1995)

Central States Department Heads Association (Member, 1992 - 1995, Chair 1995)

NEEDHA Annual Survey Coordinator (1994 and 1995)

Professional Responsibilities:

Technical Program Co-chair, IEEE Midwest Symposium, 2014.

Chair, CAS Education Award Subcommittee, 2011.

Member, IEEE CAS Fellows Committee, 2010.

Panelist, IEEE International Symposium on Circuits and Systems,

Panelist, IEEE International Test Conference, Austin, October 2010.

External Evaluation Committee, College of Engineering, University of Texas at Dallas (chair) Spring 2008.

Panelist, IEEE International Solid State Circuits Conference,

Technical Program Committee (Responsible for analog track), IEEE Midwest Symposium on Circuits and Systems, Midwest Symposium on Circuits and Systems, Tulsa, August 2002.

Session Chairman, IEEE International Symposium on Circuits and Systems, Sydney, June 2001.

Session Chairman, IEEE Midwest Symposium on Circuits and Systems, East Lansing, August 2000.

Technical Program Committee, IEEE International Symposium on Circuits and Systems, Orlando,

May 1999.

Technical Program Committee, IEEE International Symposium on Circuits and Systems, Monterrey, May 1998, Chair, Analog Track

Member, Comission Dictaminadora Externa (External Evaluationg Committee) Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico (1997,1998,1999,2000,2001)

Chairman, Workshops, IEEE International Symposium on Circuits and Systems, Chicago, 1993

President, IEEE Circuits and Systems Society (Elected) 1992

President Elect, IEEE Circuits and Systems Society (Elected) 1991

Vice President - Publications, Administrative Committee, IEEE Circuits and Systems Society, (Elected), 1989 to 1990.

Chairman, Special Sessions, IEEE International Symposium on Circuits and Systems, New Orleans, LA, 1990.

Consulting Editor, McGraw Hill Encyclopedia of Science and Technology, (1987 to 1988).

Chairman, Publications Committee, IEEE Circuits and Systems Society, 1987 to 1988).

CAS Society Editor, IEEE Circuits and Devices Magazine, (1986 to 1989).

Member, Scientific Committee, European Conference on Circuits Theory and Design, 1989.

Member, Ad Com, IEEE Circuits and Systems Society, Elected, 1986 to 1993.

Member, Technical Committee on Analog Signal Processing, IEEE Circuits and Systems Society,

1985 to present.

Guest Editor, IEEE Circuits and Devices Magazine, Special Issue on Workstations, July 1986.

Associate Editor, IEEE Trans. on Circuits and Systems, (1983 to 1985, 1999 to 2001).

Member, Steering Committee of Midwest Symposium, 1980 to present.

Conference Chairman, 5th UGIM Conference, Texas, May 1983.

Professional Activities:

Panel Member, NSF Career Program, November 2015

Panel Member, NSF ILI Program, January 1998

Panel Member, NSF ABIR Program, September 1998

Panel Member, NSF ATE Program, December 1998 (panel chair)

Panel Member, NSF CCLI Program, Feb. 1999 (panel chair)

Invited Participant, ,NSF CCLI Program Evaluation Meeting, January 1999

Session Chairman, Communication Circuits 1999 IEEE International Symposium on Circuits and

Systems, Orlando, May 1999.

Finance Chairman, 1996 Great Lakes Symposium, Ames, IA, March 1996.

Session Chairman, "Analog Circuits," IEEE Midwest Symposium on Circuits and Systems, Rio de

Janeiro, Brazil, August 1995.

Session Chairman, "Switched-Capacitor Filter," Midwest Symposium on Circuits and Systems,

Monterey, CA, May 1991.

Panelist, Mixed-Model ASIC Design Tools, ASIC Seminar and Exhibit, Rochester, New York, September 1990.

Session Chairman, "Switched-Capacitor Filters," IEEE International Symposium on Circuits and

Systems, New Orleans, May 1990.

Sessions Chairman, "Continuous-Time Filters and Networks," ECCTD '89, Brighton, UK, September 1989.

Panelist, VLSI Curriculum, VLSI Conference and Exposition, Santa Clara, CA, July 1989.

Session Chairman, "Analog Circuit Design," Midwest Symposium on Circuits and Systems, St.

Louis, MO, August 1988.

Participant, NSF VLSI Workshop on VLSI Education, Washington, D.C. November 1987.

Panel Organizer and Moderator, Midwest Symposium on Circuits and Systems, "Gallium Arsenide

and High Speed Bipolar Silicon as Technologies for High Speed IC's in the '90's," Syracuse,

NY, August 1987.

Session Co-Organizer, "Continuous-Time Integrated Circuit Signal Processing," IEEE International

Symposium on Circuits and Systems, Philadelphia, PA, May 1987.

Session Chairman, "Digital Systems," 30th Midwest Symposium on Circuits and Systems, Syracuse, NY, August 1987.

Session Chairman, "Testability and Fault Diagnosis for VLSI," 29th Midwest Symposium on Circuits

and Systems, Lincoln, NE, August 1986.

Session Chairman and Organizer, "Telecommunication Circuits and Applications," IEEE International

Symposium on Circuits and Systems, San Jose, CA, May 1986.

Sessions Chairman, "MOS Circuit Design and Applications," 28th Midwest Symposium on Circuits

and Systems, Louisville KY, August 1985.

Session Chairman and Organizer, "Design Using Operational Transconductance Amplifiers," 27th

Midwest Symposium on Circuits and Systems, Morgantown, WV, June 1984.

Session Chairman and Organizer, "Laser Trimming of Monolithic Integrated Circuits," (all invited

contributors) IEEE International Symposium on Circuits and Systems, Montreal, Canada,

May 1984.

Session Chairman and Organizer, "Integrated Analog Active Filters," (all invited contributors) IEEE

International Symposium on Circuits and Systems, Montreal, Canada, May 1984.

Session Chairman and Organizer, "Laser Trimming of Monolithic Integrated Circuits, 26th Midwest

Symposium on Circuits, Puebla, Puebla, Mexico, August 1983.

Session Chairman and Organizer, "Active Filters," 25th Midwest Symposium on Circuits and

Systems, Houghton, MI, August 1982.

Session Chairman, "Switched Capacitor Circuits," 24th Midwest Symposium on Circuits and

Systems, Albuquerque, NM, June 1981.

Reviewer for:

IEEE Trans. Circuits and Systems

IEEE Trans. Electron Devices

IEEE J. Solid State Circuits

IEE Proceedings

IEEE Trans. Components, Hybrids and Mfg. Technology

IEEE Int. Symposium on Circuits and Systems

IEEE Midwest Symposium on Circuits and Systems

CAS Magazine

National Science Foundation

Engineering Foundation

UNIVERSITY ACTIVITIES

University Committee

1999-2005 Welfare and Benefits Committee

Departmental Committees

1991-2015

Periodic service on Graduate Committee, Faculty Search Committee, Curriculum Committee, Honors and Awards Committee, and Promotion and Tenure Committee.

1978-1990:

Member of Curriculum Committee, Computer Usage Committee, Graduate Committee, Awards Committee and Promotion and Tenure Committee numerous times in the Electrical Engineering Department at Texas A&M University.

Member of Department Head Search Committee and Chairman of Endowed Chair Search Committee at Texas A&M University.

OTHER INFORMATION

Courses Developed or Co-Developed

ISU No. EE 505 Data Converter Design (major redevelopment)

ISU No EE 435 Analog VLSI Circuit Design (major redevelopment)

ISU No. EE 330 Integrated Electronic Circuits

ISU No. EE 230 Electronic Systems

ISU No. EE 434 Analog and Digital VLSI Design (Undergraduate -Major revision with same course number)

ISU No. EE/CpE 508 Integrated Filter Design (Graduate)

ISU No. EE/CpE 501 Analog VLSI Circuit Design (Graduate)

ISU No. EE 231 Electronic Circuits (Major revision of existing course Undergraduate)

TAMU No. EE 474 Microelectronic Circuit Design (Undergraduate)

TAMU No. EE 620 Network Theory (Graduate)

TAMU No. EE 622 Active Network Synthesis (Graduate)

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