Guidlines/Clean - ADCO Circuits



ADCO DESIGN GUIDELINESThe ADCO Design Guidelines is a publication of ADCO Circuits, Inc., and is provided to aid engineers in designing and planning the manufacturing of electronic assemblies. It is not intended to be used as a replacement for applicable design standards. No warranty is made, express or otherwise, regarding the accuracy of the information contained herein. As such, all information and specifications are subject to change without notice. Any comments or questions about the Guidelines should be directed to:SalesADCO Circuits, Inc.2868 Bond StreetRochester Hils, MI 48309(248) 853-6620(248) 853-6698 faxsales@1) GENERAL NOTES IPC Specification Tree lists all relevant IPC standards (). We suggest you copy Document Revision Table from into excel and use the excel search tool to find more details on the specifications listed on the Tree. Follow design rules that are specified by component manufacturers. ADCO size limits: SMT line – Max - 20" x 16", Min - 5.000" in X, 4.250" in the Y (length > width) Component - 45mm x 100mm x 225mm (ht) BGA X-ray 14” x 10” from center of item being processed Cost Influencers:Choose surface mount (SMT) devices over through hole (TH) if unit costs equateHave more than one approved mfg. part number on the AVLIf you have space, avoid 0402 and smaller for visual inspection & rework reasonsUse least quantity of layers possibleUse conventional thickness of 0.062" to reduce bowing Trace space & width 0.004 or greater Finished hole sizes 0.008 or greaterLocate BGA's, large actives, and through-hole components on the top side Locate passives and smaller actives on the bottom sideKeep copper thickness 0.5 to 1.0 ozAvoid dimensional location call outs for SMT devicesAvoid the use of shielding if possibleEliminate all hand soldering operations. Leave adequate space around TH connectors for selective soldering Low volume usually utilize functional testersHigher volume can justify costs of automated test eqp., test points may be required2) PWB FABRICATION DRAWING Every Printed Wiring Board (PWB) should have a drawing that specifies how it is to be built in addition to the Gerber Files. The Fabrication Drawing at a minimum should include the following items. Ref: IPC–D-325Dimensions and tolerances including thicknessHole-chart specifying finished size, count, plating, plugging or tenting.Class of IPC for acceptability - most common 2, Ref IPC-6011 Stack-up / Layer DetailLaminate Specification - Ref: IPC Laminate Section of TreeIf rigid, IPC 4101 lists the options, suggest /24 if lead-freeMin. copper plating in holes - Suggest 0.001Final Finish / Surface Plating For SMT assemblies suggest ENIG per IPC-4552For non-SMT assemblies suggest HASL / LF_HASLSolder Mask - Suggest IPC-SM-840 (Class T for IPC class 2 assemblies, Class H for IPC class 3 assemblies) over bare copper, via holes to remain openSilkscreen - Suggest white epoxy, none allowed on pads Nickel / Gold Edge Contacts - Ref: IPC-6012 Testing Method / Requirements - Suggest 100% Net-ListAssociated Gerber File Name Descriptions3) VIASVias should not be tented as it is an imperfect process and can trap chemicals that may lead to degradation of plating. Refer to IPC-T-50 for definition of 7 methodologies (tent, tent & cover, plug, plug & cover, fill, fill & cover, fill & cap) If via-in-pad must be used, cap and/or mask it. Capping the component side is better than capping the bottom because it reduces the chance of out-gassing and voids. Make it as small as possible. For BGAs, your only option is to fill and cap over the vias. For QFNs, you can also cap or tent the vias.4) RAILS / ARRAYS Assemblies are typically transported with conveyors and are supported along the long edges of the assembly. Components cannot encroach along these edges. A 3mm clearance is required for single sided assemblies and the top of double sided assemblies, 5mm for the bottom of double sided assemblies. Rails may need to be added to adhere to this standard. Rails to be a width of 0.500” with 3 corner fiducials at 0.250” in the X & Y.For small PWB’s, it is advantageous to assemble them in an array configuration to reduce the handling through the assembly operation. The limiting factor of an array is the stability it offers during the manufacturing process. Thinner boards require smaller array size.If the design prohibits the use of arrays or rails, then carriers will need to be ponents that extend beyond the edge of the board must be accommodated with space between boards if designing an array. If the PWB is mostly square or rectangular, then V-scored rails / array can be configured. If the PWB is not, or has parts overhanging, a routed style array utilizing router tabs or mouse bite breakaway tabs is an option. Routed arrays require fixturing to be routed during depanelingCopper layers & edge trace clearance – To prevent damage during depaneling, copper planes and traces should be at least 1mm from edge of board or edge features in arraysArray should be a multiple to accommodate quote quantities. Array should be submitted for ADCO’s review of manufacturability and approval.V-Scored ArraysMinimum dimensions - 5.0” in the X and 4.25” in the YMaximum dimensions if 0.062 thick - 19.5” in the X and 14.75” in the YMaximum dimensions if 0.031 thick - 11” in the X and 9” in the YV-Score to be 1/3 deep on each side leaving 1/3 thickness of the board Routed ArraysMinimum dimensions - 5.0” in the X and 4.25” in the Y.Maximum dimensions if 0.062+ thick - 19.5” in the X and 13.75” in the Y.Maximum dimensions if 0.031- thick- 11” in the X and 9” in the YTooling holes needed in each corner at 0.500” in the X, and 0.200” in the Y. Routing tab size to be 0.10” X 0.094” Material needed between boards at a width of 0.250”Standard 0.500” top and bottom rail w/fiducials neededRail fiducials to be a 0.250” in the X and Y from 3 corners.5) FIDUCIALS When designing a surface mount board there should be at least 3 global fiducials on each side with SMT components. When there are fine pitch parts on the board (pitch <0.020) then two local fiducials are needed. These fiducials should be .040” in diameter and should be located within two opposing corners of the footprint of the part.The fiducials shape should be a solid filled circle at least .040” in 3 corners of the board typically .250” x .250” from the edge of the board. The fiducial must have a clearance area of at least two times the diameter of the fiducial. Do not have masking in the clearance area or on the fiducial itself.6) SILKSCREEN Reference Designators should be placed outside of the body of the component and they should all face in the same direction.Polarity of components should be identified by the silkscreenPin 1 should be identified by the silkscreenOutline of a non symmetrical part can be used to ID polarity7) TOOLING AND INSERTION HOLESTooling hole locations shall be provided in at least two corners on the same card edge. Diagonal tooling holes are allowable. Recommend tooling hole size to be .125” in diameter and .250” x .250” from the corners of the PCB. Tooling holes should have .5” clearance to nearest axial and dip hole locations.Board locator tooling hole position +/- .001”Board locator tooling hole diameter +/- .002”Axial insertion hole diameter = maximum lead diameter plus .015”Dip insertion hole diameter = maximum lead diameter .015”8) SELECTIVE SOLDER Automated selective soldering requires clearance around the joints to be soldered to accommodate the contact diameter of the nozzle’s solder puddle. The contact diameter is the circular area of contact, to the PCB, of the molten solder cascading off of the tip of the selective soldering machine’s nozzle. A variety of different nozzles can be used, with the largest nozzle (that will fit) being the optimal choice. Available nozzle sizes are #6, #8, #10, & #12. The number directly correlates to the contact diameter expressed in millimeters. The default nozzles used are #6 & #8 so 6mm – 8mm contact diameter is preferred. From a design perspective, there needs to be at least a 6mm clearance path (#6 nozzle), for the nozzle to solder, without disturbing adjoining components. 6mm to 8mm is preferred. This clearance path is concentric to the solder joint, by default meaning there is a minimum 3mm clearance required all the way around a solder joint’s center point.9) EMI SHIELDING Refer to Laird Technologies EMI shielding calculator10) AUTOMATED DIP INSERTION SPECIFICATIONSMinimum side to side clearance .150”Minimum end to end clearance .150”11) AUTOMATED AXIAL INSERTION SPECIFICATIONS? and 1/8 watt resistors:Side to side is .100”Lead to lead is .100”Left lead to right lead .400” ? watt resistors:Side to side is .150”Lead to lead is .150”Left lead to right lead .500”12) CONFORMAL COATING / POTTINGConformal Coating or Parylene Coating can help protect the assemblyPotting is used in conjunction with an enclosure to encapsulate the assemblySuggested conformal coating: Acrylic – Humiseal 1B31 Silicone – Humiseal 1C53 Urethane – Humiseal 1A20Suggested potting:Henkel 2009004 w/2011992 hardenerDow Corning 7091 Black13) PCBA TESTABILITYTest points should be available for every net (node) on the board.All test points should be accessible from the ‘solder’ side of board whenever possible. If this is not feasible the component side may be probed, but not recommended.Dedicated test pads are preferred.Test points may consist of through-hole components leads, or dedicated test pads. Vias may be used as test points for in-circuit test (ICT) but for flying-probe it is very difficult due to the test pin being smaller than the via and may not make contact.ICT test points should be a minimum of 35 mil. diameter, and spaced at 50 mil. intervals minimum. The preferred size is 40 mil. with at least 100-mil spacing whenever possible.Flying-Probe minimum test pads should be minimum of 15 mil diameter with no holes or openings in the pad and a minimum of 120 mil from the edge of the board.For ICT, test points should be at least 200mils from the edge of the board for better board gasketing, or an absolute minimum of 100 mils.Test point vias shall NOT be filled with solder mask. Do NOT mask over the test point area to be probed by the tester.If using vias for test points in a board design, define 2 types of vias: one being a larger size for test points.Extra ground and power (VCC, VDD) test points should be accessible, 4 each per ampere consumed by the circuit. A minimum of two each is required, regardless of the amount of current. Power and ground points should be spaced evenly across the board whenever possible.Any and all digital Chip Select and Enable lines if not controlled by other component outputs should be tied to ground or VCC (VDD) by a pull-down or pull-up resistor, not tied directly to the supply. 330 ohms is a good value for a pull-down and 1k to 10 k for pull-ups.Materials required for test program development:Current rev. bare board.Current rev. known good loaded boardFabrication drawing Assembly drawingsSchematic drawingB.O.M for list – see lists – Whenever possible, netlists should include all of the following information:net (node) namecomponent descriptionpin descriptionx-y location of component pinx-y location of test points (via or pad)Where placed (top or bottom)SMT or Through- Hole components14) ASSEMBLY DRAWING A separate drawing for the complete assembly should be developed that includes: Dimensional or exploded view(s) with balloons to associated with BOM(s)Programmed Device information Listing of jigs or fixtures required for assemblyWorkmanship Standard & Acceptability criteriaLead protrusion / component height specification if requiredConformal coating requirements with clearly marked keep out areasWire routing and adhesion requirementsMethod of identification, serialization, or labelingTest requirement(s)Packaging specifications if applicableTorque specification for all fasteners, ADCO can assist if needed ................
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