LAN8720A RMII PHY Customer Evaluation Board Schematic - SMSC

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LAN8720A RMII PHY Customer Evaluation Board

D

Design Details

Board: Assy 6584

Chip: SMSC LAN8720A

Board Form Factor: MII Add-On Card

Assembly:

C

24 Lead QFN w/ Exposed GND Pad

Revision History

Rev 1.0:

Initial release, Rev C

Rev 1.1:

U3 (page 2) - Changed from

74LVC1G07 to 74LVC1G17

B

in rework prior to release of

all Revision C boards.

"Configuration Resistor Settings" (Pg. 03): Created new table.

Configuration Resistor Settings" table, (Pg. 03): Correction to signal name within table from "nINT/TXEN/TXD4" to "nINT/REFCLKO Signal".

Added text to signal "nINT" pull-up jumper.

Rev 1.2:

All Pages - Changed from LAN8720 to LAN8720A

Rev 1.3:

A

C19 changed from 0.1uF

to 470pF.

Assy 6584

PCB Revision C Schematic Revision 1.3

BLOCK DIAGRAM

D

Circuit Diagrams utilizing SMSC Products Are

Included As A Means Of Illustrating Typical

Semiconductor Applications: Consequently

Complete Information Sufficient For Construction

Purposes Is Not Necessarily Given. The Information

Has Been Carefully Checked And Is Believed To Be

Entirely Reliable. However, No Responsibility Is

C

Assumed For Inaccuracies. Furthermore, Such

Information Does Not Convey To The Purchaser Of

The Semiconductor Devices Described Any License

Under The Patent Rights Of SMSC Or Others. SMSC

Reserves The Right To Make Changes At Any Time In

Order To Improve Design And Supply The Best

Product Possible.

ITEM

Title Page LAN8720A / RMII / Magnetics Configuration Settings

Page(s)

1 2 3

B

A

Title

LAN8720A RMII PHY Customer Evaluation Board

Size Engineer

Assembly No. PCB Rev Schematic Rev

R. W.

6584

C

1.3

Date:

Tuesday, May 18, 2010

Sheet 1 of 3

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LAN8720A / Magnetics / RMII Connector

+5V

+3.3V

TP2 Test Point - Red

+5V D

+5V

RMII +5V decoupling capacitors to be placed near RMII connector

C1 1.0uF 16V 10%

VR1 1 Vin

OUT 5

2 GND

3 ON/OFFBYPS 4

LP2992IM5-3.3 SOT23-5

C4 0.01uF 50V 10%

C2 4.7uF 6.3V 10%

C18 0.1uF 16V 10%

TP1 Test Point - Orange

+3.3V

TP5 Test Point - Purple

VDDIO

C16 0.1uF 16V 10%

+ C17 10uF

- 25V 10%

VDDIO

3

FB1 2.0A/0.050 DCR

AVDD

C5

C6

C3

0.1uF

0.1uF

4.7uF

16V

16V

6.3V

R12

10%

10%

10%

0

VDDCR

+3.3V

VDDIO

+5V

R11 1.50K 1/10W 1%

C7 0.1uF 16V 10%

VDDCR 6

1 19

VDD2A VDD1A

VDDIO 9

J1

1

2

nRST

3

4

MDC

5

6 MDIO

R_RXD1

7

8 R_RXD0

R_RXER

9

10 R_RXCLK

nINT

11

12 TXCLK

TXEN

13

14

TXD0

15

16

TXD1

17

18

C

R_CRS

19

20

HEADER_2x10 RMII Signal Test Point Header

P1

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

+5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND +5V

5173278-2

+5V MDIO MDC RXD3 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER TX_ER TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3

COL CRS +5V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

MDIO MDC

R_RXD1 R_RXD0 R_RXDV R_RXCLK R_RXER

TXCLK TXEN TXD0 TXD1

R_CRS

R3

100

R4

100

R5

100

R7

100

R10

100

DNP

MDIO MDC

RXD1/MODE1 RXD0/MODE0 nINT/REFCLKO RXER/PHYAD0

TXEN TXD0 TXD1

CRS_DV/MODE2

nRST XTAL1/CLKIN XTAL2

12 13

MDIO MDC

7 8

RXD1/MODE1 RXD0/MODE0

14 10

nINT/REFCLKO RXER/PHYAD0

16 17 18

TXEN TXD0 TXD1

U1 LAN8720A

TXP T2X1P TXN 20 TXN

RXP 23 RXP RXN 22 RXN

11 CRS_DV/MODE2

15 nRST 5 XTAL1/CLKIN 4 XTAL2

LED1/REGOFF LED2/nINTSEL

3 2

LED1/REGOFF LED2/nINTSEL

RBIAS 24 RBIAS

25 GND_EP

Reset Generator

QFN24_4X4MM_EP2P5MM

R22 12.1K 1/10W 1%

+3.3V

VDDIO

R44

U4

4.75K

VTH = 2.63V

1%

R51

Treset = 20 mS

4 VCC RESET 2

nRST

S1

10.0K

B SPST_MOM

3 MR

C15 0.1uF 10V 10%

MIC6315-26D2UY SOT-143_BIG1

50MHz TX Clock Signal Input (if provided on TXCLK by RMII MAC)

TXCLK

TXCLK

R49

0 XTAL1/CLKIN

DNP

2

1

VDDCR Decoupling Capacitors

R13 49.9 1/10W 1%

R14 49.9 1/10W 1%

R15 49.9 1/10W 1%

R16 49.9 1/10W 1%

VDDCR

Note:

Place 0 Ohm resistor close

to magnetics module .

R17

0

Place 49.9 Ohm resistors

close to LAN8720A.

TP3 Test Point - Green VDDCR

DNP

C19

C20

C21

D

470pF

1.0uF

4.7uF

Note:

50V

16V

6.3V

C19& C20 decoupling

5%

10%

10%

capacitors for VDDCR

DNP

should be placed as

close to LAN8720A

as possible.

C21 is for internal use

only.

LED1_CATHODE LED1_ANODE

T1 Pulse J0011D01BNL

C 10 A9

C8 0.022uF 50V 10%

1 TD+ 4 TXCT 2 TD-

XMIT

3 RD+ 5 RXCT 6 RD-

7 NC 8 CHS GND

RCV

75

75 1000 pF

GRN

RJ45

1 75

4 & 5

2

LED1 (Green) = LINK/ACT

LED2 (Yellow) = SPEED

C

3 75

7 & 8

6

2 kV

YEL

13 GND 14 GND 15 MTG 16 MTG 11 C 12 A

C9 10pF 50V 5% DNP

C10 10pF 50V 5% DNP

C11 10pF 50V 5% DNP

C12 10pF 50V 5% DNP

LED2_ANODE LED2_CATHODE

Note: Capacitors C9 through C12 are optional for EMI purposes and are not populated on the LAN8720A evaluation board. These capacitors are required for operation in an EMI constrained environment.

VDDIO

nINT

B

R25 4.75K

nINT

R50

0 nINT/REFCLKO

DNP

1 GND 3

RMII Clock Source Selection Jumpers

CLKIN

R45 XTAL1/CLKIN 2

0

1 XTAL1 3 EXTCLK50

3-Pad Resistor Default Population Settings: 1--2

REFCLKO

+3.3V

R_RXCLK

R46

1 nINT/REFCLKO

2

3 EXTCLK50

XTAL2

R21

1.00M

DNP

0

R20

Note:

10.0

R47

U3 must be depopulated when

1/10W

A

4.75K

DNP

sourcing a 50MHz external (offboard) VDDIO

1%

clock via the R_RXCLK pin.

Y1

U2

2

1

1 EN VCC 4

U3

R48 4.75K

2 GND OUT 3 50.000MHz

1 CLK50 2

3

NC IN GND

VCC 5 OUT 4

25.000MHz HC49US

C22 0.1uF 10V 10%

74LVC1G17

C23 0.1uF 10V 10%

C13 30pF 50V 5%

C14 30pF 50V 5%

5

4

REGOFF & INTSEL Configuration Resistors

AVDD

REGOFF

LED1/REGOFF 1

R40

2

3

0

R41 1

2 LED1/REGOFF 3

330

LED1_ANODE

R38 4.75K 1/10W LED1_CATHODE

AVDD

3-Pad Resistor Default Population Settings: 1--2

nINTSEL

LED2/nINTSEL 1

R42

3 0

1 LED2/nINTSEL 3

R43 330

2 LED2_ANODE

R39 4.75K 1/10W 2 LED2_CATHODE

3

PHY Address / nINT Strap / Mode Select Resistors

VDDIO

PHYADD0

MODE2

MODE1

MODE0

R24 4.75K 1/10W 1%

DNP

R28

4.75K 1/10W 1%

R29 4.75K 1/10W 1%

R30 4.75K 1/10W 1%

RXD0/MODE0 RXD1/MODE1 CRS_DV/MODE2 RXER/PHYAD0

R37 4.75K 1/10W 1%

R33 4.75K 1/10W 1% DNP

R32 4.75K 1/10W 1% DNP

R31 4.75K 1/10W 1% DNP

2

R23

0

1210

TP4 Test Point - Black GND

MTG1 1 NC

3 Plated Hole w_GND

MTG2 1 NC

3 Plated Hole w_GND A

Title Size Date:

LAN8720A / Magnetics / (R)MII Connector

Engineer

Assembly No.

R. W.

6584

Thursday, January 06, 2011 1

PCB Rev

C

Sheet

Schematic Rev

1.3

2 of 3

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Configuration Settings

D

D

Configuration Settings

SIGNAL

POPULATE

DEPOPULATE

COMMENTS

PHYAD[0] = 0

R37

R24

Default

PHYAD[0] = 1

R24

R37

MODE[0] = 0 MODE[1] = 0 MODE[2] = 0

R31

R30

R32

R29

R33

R28

C

MODE[0] = 1

R30

R31

Default

C

MODE[1] = 1

R29

R32

Default

MODE[2] = 1

R28

R33

Default

Internal 1.2V Reg. Enabled Internal 1.2V Reg. Disabled

R40 & R41: 1-2 R40 & R41: 2-3

R40 & R41: 2-3 R40 & R41: 1-2

Default

Interrupt Function Enabled on nINT/TXER/TXD4 Signal

Interrupt Function Disabled on nINT/TXER/TXD4 Signal

R50, R42 & R43: 2-3

R42 & R43: 1-2

R42 & R43: 1-2

R50, R42 & R43: 2-3

Default

25.000MHz Crystal Clock Source Enabled

R20, R48, R45 & R46: 1-2

R47, R49 R45 & R46: 2-3

Default

Interrupt Function must be disabled in this configuration.

25MHz Crystal Clock Source Disabled, with Offboard 50MHz Clock Source Provided on TXCLK

R48, R49

R20, R47, R45 & R46: 1-2 R45 & R46: 2-3

Interrupt Function must be enabled in this configuration.

25MHz Crystal Clock Source Disabled, with

R48,

U3, R20, R47, R49

Interrupt Function must be enabled in this configuration.

Offboard 50MHz Clock Source Provided on

R45 & R46: 2-3

R45 & R46: 1-2

RXCLK

B

B

25MHz Crystal Clock Source Disabled, with Onboard 50MHz Clock Source Provided on RXCLK

U3, R47, R45 & R46: 2-3

R20, R48, R49 R45 & R46: 1-2

Interrupt Function must be enabled in this configuration.

25MHz Crystal Clock Source Disabled, with Onboard 50MHz Clock Source Provided on RXCLK via REFCLK0

U3, R47, R45: 2-3 R46: 1-2

R20, R48, R49 R45: 1-2 R46: 2-3

Interrupt Function must be disabled in this configuration.

A

A

Title

Configuration Settings

Size Engineer

Assembly No. PCB Rev Schematic Rev

R. W.

6584

C

1.3

Date:

Tuesday, May 18, 2010

Sheet 3 of 3

5

4

3

2

1

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