IEEE-1394 Data Link



IEEE-1394 Data Link

Final Design Report

ECE4040

Dr. Martin Brooke

November 28, 2000

Sherry Womack

Erik Pace

Introduction

The objective of this project is to create a high speed data connection between a camera and a PC. The camera will be placed on a toy car, and communication between the camera and PC will be via an RF link. In Figure 1 the link between the camera and PC is illustrated.

Figure 1. Communications link between camera and PC.

To reach high speeds of data transmission, IEEE 1394 cable will be used, and thus an interface for the cable needs to be designed. Another group has been developing the RF link, while our group has focused on the interface.

What is IEEE 1394?

As the world moves towards a state of greater connectivity through various networks, people will need to find ways to share their data no matter what form in may be in. One area of interest is that of sharing video and still images. It is important that the form of transfer is fast, easy, inexpensive, and involves no image degradation. The IEEE 1394 multimedia connection enables simple, low-cost, high-bandwidth isochronous (real-time) or asynchronous data interfacing between computers, peripherals, and consumer electronics products such as camcorders, VCRs, printers, PCs, TVs, and digital cameras. Using IEEE 1394-compatible products, users can achieve all of the goals listed above.

1394 was adopted as an industry standard by the Institute of Electrical and Electronics Engineers Standards Board and given the official name IEEE 1394-1995 Standard for a High Performance Serial Bus. The 1394 Trade Association was formed in 1994 to increase the use of the standard by industry electronics manufacturers. The IEEE-1394 standard was dubbed the Multimedia Connection by the 1394 Trade Association.

There are many significant advantages of the 1394 standard over the other current and proposed serial buses. These advantages include:

• Versatility: IEEE-1394 provides a direct digital link between up to 63 devices without the need for additional hardware, such as hubs. Digital Video (DV) camcorders, scanners, printers, videoconferencing cameras, and fixed-disk drives all share a common bus connection not only to an optional PC, but to each other as well. IEEE-1394 is a candidate for the "Home Network" standard initiated by VESA (Video Electronic Standards Association) and other industry associations.

• High speed: The present implementation of IEEE-1394 delivers 100 Mbps (Megabits per second), 200 Mbps, or 400 Mbps of data (payload) and control signals (overhead). Future versions that support 1.2 Gbps are in the development stage. All of these speeds are supported on a single continuous cable making IEEE-1394 scalable. Isochronous data transmission lets even the lowest-speed implementation support two simultaneous channels of full-motion (30-frame-per-second), "broadcast quality" video and CD-grade stereo audio. Full-frame digital video contains an immense amount of information and it requires a constant frame rate (usually 30 frames per second) to provide a high quality image. IEEE-1394’s transfer rates are more than enough to handle the digital video frame rates.

• Low cost: The cost of the integrated circuits and connectors to implement IEEE-1394 is often less than the cost of the connectors and circuitry it replaces. 1394 uses a flexible, six-conductor cable and connectors derived from Nintendo's Gameboy to interconnect devices. (A four-conductor version of the standard cable is used to interconnect consumer audio/video components.) Use of IEEE-1394 for consumer electronics gear, such as camcorders and VCRs, will provide the high-volume market needed to achieve low-cost implementation of IEEE-1394 on PCI adapter cards and PC motherboards.

• Ease of installation and use: IEEE-1394 extends Plug and Play features far beyond the confines of the personal computer. When you add a new device, 1394 automatically recognizes the device; similarly, on disconnect 1394 automatically reconfigures itself. The standard 1394 cable provides up to 1.5 amps of DC power to keep remote devices "alive" even when they're powered down. You don't need a computer to take advantage of IEEE-1394; as an example, a VCR can act as a 1394 controller for camcorders, TV sets, receiver/amplifiers, and other home theater components.

How IEEE 1394 Works

The IEEE-1394 High Performance Serial Bus is a remarkable feat of engineering that has occupied many highly-creative digital circuit designers and software programmers for the past 10 years. IEEE-1394 is a very complex serial bus protocol, as evidenced by the hundreds of pages that comprise its standard specification. The following list is a very simplified description of the external and internal workings of the IEEE-1394 bus:

Standard cables and connectors replace the myriad of I/O connectors employed by consumer electronics equipment and PCs. IEEE-1394 multiplexes a variety of different types of digital signals, such as compressed video, digitized audio, MIDI, and device control commands, on two twisted-pair conductors. Multiplexing is used in virtually all analog and digital networking systems, but usually only a single type of signal is involved. As an example, Ethernet multiplexes digital data streams from workstations and servers over one (10Base2, "Thin" Ethernet) or two (10BaseT, 100BaseT) pairs of conductors. (1394 cabling is quite similar to that of 10BaseT Ethernet.) Sending real-time, high-quality audio and video data over Ethernet, however, requires special protocols presently implemented only by proprietary multimedia networking systems. IEEE-1394 is much more flexible in its accommodation of different data types and topologies than alternative networking systems. IEEE-1394 uses a "fairness" arbitration approach to assure that all nodes having information to transmit get a chance to use the bus; standard Ethernet does not provide this type of arbitration.

Special integrated circuit chips implement the IEEE-1394 protocol. Like Ethernet and other high-speed digital data transmission systems, 1394 is a layered transport system. The IEEE-1394 standard defines three layers: Physical, Link, and Transaction (see Figure 2). The Physical layer provides the signals required by

Figure 2. The 1394 Protocol Stack and Serial Bus Management Controller.

the 1394 bus as well as the initialization and arbitration services necessary to assure that only one node at a time is sending data and to translate the serial bus data stream and signal levels to those required by the link layer. The Link layer handles all packet transmission and reception responsibilities, plus the provision of cycle control for isochronous channels. The Link layer also supplies an

acknowledged datagram to the transaction layer. The Transaction layer takes the packets from the Link layer and presents them to the application. Link chips provide all link functions as well as a limited number of transaction functions. The remainder of the transaction functions are performed in software.

As shown in Figure 3, the standard 1394 cable actually consists of six wires. Data is sent via two separately-shielded twisted pair transmission lines. The two twisted pairs are crossed in each cable assembly to create a transmit-receive connection. Two more wires carry power (8 to 40V, 1.5A max.) to remote devices. Currently, these power lines are rarely used. The wires terminate in gameboy-style plugs, also shown in the figure.

Figure 3. IEEE-1394 Cable Design.

Design of Previous Group

The previous group who worked on this project concluded that two interfaces should be used to link the camera to the PC. Each interface would have a physical layer and a link layer. The physical layer carries out the arbitration, data resynchronization, bus initialization, and it also controls the encoding and decoding, the signal levels, and the connectors and media. The link layer is responsible for packet transmission, packet receiving, and for cycle control. Their design is illustrated in Figure 4.

Figure 4. Previous group’s design for IEEE 1394 RF link.

The chip for the physical layer was Texas Instruments TSB41LV03A IEEE 1394a Three-Port Cable Transceiver/Arbiter. It provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission.

The chip chosen for the Link layer was TSB12LV42 (DVLynx) IEEE 1394-1995 Link-Layer Controller for Digital Video, which is also made by Texas Instruments. It is a 1394 interface for high-speed audio, video, and data applications at up to 200 Mb/s. On the TSB12LV42 a bulky data interface (BDIF) is implemented that supports long term data rates up to 60 Mb/s. Burst data rates, however, can go up to 160 Mb/s. The TSB12LV42 contains two FIFOs that are a 256-byte control FIFO (Control FIFO) and an 8K-byte BDIF FIFO. These two FIFOs are further subdivided into smaller logical FIFOs. Bulky data is usually buffered in the BDIF FIFO. The BDIF FIFO supports DV, asynchronous, and isochronous formatted traffic for receive and transmit. Based on destination address, received asynchronous request packets may be steered into either the Control FIFO or the BDIF FIFO.

The interfaces were to be laid out according to the schematics provided by Texas Instruments. The connections between the layers are shown in Figure 5.

Figure 5. Physical and Link layer connections.

Cable connections and power decoupling networks were found in the TSB41LV03A/ TSB12L42A Reference Schematic provided by Texas Instruments. This schematic is shown in Figure 6.

Figure 6. Cable connections and power decoupling network.

The PC Board Layout created by the previous group is shown in Figure 7. It contains the Physical and Link layers, but omits the connections to the processor and cable.

Figure 7. PC Board Layout for previous design.

There were several problems found with the previous group’s design. The layout did not include a power decoupling network, and the physical positioning of the chips on the PC Board layout needed to be adjusted to account for high frequency transmission line effects. Also the etch lengths of the TPA+, TPA-, TPB+, and TPB- lines connecting the physical layer to the cable were not equal, and this is important for insuring that data transmission is synchronous with the clock. The parts list provided by the previous group for the PC Board contains several parts that were unavailable and listed with incorrect values. In the schematics supplied by Texas Instruments, microprocessors were connected to the link layer. This was an area of the design that the group had not addressed, and later turned out to be an important challenge faced when developing the new design.

Proposed New Designs

The first design attempted this semester involved finishing the work of the previous group. The decoupling network was added to the existing layout, and the etch lengths were adjusted where necessary. The new layout created in SuperPCB is shown in Figure 8.

Figure 8. First new design showing the physical to link layer layout.

The backplane for this layout was also created, and it is shown in Figure 9.

Figure 9. Backplane layout for first design.

The parts necessary to build the board laid out by Texas Instruments in the schematics shown earlier were purchased. The vendors used were DigiKey, Linear Technology, Mouser, National Semiconductor, ON Semiconductor, and Texas Instruments.

Problems arose when the group realized that a microprocessor or microcontroller was necessary to control the link layer. After coming to this conclusion, the group decided to try using a PC to handle the processing for this test board. The group then chose to explore the possibility of eliminating the link layers on the boards altogether.

Thus, the second design significantly departed from the previous group’s design in that the link layer was eliminated from the design. Since the link layer chip was created for handling arbitration of data between two devices, this arbitration was unnecessary because the system only required a one way connection. One concern related with this design is the question of the initialization state. Will the PC try to ask the camera if it is connected to the PC? Will the camera have to respond? If the camera must respond, then the connection between the camera and PC must be bi-directional. The group decided to set up two physical layer chips and connect their data outputs together to see if they would be able to communicate successfully. Because one of the physical layer chips was connected to an identical chip, a network of zero ohm resistors was included in the design to keep the wires from touching as they crossed over each other. This layout is shown in Figure 10.

Figure 10. Physical layer to physical layer layout with zero ohm resistor network.

This layout showing the zero ohm resistor network was flawed because the connections between the data lines were all different lengths. To solve this problem the group proposed that instead of using a zero ohm network, each physical layer chip should be placed on opposite sides of the board. By having one physical layer chip on the top and the other inverted one the bottom, the pins would be able to be matched with short etch lengths.

The top layout of the physical to physical layer design is shown in Figure 11. The power and ground connections are also shown in this figure.

Figure 11. Top view of the physical layer to physical layer layout.

The bottom layout of the physical-to-physical layer is shown in Figure 12.

Figure 12. Bottom view of physical layer to physical layer layout.

The layout design was altered for easier fabrication. The chips were placed on the same layout, but the physical layer chips will still be on opposite ends of the board. The new layout is shown in Figure 13. The IEEE 1394 cable connectors are located on the

left and right of the schematic.

Figure 13. Revised layout of the physical layer to physical layer design.

Final Design

As stated previously in this report the physical-to-link layer connection seems superfluous to the application that is being implemented here. Instead, it was decided to modify the physical-to-link connection into a physical-to-physical connection. The physical layer chip is designed to connect with a link layer chip so there was a question of how the physical chip would react when being connected with another physical chip directly through the data lines.

When the physical chip wants to send data out through the data lines (called Receive) it takes control of the data bus and sends the data according the description that follows. Whenever the physical chip detects that data needs to be sent out on the data lines, it initiates a receive operation by asserting Receive on the control terminals (see Table I) and a logic 1 on each of the D terminals. The speed code is then sent out along the data lines as shown in Table II for one cycle immediately preceding packet data. The link decodes the speed-code on the first Receive cycle for which the D lines are not the data-on code. If the speed-code is invalid, or indicates a speed higher than that which the link is capable of handling, the link should ignore the subsequent data. Following the data-on indication and the speed-code, the PHY (physical layer chip) asserts packet data on the D lines with receive on the CTL (control) lines for the remainder of the receive operation. The PHY terminates the receive operation by asserting Idle on the CTL lines.

Table I

CTL Encoding When PHY Has Control of the Bus

|CTL0 |CTL1 |Name |Description |

|0 |0 |Idle |No activity (default) |

|0 |1 |Status |Status information is being sent out from the PHY |

|1 |0 |Receive |An incoming packet is being sent out from the PHY |

|1 |1 |Grant |The PHY gives control of the bus to the LLC to send an outgoing packet |

Table II

Receive Speed Codes

|D0-D7 |Data Rate |

|00XX XXXX |S100 |

|0100 XXXX |S200 |

|0101 0000 |S400 |

|1YYY YYYY |"data-on" indication |

For the proposed PHY-to-PHY interface, the physical layer devices do not have a problem with sending out data on the data lines. The procedure above is followed in the same way as it was for the PHY-to-Link interface. The problem with the proposed solution comes when the physical layer receives data on the data lines. Since the physical layer was designed to work with a link layer chip it expects certain information from the LLC (link layer controller) when it receives data on the data terminals. Below is a description of what happens when the physical layer received data on the data lines (called a Transmit).

First, the LLC issues a bus request through the LREQ (link request) terminal as shown in Table III using an 8-bit stream of data. Then the PHY asserts grant on the CTL lines (see Table I) followed by Idle to hand over control of the interface to the link so that the link may transmit a packet. The PHY then releases control of the interface. The link may assert at most one idle cycle preceding assertion of either hold or transmit (see Table VI). This idle cycle is optional. The link is not required to assert Idle preceding either hold or transmit. The link may then assert Hold for up to 47 cycles preceding assertion of transmit. These hold cycles are optional. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the data on the D lines. The transmit operation is terminated by the link asserting Hold or Idle on the CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to transmit a concatenated packet. The link asserts Idle to indicate that packet transmission is complete and the PHY may release the serial bus. The link then asserts Idle for one more cycle following this cycle of Hold or Idle before releasing the interface and returning control to the PHY. After regaining control of the interface, the PHY shall assert at least one cycle of Idle before any subsequent status transfer, receive operation, or transmit operation.

Table III

Bus Request

|BIT(s) |Name |Description |

|0 |Start Bit |Indicates the beginning of the transfer (always 1). |

|1-3 |Request Type |Indicates the type of bus request. See Table IV. |

|4-6 |Request Speed |Indicates the speed at which the PHY will send the data for this request. See Table V. |

|7 |Stop Bit |Indicates the end of the transfer (always 0). |

Table IV

Request Type Encoding

|LR1-LR3 |Name |Description |

|000 |ImmReq |Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately |

| | |without arbitration. |

|001 |IsoReq |Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting|

| | |for a subaction gap. |

|010 |PriReq |Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair |

| | |protocol. |

|011 |FairReq |Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair |

| | |protocol. |

|100 |RdReq |The PHY returns the specified register contents through a status transfer. |

|101 |WrReq |Write to the specified register. |

|110 |AccelCtl |Enable or disable asynchronous arbitration acceleration. |

|111 |Reserved |Reserved. |

Table V

Bus Request Speed Encoding

|LR4-LR5 |Data Rate |

|000 |S100 |

|010 |S200 |

|100 |S400 |

|All Others |Invalid |

Table VI

CTL Encoding When LLC Has Control of the Bus

|CTL0 |CTL1 |Name |Description |

|0 |0 |Idle |The LLC releases the bus (transmission completed) |

|0 |1 |Hold |The LLC is holding the bus while data is being prepared for transmission, or indicating |

| | | |that another packet is to be transmitted without arbitrating |

|1 |0 |Transmit |An outgoing packet is being sent from the LLC to the PHY |

|1 |1 |Reserved |None |

When trying to connect PHY to PHY some modifications to the above process had to be made. By comparing Table I and Table VI one can see that the CTL lines have the same it assignments for both Receive and Transmit no matter which chip has control of the bus. The problem is getting one PHY to grant control of the bus to the other. Usually this is done using the LREQ terminal on the PHY, but in the new case there is no LLC to generate and send an LREQ stream. Without this LREQ the PHY never assert Grant on the control lines in order to give control of the bus to the other PHY. Without one PHY granting control of the bus to the other both physical chip will think they have control of the bus. Assuming that the control lines of both chips are connected together, if one chip tried to assert Receive without first having the other chip assert Grant, then both chips will believe that they have control of the bus and are trying to send out data on the D lines. In this case the data will be lost.

To combat this problem a Parallel-In-Serial-Out shift register is used to generate the LREQ signal. The data lines are connected together. Also the control lines are connected together through 10-100 kilo-Ohm resistors. The shift register is set up to constantly output a data stream following the constraints of Table III. This request will seek a fair bus request and a data rate of S400. The PHY can only process one request at a time and all subsequent requests are lost. The SYSCLK terminal of the PHY is used to synchronize the LREQ data stream output by the shift register. After an idle by the PHY that is being used as the receiver of data, the PHY will process the bus request. The shift register keeps generating the request stream, but since the PHY is already processing a request this stream is ignored. Once the request is completed the LREQ terminal will sense another request and prepare for reception of data again.

Once the PHY receives the LREQ stream it asserts Grant on the control lines. Because of the resistors between the CTL lines of both chips, the data-sending PHY does not see the Grant assertion and is not affected by it. The data-receiving PHY (PHY-R) is now ready to receive commands from the data-sending PHY (PHY-T). PHY-T then asserts Receive on its CTL lines and PHY-R views this as an assertion of Transmit as can be seen by comparing Tables I and VI. PHY-T now sends data to PHY-R. When the transmission is complete PHY-T will assert Idle on the CTL lines and both chips will idle. At this time PHY-R will sense another link request on its LREQ terminal and await another transmission from PHY-T.

While this set-up is unidirectional in data flow, it is much simpler than the design involving the LLC. Further investigation into this arrangement will probably reveal a solution that will enable a bi-directional flow of data. Perhaps there is a way to connect the shift register to both PHY chips in order for both to be capable of data reception.

The layout for the final design is located in Figure 14.

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Figure 14. Layout of the final physical-to-physical layer design.

Summary of Status

The layout needs to be checked to make sure it is in accordance with the Georgia Tech fabrication guidelines. There is the issue of spacing between etches that needs to addressed. The minimum preferred separation of etches is 15 mils. In certain areas of the board the separation goes below this guideline and causes fabrication difficulties. After these changes are made, the board needs to be fabricated and populated using the purchased components. The board also needs to be tested to insure that the correct data output is being given by this design. Testing can be done by placing a signal on the data lines of the physical chip on the left of the board, connecting the 1394 cable from the chip on the left to the chip on the right, and monitoring the data lines from the physical chip on the right. The same signal should appear on the input and on the data lines between physical chips. If this test is passed, then the data and control lines can be connected together using jumper wire on the board. Then the signal from the camera can be input using the 1394 cable on the chip on the right, and the data from the chip on the left can be sent through 1394 cable to the PC. Finally, after this test is successfully completed, a new design should be created for two boards. Each board should have data lines that are sent to the RF link. These two new boards will then act like the single board, but the jumper wires will be replaced with an RF link.

Web Site References

I. Organizations

A.

B.

II. 1394 Chip Manufacturers

A. firewire

B. sc/docs/msp/1394/1394.htm

III. Technical Papers

A.

B.

C.

D.

E.

F.

G.

H.

I.

J.

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The idea for the 1394 connection was first conceived in 1986 by developers at Apple Computer. They chose to name the technology FireWire in reference to its speeds of operation. Eventually in 1995,

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