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Verilog Startup
This will give you the basics on starting your Verilog Project. This is just a brief list of commands that you may use, but it should be enough to get you started. I tried to make sure everything is accurate, if you find any errors, please let me know and I will fix it immediately.
-Henry
Inserting Text
/***********************
*This is how your can
*type comments
*and insert blank test
***********************/
//You can also insert text like this
Creating Modules
module test_mod;
// insert Verilog Code here
endmodule
Creating Wire(s)
Wire NameofWire;
Wire [3:0] ManyWires; // 3 is MSB
Defining Modules
//Creating a generic module
module generic_module(in1, in2, out1);
input [3:0] in1;
input in2;
output out1;
endmodule
// Defining a specific module
module test_mod;
wire [3:0] blink;
wire smile;
wire nod;
generic_module plesant_module(blink, smile, nod);
endmodule
Creating Registers
reg clk;
reg [2:0] KeyPosition;
Defining Parameters
parameter period = 1;
parameter Key_0 = ‘b000;
Creating Clocks
//this will set a clock high and low at each period I have defined
//note with always, you can add conditionals, ie. always @ (negedge clk)
always
begin
//I have defined period from in my parameters
//clk is a register that I created above
// # lets you create delay
// #(num_units_of_time)
#(period) clk = 0;
#(period) clk = ~clk;
end
Displaying Waveforms
// use this to display waveforms to WAVES window
initial
begin
$gr_waves(“labelofyourvariable”, clk, “StatePosition”, StatePosition);
// wait for 100 * periods
#(100*period);
//$stop is used to create breakpoints within a simulation, if you don’t have // one, then verilog will exit right after the end of simulation w/o pausing
// if you want to continue after the stop, type “.” and enter at the prompt to // continue with the simulation
$stop;
$finish;
end
//to look at wires/registers inside a module, the module name is attached to the //beginning of the wire with a period separating them.
initial
begin
$gr_waves(“module.insidewire”, alu.reg_clk);
$stop;
end
Printing Waves Window to a Postscript File
// This command can be entered into the code or in the verilog interactive mode.
$ps_waves(“filename.ps”, “headername”);
Conditionals and Cases
//very useful for your project.
if(Restart)
begin
State_Position=S_0;
end
else
begin
State_Position=Next_State;
end
//Cases
always @(posedge clk)
case(State_Position)
S_0: begin
If(Key==Key1)
Next_State=S_1;
Else
Next_State=S_0;
end
endcase
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