Op Amps - Baylor ECS



The objective of this circuit is to lock oscillator Vpulse frequency and phase angle with wall outlet Va.. Wall outlets are nominally 60 Hz, but their frequency varies nervously around 60 Hz as generator governors keep grid generation in balance with load. Sometimes the variation is as much as 0.3 Hz. For most of the time the variation is within ± 0.05 Hz.

Vpulse from this circuit is a square wave with 50% duty cycle and adjustable frequency. For the moment, let Vb represent the fundamental frequency component of Vpulse. Recall the product of cosine and sine trig identity

Unfortunately, the above function is not zero when [pic]. To obtain the desired zero property, it is necessary to integrate [pic] and use the sine • cosine trig identify which, when the frequencies of [pic] and [pic] are equal, has positive or negative error depending on phase angle error. Thus, for the phase locked loop we will use

To understand how phase locking works, consider the case where [pic]. Let angle A be reference zero, and consider the situation where B = 0. Filter out the double-frequency term. The sine • cosine function is then zero. But as [pic] drops very slightly and B moves negative, the sine of (-B) goes positive. If the feedback mechanism is set up so that positive angle error increases [pic] slightly, then B will advance back toward zero.

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[pic]

[pic]

MOSFET used as voltage-controlled resistor

Resistance seen at waveform generator RF pin ranges between 150k© and (150+220)k©. Raising voltage VGS reduces RDS, thereby raising pulse frequency. VGS H" 1.5 V yields 60 Hz when CF = 00kΩ and (150+220)kΩ. Raising voltage VGS reduces RDS, thereby raising pulse frequency. VGS ≈ 1.5 V yields 60 Hz when CF = 0.1μF. The frequency range for the given R’s and CF is about 30 to 80 Hz

Waveform Gen.

RF pin

C

Vpulse (no DC)

4.7μF

+

1MΩ

R

0 to 12V, 50% duty cycle

0.00147 > RiC > 0.00047

680 < Ki < 2128

Summer

10kΩ

10kΩ

10kΩ

R

R

–

+

Verr

–

+

-Ki• Intg(Verr)

-Kp•Verr

B100kΩ

22kΩ

1MΩ

0.01μF

47kΩ

R

C

Rc

–

+

Ki• Intg(Va)

–

+

Rc

C

x•y /10

1MΩ

0.1μF

47kΩ

Vpulse

DC blocking filter. RC = 4.7s

Integrator element of PI controller

Proportional element of PI controller

Rp

Ri

B100kΩ

RcC = 0.01s

Integrator. RiC = 0.0047s, RcC = 0.1s, Ki = 1/RiC = 213

0 < Kp < 4.5

Ri

Scaled 120Vac wall outlet 60 Hz base, peaking at 8V

-Va

150kΩ

D

G

S

220kΩ

Kp•Verr +

Ki• Intg(Verr)

R

Notes.

1. Shunt resistors Rc, connected across integrator capacitors, drain off parasitic DC voltages slowly and have time constants about 10 times that of the corresponding RiC time constants.

2. The unknown process time constant was determined experimentally by varying the PI error integrator gain to observe the point at which unstable oscillation in output voltage VGS begins. Oscillation occurred for RiC ................
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