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JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR ANANTHAPURAMU (A.P.)COURSE STRUCTURE AND SYLLABUS(For Affiliated Engineering Colleges w.e.f. 2017-18 Admitted Batch)M.Tech-ECE-VLSI, VLSI SYSTEMS, VLSI SYSTEM DESIGN (VLSI, VLSIS, VLSISD)M.Tech I SemesterS.NoSubject CodeSubjectLTPC1.17D06101Structural Digital System Design4--42.17D57101Advanced MOSFET Modeling4--43.17D57102CMOS Analog IC Design4--44.17D57103CMOS Digital IC Design4-45.17D5710417D0610317D57105Elective-I VLSI Signal ProcessingAdvanced Computer ArchitectureCAD for VLSI3--36.17D0620217D5520617D57106Elective-IICPLD and FPGA Architectures and Applicationsb. ASIC Designc. Optimization Techniques in VLSI Design3--37.17D38107Structural Digital System Design Lab--328.17D57107VLSI System Design Lab - I--32 Total22-0626M.Tech II SemesterS.NoSubject CodeSubjectLTPC1.17D57201Low Power VLSI Design4--42.17D57202CMOS Mixed signal Design4--43.17D06201Embedded System Design4--44.17D06109Test and Testability4-45.17D5520117D5720317D57204Elective-IIISystem On Chip ArchitectureSemiconductor Memory Design and TestingRF IC Design3--36.17D3820217D5520417D57205Elective-IVInternet of Things Hardware and Software Co-design of Embedded SystemPhysical Design Automation3--37.17D38208Embedded System Design Lab--328.17D57206VLSI System Design Lab - II--32 Total22-0626M.Tech. II YEAR (III Semester)S.NoCourseCodeSubjectLTPC1.17D2030117D2030217D20303Elective – V ( Open Elective)1. Research Methodology 2. Human Values & Professional Ethics 3. Intellectual Property Rights4------42.17D57301ELECTIVE – VI ( MOOCs)----------3.17D57302Comprehensive Viva Voce--------24.17D57303Seminar--------25.17D57304Teaching Assignment--------26.17D57305Project Work Phase I --------4 Total 4 ................
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