IceCube Neutrino Observatory



Antarctic Astronomy and Astrophysics Research Institute

The University of Wisconsin-Madison

IceCube

DOM PMT High-Voltage Power Supply Control Board

Functional Test Procedure (Draft)

Revision (Original Release) April 15, 2005

Originator

N. Kitamura

Engineer

_______________________

QA

________________________

Approval

________________________

General

1 Definition

The HV Control Board Functional Test is a suite of tests to be performed by the Vendor of the HV Control Board. The test setup consists of hardware test fixture and a personal computer (PC) running a test program. During the Functional Test, the unit under test (UUT) receives power and control commands from the interface of the Digital Optical Module Main Board (DOMMB) under the host PC control. A set of Python scripts running on the host PC controls the tests and collects data for each unit.

2 Responsibility

a. IceCube shall define the Functional Test suite, create necessary test hardware and software and deliver them to Vendor. IceCube shall participate in setting up the test hardware and software at Vendor’s facility.

b. IceCube shall document the procedure for calibrating the test setup, and perform the initial calibration.

c. Vendor shall perform the Functional Test defined herein on every HV Control Board and ship only those that have passed the Test to IceCube.

d. Vendor shall make available the test data generated by the Functional Test software to IceCube prior to the shipment of the units.

3 Applicable Documents

1. DOM PMT High Voltage Power Supply Generator Source Control Drawing—Procurement Document (Rev. -, 9400-0068-SCD.041119.doc)

2. DOM PMT High-Voltage Power Supply Control Board Process Flow and Test Requirements (April 11, 2005)

3. HV Control Board Schematic (9400-0027-SCH.041115.pdf)

4. HV Control Board Parts List (9400-0027-PRT.041111pdf)

5. HV Control Board Assembly Drawing (9400-0027-DWG.041119.pdf)

6. HV Control Board PCB Fabrication Drawing (9400-0027-DWG2.041119.pdf)

7. Interface Ribbon Cable Assembly Drawing (9400-0022-DWG.041109.pdf)

8. HV Control Board Specification Control Drawing (9400-0027-SPC, to be released)

Test Setup

[pic]

Figure 2.1 Hardware setup block diagram

1 Hardware

The functional test setup consists of

1) the test fixture box internally housing the DOM Main Board, DC power supply, and the voltage divider (1:1000), and equipped with the mounting posts and electrical connection mechanism for accepting the UUT on the top side of the box itself;

2) Fluke Model 45 digital multi-meter (DMM) for monitoring the high-voltage output of the UUT that is scaled down by the voltage divider; and

3) the host personal computer to control the measurement.

[pic]

Figure 2.2 DOMMB (RJ45) to RS232 (DB9) connection

Host PC

The host PC communicates with the RS232 ports of the DOMMB and the DMM through its USB ports using the RS232-to-USB adapter cables.

Host PC Minimum Requirements:

• Windows XP Professional

• 256MB RAM

• Pentium 4

• Hard drive

• USB ports

Ribbon Connector

The temporary electrical connection between the ribbon connector and the DOMMB is made at the connector adapter residing on the top side of the test fixture.

[pic]

Figure 2.3 Voltage Divider

HV Monitor

See the above figure for the voltage divider schematic. The temporary electrical connection between the voltage divider and the HV output of the HV Control Board is made using a pair of test grabbers at the end of the test wires.

Calibration

The voltage divider ratio needs calibration. (See Section 6 Calibration.)

2 Software

[pic]

Figure 2.4 Test flow controlled by Python script

Prerequisite

Windows XP Professional

Python 2.3

PySerial

Software Compoents

Installation

Directory Structure

Program directory

Data directory

Parameter directory

Test Definition

1 Initialization

Purpose

Place holder. No measurement is performed.

Pass/Fail Criteria

All units pass automatically.

2 HV ID Read

Purpose

Test the reliable readout of the ID.

Operation

Read the on-board ID device (DS2401) N times, where N = REPEAT_HVID_TIMES.

Parameters

|Name |Value |Explanation |

|REPEAT_HVID_TIMES |10 |Number of times to read the ID. |

Pass/Fail Criteria

All the repeated readouts are non-zero and identical.

3 HV Ramp Up

Purpose

Test the linear relationship between DAC and ADC, and between DAC and HV, when the DAC is ramped up.

Operation

Ramp up HV by setting DAC = 0, 50, 100, ..., 4000, 4095 (decimal, 82 values). Pause T seconds at each DAC setting and then, read the ADC value and the Fluke DMM value. (T = RAMP_WAIT_SEC)

Parameters

|Name |Value |Explanation |

|RAMP_WAIT_SEC |0.1 |Number of seconds to wait between DAC values. |

|ADC_LINEARITY_ERROR |0.025 |Maximum allowed deviation from unity of the slope characterizing ADC|

| | |value vs. DAC value. |

|HV_LINEARITY_ERROR |0.025 |Maximum allowed deviation from unity of the slope characterizing the|

| | |HV output voltage vs. 1000 × DAC voltage. |

|DAC_VOLT_PER_BIT |0.5 |LT1257 scale × 1000 |

|ADC_VOLT_PER_BIT |0.5 |LT1286 scale × 1000 |

|HV_DIVIDER_SCALE |(subject to |Calibration factor of the nominally 1000:1 voltage divider, defined |

| |calibration) |as |

| | |(High-voltage output) divided by (Fluke DMM reading) |

Pass/Fail Criteria

Pass, iff the following conditions are met

| a1 – 1 | < ADC_LINEARITY_ERROR

| a2 – 1 | < HV_LINEARITY_ERROR

a1 and a2 are computed by fitting the data to the following model

AV = a1 × DV + b1

HV = a2 × DV + b2

where

DV = DAC voltage × 1000 = DAC (decimal) × DAC_VOLT_PER_BIT

AV = ADC voltage × 1000 = ADC (decimal) × ADC_VOLT_PER_BIT

HV = High-voltage output = (Fluke DMM read value) × HV_DIVIDER_SCALE

4 HV Ramp Down

Purpose

Test the linear relationship between DAC and ADC, and between DAC and HV, when the DAC is ramped down.

Operation

Similar to HV Ramp Up, except that the DAC value is set in the reverse order of HV Ramp Up.

Parameters

Same as in HV Ramp Up

Pass/Fail Criteria

Same as in HV Ramp Up

5 HV Enable

Purpose

Operation

Disable the HV Generator, set DAC = DAC_ENABLE_VAL, enable the HV Generator, and start recording ADC and DMM at ENABLE_WAIT_SEC intervals.

Parameters

|Name |Value |Explanation |

|DAC_ENABLE_VAL |3000 |DAC value set in the HV Enable test. |

|ENABLE_TIMES |30 |Total number of readings during the HV Enable test. |

|ENABLE_WAIT_SEC |0.1 |Wait period between reads during the HV Enable test. |

|EN_READY_LEVEL |0.1 |See Pass/Fail Criteria of HV Enable |

|EN_READY_TIME |5 |See Pass/Fail Criteria of HV Enable |

Pass/Fail Criteria

Pass, iff the measured ADC and HV values both reach within EN_READY_LEVEL × 100 % of the target value set by DAC in EN_READY_TIME seconds.

6 HV Reads

Purpose

Short-term (~ 1 min.) stability test of HV output and ADC monitor readout.

Operation

Set DAC = DAC_ENABLE_VAL, and read ADC and DMM N times at T seconds intervals, where N = REPEAT_READ_TIMES and T = REPEAT_WAIT_SEC. This test is to follow the HV Enable test.

Parameters

|Name |Value |Explanation |

|REPEAT_READ_TIMES |100 |Number of times to read the ADC and DMM during the HV Reads test. |

|REPEAT_WAIT_SEC |0.5 |Wait period between reads during the HV Reads test. |

|ADC_MEAN_ERROR |0.03 |See Pass/Fail Criteria of HV Reads |

|HV_MEAN_ERROR |0.03 |See Pass/Fail Criteria of HV Reads |

|ADC_STD_ERROR |2 |See Pass/Fail Criteria of HV Reads |

|HV_STD_ERROR |1 |See Pass/Fail Criteria of HV Reads |

Pass/Fail Criteria

Pass, iff the computed mean and standard deviation of the ADC values (decimal) and the HV values (volt) meet the following conditions

| (m1 – m10)/m10 | < ADC_MEAN_ERROR

| (m2 – m20)/m20 | < HV_MEAN_ERROR

s1 < ADC_STD_ERROR

s2 < HV_STD_ERROR

where

m1, s1 = ADC mean and standard deviation, respectively

m2, s2 = HV mean and standard deviation, respectively

m10 = DAC_ENABLE_VAL

m20 = DAC_ENABLE_VAL × DAC_VOLT_PER_BIT

7 HV Disable

Purpose

Operation

Disable the HV Generator, set DAC = DAC_ENABLE_VAL, enable the HV Generator, and start recording ADC and DMM at ENABLE_WAIT_SEC intervals.

Parameters

|Name |Value |Explanation |

|DISABLE_TIMES |30 |Total number of readings during the HV Disable test. |

|DISABLE_WAIT_SEC |0.1 |Wait period between reads during the HV Disable test. |

|DIS_READY_LEVEL |0.9 |See Pass/Fail Criteria of HV Disable |

|DIS_READY_TIME |5 |See Pass/Fail Criteria of HV Disable |

Pass/Fail Criteria

Pass, iff the measured ADC and HV values both fall by DIS_READY_LEVEL × 100 % from the initial value in DIS_READY_TIME seconds after the HV Generator is disabled, where the initial condition is set by DAC_ENABLE_VAL.

8 Shutdown

Purpose

Operator safety.

Operation

Set DAC = 0, power down the HV Control Board, and wait for FINISH_WAIT_SEC seconds.

Parameters

|Name |Value |Explanation |

|FINISH_WAIT_SEC |15 |See Pass/Fail Criteria |

|HV_FINISH_VOLT |30 |See Pass/Fail Criteria |

Pass/Fail Criteria

Pass, iff the output HV is less than HV_FINISH_VOLT after waiting for FINISH_WAIT_SEC seconds.

Test Procedure

1. Turn on the test fixture power

2. Run the batch program runtest.bat by double clicking the shortcut icon. Follow the instructions on the screen.

3. Enter the following at the graphical user interface and click “OK”.

• Operator name

• HV Generator serial number

• HV Control Board assembly serial number

4. Load the device under test (UUT) on the test fixture

1. Mount the unit on the mounting posts

2. Connect the ribbon cable

3. Connect the HV test clips

4. Close the safety cover

5. Start the program by pressing . The program runs for approximately six minutes.

6. When the program terminates, remove the unit and set aside based on the pass/fail result.

7. Press to terminate the program. Pressing any other key will bring the program control to Step 3.

Test Data

Data File Naming Convention

For each run of the functional test, a text file with a name uniquely identifying the UUT serial number and the run number, is created and stored on the hard drive of the host PC. The data file names have the following format:

vvv_HVC_sss_rrr.DAT

where

vvv = Vendor identification

sss = HV Control Board assembly serial number

rrr = Run number. This integer value is incremented each time the test program is executed, thereby keeping track of multiple tests that may be conducted on the same unit.

Information Collected during Tests

The following information is recorded for each test run:

• Run ID

• Test date, start time, and finish time

• Operator name

• UUT identification (UUT S/N, HV Generator S/N, on-board electronic ID)

• Test setup identification (DOMMB ID, Test script name)

• Pass fail results

• Computed results

• Raw data

Data Format

Calibration

Acronyms

ADC Analog-to-digital converter

DAC Digital-to-analog converter

DMM Digital multi-meter

DOM Digital Optical Module

DOMMB DOM Main Board

DVM Digital volt meter

HV High voltage

ID Identification

PC Personal computer

PCB Printed circuit board

PMT Photomultiplier tube

SCD Source control drawing

S/N Serial number

UUT Unit under test

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