Adaptive Integrated Radio System for Wireless Communications



Adaptive Integrated RF Transceivers for Wireless Communications: Invited Paper

Zheng Yuanjin

Integrated Circuit and System Lab.,

Institute of Microelectronics,

11 Science Park Drive, Singapore Science Park II, Singapore 110675, Singapore.

Tel.: (65)67705513

Abstract: In this paper, three radio architectures named high IF, low IF and direct conversion, for wireless communication transceiver systems are reviewed. Based on the literature results, we propose three new and promising adaptive RF receiver system architectures to achieve high performance and low cost implementation at the same time. Chip IC implementation prototype are provided, and simulation and experiment results are shown, which verify the superior performance of the proposed radio systems.

Key-Words: RF transceiver system, High IF receiver, Low IF receiver, Direct conversion receiver, Integrated circuits, Wireless communication

I. Introduction

The steady growth of wireless services and applications has demanded a wireless transceiver, which not only must achieve high performance but also need to attain low cost and small form factor. A fully integrated single-chip CMOS transceiver has become an attractive option to meet this demand [1], [7].

Traditionally, superheterodyne receiver is the most common architecture employed by wireless industry, which can provide many advantages in terms of sensitivity and selectivity. However, the limitations of process technology to realize high performance on-chip RF filter has made designers choosing the bulky and expensive off-chip filter like surface acoustic wave (SAW) filters to reject the images [1].

Recently, RF notch filter integrated with LNA has been proposed to achieve on-chip image rejection [2], [3]. Although it can be used to replace SAW filter for image rejection, it has to compromise in many aspects, such as NF, current consumption, tuning range and image rejection ratio (IRR). To meet the stringent specification of image rejection in many wireless applications, it is good to distribute some image rejection to IF band. Normally, IRM is preferred to fulfill this objective, however, the performance improvement of IRM is always limited by process variation and circuit mismatches [1], [8]. Some researchers have combined the notch filter with the IRM for high image rejection. In [4], an image rejection RF filter combined with a Hartley IRM was integrated to achieve about 79dB image rejection. In another design [5], a simple cross-coupled notch filter was integrated with a Weaver IRM to achieve high image rejection. In this paper, a high image rejection receiver front-end targeted for wideband high data rates wireless communication applications such as wireless LAN 802.11 b&g and Bluetooth is implemented. For this purpose, a new monolithic notch filter with Q-enhancement circuit is proposed in this paper to provide a good image rejection at low current consumption and low noise figure. In addition, the filter is able to attain deep notch response in a wide frequency range. Combined the notch filter with an IRM, total image rejection of 55dB and image rejection band of 100MHz have been realized. Moreover, with fine tuning of the building blocks and the system, the proposed front-end also can be used in other stringent wireless applications such as GSM, DECT, WCDMA, and so on.

In modern wireless communications, the low IF receiver is regarded as a proposing architecture due to its super performance, high degree of integration and low cost [8]-[11]. The main problem is that the image rejection ratio (IRR) provided by this architecture is very sensitive to the amplitude and phase mismatches between the In-phase (I) and Quadrature (Q) path of the receiver [8], [9]. Since it is impossible to attain perfect matching in current analog IC design process, the existed low IF receivers can only attain 30-40 dB IRR [8]. In most RF applications, the image signal may be 60 dB larger than the desired RF signal. Thus, the system must attain IRR around 60 to 70 dB. The matching requirements have put a big challenge to this topology [9]. To improve the IRR of low IF receivers, a technique is developed to convert low IF signals into digital baseband signals, and then I/Q mismatches can be cancelled through various digital signal processing (DSP) algorithms [11]. High IRR can be attained (50-70dB) but the cost and complexity of this method are also significantly increased. Another promising architecture using double quadrature mixers with a complex filter is proposed in [10], which can achieve I/Q phase accuracy of less than [pic]. However, it is still sensitive to amplitude mismatches. To compensate I/Q mismatches efficiently and improve the IRR significantly in low IF receivers, a new feedback tuning architecture is proposed in this paper.

Most recently, direct conversion receiver (DCR) has attracted great attentions since it can significantly lower the power consumption and chip area and allows for a high-level of integration and low–cost realization. However, some issues have prevented its use in practical applications [16]. One of the main problems is the DC offsets produced by self mixing between the leaked LO (RF) with the LO (RF) signal. DC offset can corrupt the signal, but more importantly, it may saturate the following gain stages. Several DC offset reduction techniques have been reported, e.g., even harmonic mixer, servo feedback, and DSP digital controlled canceling technique etc. The realized performance by these has to be compromised with circuit implementation complexity. In this paper, a novel DC offset free RF front-end (DOF_RFFE) architecture is proposed, which can enhance the desired signal and cancel the DC offsets simultaneously at the receiver front-end. A fully integrated DC offset feedback tuning circuits is also proposed to further reduce the time-varying DC offset and improve I/Q matching. A high DC cancellation performance can be achieved with low circuit implementation cost. Potentially, it can be used in most of wireless communication applications, e.g., GSM, WCDMA, WLAN, cordless phone, and so on.

Based on the literature results, we have developed three new receiver systems which can achieve high performance and low cost implementation at the same time. In the following section, these three systems will be discussed in details.

II. New Receiver System Architecture

2.1 High IF Architecture

As shown in Fig. 1, proposed high IF receiver front-end includes a LNA, an active balun, a notch filter, and an image rejection mixer. The LNA is a single-ended design followed by an active balun which can convert the single-ended signal to differential signal [6]. The notch filter is implemented together with the active balun. The integrated LNA and notch filter can amplify the useful RF signal and notch the image signal. A subsequent building block is a Hartley IRM which can provide another image rejection. The IRM is composed of two mixers (Mixer_I&Q), two buffers (LO_Buffer_I&Q), a LO polyphase filter (LO_PF), two IF polyphase filters (IF_PF_I&Q) and an IF combiner [1]. I/Q mixers are used to downconvert the RF signal to the IF signal. The downconverted I/Q signals are firstly shifted by 90( using IF polyphase filters and then the filter outputs are summed differentially by the IF combiner.

The RF central frequency is 2.45GHz and the LO central frequency is 2.082GHz. Thus the image frequency is 1.714 GHz and the IF frequency is fixed at 368MHz. The operating frequency of the notch filter can be tuned from 1.649GHz to 1.779GHz and around 20-30dB image rejection can be provided in this image band. The IRM can provide further 30dB image rejection and thus total around 55dB image rejection can be achieved at the IF output. For whole system, the total gain of the LNA and active mixer core is designed at least 30dB, which can be used to compensate the losses in the IF polyphase filters (~10dB). The notch filter is integrated with the LNA, which consumes small current and adds only a small fraction of NF to the LNA. Due to the high gain of the LNA and mixer, the NF of the whole receiver front-end is less than 8.5dB. The IIP3 of the receiver front-end has to be compromised with the receiver gain, which is targeted to be better than –10dBm. In the following section, each circuit building block is described in detail.

[pic]

Fig. 1 High image rejection high IF receiver RF front-end

2.2 Low IF Architecture

The proposed low IF receiver architecture is shown in Fig. 2. It includes three parts: the forward receiver, the feedback amplitude tuning loop, and the feedback phase tuning loop. A low noise amplifier (LNA) and a pair of I/Q mixers are used in the forward receiver to amplifier and downconvert the RF (and image (IM)) signals coming from the antenna [8]. The RF and IM signals lie in the two sides of the local oscillator (LO) signal both with an interval of an IF frequency [pic]. To separate the RF signal from the IM signal and achieve channel selection, a pair of complex filters is used. When the phase difference of I/Q LOs keeps exactly [pic] and the gains of I/Q mixers remain exactly equivalent, the complex filter can achieve very high image rejection [8], [10]. Since I/Q mismatches between LOs and mixers are inevitable, two tuning loops shown in Fig. 1, are proposed to compensate the mismatches in the forward receiver in this paper. One is an amplitude tuning loop which includes a correlator, a low pass filter (LPF), a gain mismatch estimator (GME), and a variable gain amplifier (VGA). A sign-LMS algorithm is employed to adaptively compensate the I/Q amplitude mismatches. The other is a phase tuning loop which includes a correlator, a LPF, an integrator, and a polyphase filter. When this tuning loop locks, exact quadrature LO signals can be gained. In the following, each part will be introduced in details.

[pic]

Fig. 2 Self-compensated low IF receiver

a. Forward receiver. Assume [pic] represents the equivalent gain mismatches of I/Q mixers, [pic] represents the equivalent phase mismatches of I/Q LOs, and [pic] represents the angle frequency of local oscillator. As shown in Fig. 1, before compensation (i.e. [pic]), the I and Q signals input to the complex filters A and B are:

[pic], (1)

[pic], (2)

After compensation by using two tuning loops, the VGA gain [pic] is tuned to [pic], and the phase [pic] of the LO signal in the Q channel is tuned to [pic], thus the Q signal input to the complex filters changes to:

[pic]. (3)

Comparing (3) with (1), it can be seen that the I/Q amplitude and phase mismatches have been eliminated. In Fig. 1, the complex filter A (B) is used to extract the desired IF (image IF) signal. When the input I/Q signals having mismatches, and after complex filtering, a few image IF (desired IF) signal will leak into the desired IF (image IF) signal passband [11]. Thus [pic] and [pic] become correlated. A correlator in the following feedback amplitude tuning loop will be used to detect this correlation.

b. Feedback amplitude tuning loop. The Correlator1 in Fig. 1 is defined as

[pic], (4)

where E( ) represents the assemble average. As explained above, [pic] may be used to detect the degree of I/Q mismatches. The larger the mismatches, the larger [pic], and the lower the IRR can be achieved. A gain mismatch estimator, employing a simplified sign-LMS algorithm [12], is adopted to adaptively adjust the VGA gain [pic] as follows:

[pic], (5)

[pic]

[pic]. (6)

Here [pic] is the adaptive adjusting step size. The function [pic] is defined as:

[pic]. The gain [pic] is modified in the direction which promotes [pic] decreasing, and thus the IRR is improved significantly.

c. Feedback phase tuning loop. In Fig. 1, RC-CR polyphase filter can produce exact quadrature I/Q LO signals only when the resister and capacitors [pic] in the I channel and [pic] in the Q channel are perfectly matched, i.e., [pic] and [pic]. However, in reality, the mismatches between resistors and capacitors may be as high as 20% [13]. Thus a voltage controlled tunable resistor [pic] is adopted in the Q channel and automatically adjusted by the phase tuning loop, which will change the phase difference between the I and Q LOs. In fact, when the tuning loop locks, the output of the Correlaor2 will be zero and the output of the integrator will converge to a constant DC voltage level. This DC level after amplified is then used to adjust the resistor value of [pic], which resultantly forces the I/Q LOs of the polyphase filter output to be in perfect [pic] phase difference. It can be easily proved that the linearized close loop phase transfer function of the tuning loop is: [pic]. Here [pic] and [pic] represent the phase of I and Q LOs respectively, [pic], [pic], and [pic] represent the gain of the amplifier, integrator, and Correlaor2 respectively, [pic] represents the –3dB bandwidth of the LPF2. As expected, when [pic].

2.3 Direct Conversion Architecture

Figure 3 shows the block diagram of the proposed DC offset free RF front-end (DOF_RFFE). After a LNA, the I and Q signals are obtained through a polyphase filter (PFF) which acts as a wideband Hilbert transformer. The signals are then fed into four symmetrical mixers for downconversion to baseband. The downconverted I and Q signals are subtracted from each other through a subtracter/buffer stage before processed by the baseband circuits. The required four-phase LO signals are obtained with polyphase filters. Alternatively, a quadrature VCO can be used here. Although this architecture has some similarities with the double quadrature mixer proposed in [8], the difference embodies in several aspects. Firstly, the proposed architecture uses distinct phase configuration as shown in Figure 1 to overcome DC offset. Secondly, I and Q buffers are both subtracters. Thirdly, the mixer in the proposed receiver should be a symmetric multiplier core. It will be shown later in this paper that in an ideal case, the proposed system should be DC offset free.

In direct conversion receivers, self-mixing is mainly caused by two types of signal leakages, namely, the mixer port to port leakage due to parasitic capacitance and substrate coupling, and the leakage of the LO signal to the LNA input through substrate coupling and bonding wire or through the antenna [16]. Assuming that the transmitted signal can be represented by [pic], where [pic] and [pic] represent I and Q modulation signals respectively, and [pic] represents the RF carrier (LO) frequency. To cancel the DC offsets due to mixer self-mixing, the signals passed through the polyphase filters are split into I and Q portions as follows:

[pic]. (7)

Here [pic] represents Hilbert transformation. By processing these two signals and combining them as shown in Figure 1, the desired signals that appear at the inputs of each subtracter/buffer are 180o out of phase with each other, whereas the DC offset terms are in phase. Thus, the DC offset can be removed after the subtraction while the desired signal is preserved, i.e.,

(8)

Due to process variation, circuit mismatch and time-varying leaked RF signals, some DC offset inevitably appear at the outputs of subtracter/buffers in Figure 1. To further reduce time-varying DC offset and improve the system robustness to circuit mismatch, a new DC offset feedback tuning circuit, as shown in Figure 4, is also implemented with DOF_RFFE on chip. For tuning purpose, two of the four mixers are designed to have variable gains. A multiplier is used to sense the DC offset at the output of subtracter/buffer stages. A low-pass filter (LPF) is employed to remove the multiplied I/Q signal and leaves only the DC offset. This detected DC offset is then fed to an integrator whose output controls the gain of the two mixers, to further reduce the DC offset at the outputs of the I/Q buffers.

[pic]

[pic]

III. Chip Implementation and Experiment Results

3.1 High IF Radio

The proposed receiver front-end is simulated using HP Advance Design System (ADS) 2002. In-house extracted models for active and passive devices including all kinds of parasitics (e.g. transmission line, pin and package parasitic parameters) are used for the circuit simulation. The RF front-end design described in this paper is fabricated in CMOS 0.35μm, double-poly, four-metal process. The chip layout photo is shown in Fig. 5. The total chip size is 4 mm ( 1.5mm. All the passive components are integrated on-chip. The chipset has been tested on the FR-4 PCB with TQFP-52 pin package.

The image rejection performance is shown in Fig. 6, where RF frequency is set at 2.45GHz and LO frequency is set at 2.082GHz. The image frequency is set at 1.702GHz (It is slightly deviated from the actual image frequency 1.714GHz, so that the IF and image IF signal can be measured simultaneously). It can be seen that the measured IRR (~52.44dB) is quite close to the simulated IRR (~55dB). Fig. 7 shows the measured image rejection ratio vs. RF frequency. We can see that in a frequency range of RF band (2.385-2.515GHz) and image band (1.649-1.779GHz), image signals can be rejected considerably (average 55dB). The image rejection bandwidth of 130 MHz has exceeded the requirements (100MHz) of some wideband wireless systems (e.g. 802.11b&g and Bluetooth).

[pic]

Fig. 5 Chip Photograph

[pic]

Fig. 6 Measured image rejection performance

[pic]

Fig. 7 Image rejection ratio vs. RF frequency

3.2 Low IF Radio

The proposed architecture is applied to a WLAN receiver [1]. The input signals are assumed two QPSK signals, which represent desired RF and IM WLAN signals. The carrier frequency of the RF signal is 947.5 MHz, and that of the IM signal is 949.5 MHz. Thus the IF central frequency is 1 MHz. The RF and IM QPSK signals are both with BT(relative filter bandwidth)=0.3, bit rate=270 kbits/s, and modulation index=0.3 but with different modulation information bits. The complex filters are tuned to the central frequency of [pic]1 MHz and with bandwidth of 200 kHz. Assume the equivalent amplitude mismatch is [pic] (100%) and the phase mismatch is [pic] (11.11%). The minimum step size for adjusting [pic] is set as [pic] and the scheme of adaptively changing step size is adopted [12]. The sampling rate is taken as [pic] samples/s.

The desired IF and image IF signals after complex filtering are presented in Fig. 8 (a) and (b). It can be seen that the desired IF signal is bandpassed while the image IF signal is deeply notched. The estimation of [pic] and [pic] is shown in Fig. 2 (c) and (d). From initial values, the estimates of [pic] and [pic] converge to the desired values of [pic] and [pic] taking about [pic]. The output of Correlator1 is shown in Fig. 8 (e) which continuously decreases from 0 dB to –30 dB or so. Fig. 8 (f) shows the results of image rejection with and without compensation. It can be seen that the IRR is only about 7 dB without compensation while IRR improves to about 70 dB after compensation. The setting time is about [pic]. Moreover, the proposed low IF receiver has also been simulated in various communication systems using AM, FM, PM or various combined modulation schemes. In any case, the receiver always can attain high image rejection, high I/Q balance, and with fast settling time.

[pic]

Fig. 8. Performance of the proposed low IF receiver

IC Implementation Issue: The proposed system can be implemented with analog integrated circuits (ICs) as well as digital ICs. However, extra ADC/DAC is needed to implement the feedback tuning loops in digital ICs by using DSP techniques [11]. To reduce cost and save power consumption, all blocks fabricated with analog (e.g. CMOS) ICs are preferred. In more details, the mixers and the complex filters may be implemented as in [9]-[11]. OpAmp based active LPFs and integrators may be adopted [13]. The correlators may be designed using fully symmetrical analog multipliers [14]. The GMF may be realized using S/H circuits and comparators [13]. VGAs may be implemented using highly linear analog multipliers [15].

3.3 Direct Conversion Radio

The DC offset free receiver front-end is realized in the standard 0.35(m CMOS technology and is housed in a 52 pin ceramic package [17]. Figure 9 shows the test chip micrograph. Figures 10 and 11 show the performance of the DC offset cancellation as RF power and LO power are swept, repectively. In comparison with conventional mixers, a substantial reduction in the DC offset over a large input range is observed. The measured results have shown that the DC offset can be reduced to 2~5 mV by the DOF_RFFE structure alone and further lowered to 0~2 mV by integrating with feedback tuning circuits. Furthermore, the exponential increase of the DC offset with increasing RF power or LO power, as appeared in the conventional receiver architectures, has not been observed in the proposed receiver.

Figure 12 shows the measured two-tone test output spectrum. The LO frequency is fixed at 2.45 GHz and the input power is -4.8 dBm. The two downconverted fundamental tones are located at 3 and 4 MHz, respectively. The second order inter-modulation products located at 6 and 8 MHz are 47.6 dB below the fundamental ones and translate to an IIP2 of 21.8 dBm. Similarly, the third order inter-modulation products at 2 and 5 MHz are 23.7 dB below the fundamental ones, giving an IIP3 of -13.8 dBm. The overall gain of the receiver front-end is around 21.0 dB.

[pic]

[pic]

[pic]

IV. Conclusion

In this paper, three high performance and promising receiver architectures named high IF, low IF, and direct conversion have been reviewed. We have proposed three new receiver systems with respect to these three architectures. Firstly, a monolithic high IF receiver front-end has been realized for the 2.45GHz wideband wireless applications. The receiver front-end requires no off-chip components and it can achieve a good image rejection at low current consumption. The experimental results demonstrate a total gain of 20 dB with associated noise figure of 8 dB, and average 55 dB of image rejection is achieved for the whole system with the total current consumption of 21 mA at 3 V supply. Secondly, a fully integrated amplitude and phase compensated low IF receiver architecture has been proposed. It is self tuned with high image rejection (~70 dB), high I/Q balance and fast setting time. Finally, A DC offset free RF front-end receiver architecture combined with a feedback tuning loop for direct conversion is proposed. The front-end receiver is implemented in a [pic] CMOS process and achieves a measured DC offset less than 2 mV over a RF input range of -100 to 0 dBm and LO input of –20 to 15 dBm, respectively.

Acknowledgement

The author would like to thank ICS lab. managers and staffs for their contribution and support on this work.

Reference:

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IRM

Notch Flter

LNA

Figure 11: DC offset cancellation performance as LO power is varied

Fig. 9: Chip micrograph of direct conversion receiver front-end

PPF_LO

PPF_RF

Buffer_Q

Buffer_I

Tuning Loop

Mixer (4)

LNA

Figure 12: Two tone test output spectrum

Fig. 10: DC offset cancellation performance as RF power is varied

Figure 4: System diagram of DOF_RFFE with feedback tuning

Figure 3: System diagram of DC offset free RF front-end (DOF_RFFE)

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