SINGLE CHIP QPSK DEMODULATOR



Abstract:

This report is an honest attempt to elaborate the method of digital implementation of coherent QPSK Demodulator on single chip. The combination of complexity and speed in designing QPSK Demodulator is finding ready applications for VLSI system. A single chip QPSK Demodulator is of great interest in Wireless Communication, High frequency space Communication and Set top boxes. Utmost Care has been taken to reduce complexity & area of the chip and to minimize required power & probability of bit error by use of convolution coding. The QPSK modulation scheme has been studied thoroughly and the simulation results of MATLAB implementation of QPSK Demodulator and Verilog code for FPGA implementation of High speed multipliers and Viterbi Decoder have been given for the verification.

Keywords:

1. QPSK Demodulation: It is the process of Digital modulation in which two different stream of data are transmitted simultaneously over the same channel instead of single data stream as in the case of binary phase shift keying (BPSK).

2. VLSI: Very Large Scale Integration.

3. Verilog: Commonly used Hardware Description Language.

4. FPGA: Field Programmable Gate Array is a method of implementing the VLSI design.

5. Booth Multiplier: Multiplier designed using Booth’s Algorithm

6. CSD Multiplier: Multiplier designed using CSD Algorithm.

7. Root Raised Cosine Filter: RRC filters are the Match filters implemented using CSD multiplier.

8. Viterbi Decoder: It decodes the convolution coded message using Viterbi Algorithm.

1. Introduction:

Due to high Bandwidth efficiency of QPSK modulation system it is preferred over other system. In fact bit error rate is also at considerable level. This QPSK scheme of Modulation can be understood clearly by the following diagram:

[pic]

Fig.1 QPSK Modulation scheme

These waveforms correspond to phase shifts of 0º, 90º, 180º, and 270º between each other as shown in the phasor diagram below:

[pic]

In four-phase PSK, one of four possible waveforms is transmitted during each signaling interval Ts. These waveforms are:

S1 (t) = A cos (ωct +(/4)

S2 (t) = A cos (ωct +3(/4) for 0≤ t ≤Ts

S3 (t) = A cos (ωct +5(/4)

S4 (t) = A cos (ωct +7(/4)

For the above signal receiver requires two local reference waveforms Acos (ωct + 45) and Acos (ωct – 45) that are derived from a coherent local carrier reference A cos(wct). For purposes of analysis, let us consider the operation of the receiver during the signaling interval (0,Ts). Let us denote the signal components at the output of the correlators by S01 and S02, respectively, and the noise component by N0(t). If we assume that S1(t) was the transmitted signal during the signaling interval (0,Ts), then we have

S01(Ts) = ∫ 0 to Ts(A cos ωct) A cos (ωct + П /4) dt

= A2/2 Ts cos(П /4) = L0

S02(Ts) = ∫ 0 to Ts (Acos ωct) A cos (ωct – П/4) dt

|OUTPUT |INPUT |

| |S1 (t) |S2 (t) |S3 (t) |S4 (t) |

|S01 (k Ts) |L0 |-L0 |-L0 |L0 |

|S02 (k Ts) |L0 |L0 |-L0 |-L0 |

= A2/2 Ts cos П/4 = L0

[pic]

Fig.2 Block diagram of QPSK Demodulator

The digital implementation of QPSK demodulator is achieved by sampling the coming modulated signal using ADC of 8-bit precision. This digitized data is given to high speed multiplier. Here we have used the Booth’s Multiplier as the high speed multiplier .The other multiplier input will come from the carrier recovery circuit .this is also 8-bit data. This will pass through the LPF filter which also digitally implemented. The output of LPF will pass through the Matched Filters. All the filters can be implemented using the FIR filters. For that we have designed Constant coefficient multiplier (CSD multiplier). At last symbol timing recovery block samples the output of match filter at a specific time and hence we get the demodulated output. Following diagram give functional details of QPSK Demodulation scheme:

[pic]

2. Booth’s Multiplier

High-speed multipliers are essential to design a QPSK Demodulator with high data output rate. Here we have used the Booth’s algorithm to implement to design our multiplier. Booth's algorithm is a multiplication algorithm, which worked for two's complement numbers. It is similar to paper-pencil method, except that it looks for the current as well as previous bit in order to decide what to do. If the time required for an addition or a subtraction is sufficiently large, then a considerable gain in performance can be obtained by keeping the number of the additions to a minimum. In Booth's algorithm, if the multiplicand and multiplier are n-bit two's complement numbers; the result is considered as 2n-bit two's complement value. The overflow bit (outside 2n bits) is ignored. Following flow-chart describes the booth’s algorithm:

[pic]

Fig.3 Booth’s Algorithm

Here is an example:

4 bits

0110 ................
................

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