Embedded Design Flow Workshop



DSP Design Flow WorkshopXUPV5 Evaluation PlatformCOURSE DESCRIPTIONThe DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification. Install SoftwareThe workshop has been tested on a PC running the Windows XP Professional operating system. Mathworks toolsrelease r2009b (includes Matlab/simulink) Simulink signal processing blocksetXilinx tools (Professors may submit online donation form at university)v12.2i ISE Foundation Software v12.2 System Generator for DSPInstall workshop materialsThe labsource.zip file contains xupv5_board_plugin.zip and labs.zip files. Unzip this file in temp.The plugin files are required to enable JTAG co-simulation targeting the XUPV5 board.Unzip xupv5_board_plugin.zip file in <xilinx12_2>\DSP_Tools\nt\sysgen directoryVerify installationStart Matlab 2009b and enter simulink at the matlab command prompt to invoke simulinkExpand the Xilinx blockset and select Basic ElementsDouble-click on the System Generator tokenSelect Hardware Co-Simulation as the compilation type and select xupv5 board. The following options should be selected and grayed outPart: Virtex-5 xc5vlx110t-1ff1136 deviceFPGA clock period (ns): 10Clock pin location: fixedThe labs.zip file consists of source files needed to conduct labs. Unzip the labs.zip file in c:\xup\dsp_flow\ directory.The docs_pdf.zip file contains lab documents and presentations in PDF format. Unzip this file in c:\xup\dsp_flow or any other directory of your choice.Setup the hardwareConnect and power the XUPV5 Development PlatformConnect up the XUPV5 Development PlatformConnect the power supplyConnect the USB download cable between the JTAG configuration port of the board and USB connection on the PCPower up the boardFor Professors onlyDownload the labsolution.zip and docs_source.zip files using your membership account. Do not distribute them to students or post them on a web site. The docs_source.zip file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use in your classroom.Get startedReview the presentation slides and complete the lab exercises according to the workshop flow shown below.Contact XUP Please email xup@ with questions or commentsWorkshop FlowDay 1 AgendaDay 1 MaterialsFPGAs for DSP01_intro.pptxIntroduction to System Generator for DSP02_Intro_SysGen.pptxSimulink Basics03_Simulink_Basic.pptxLab 1 introduction03a_Lab1_Intro.pptxLab 1: Brief introduction to Simulinklab01.docx (lab 1 instructions)/labs/lab1 (lab 1 “user” directory)/labsolution/lab1 (lab 1 solutions)Basic Xilinx Design Capture04_Basic_XDC.pptLab 2 introduction04a_Lab4_Intro.pptLab 2: Getting Started w/ System Generatorlab02.docx (lab 2 instructions)/labs/lab2 (lab 2 “user” directory)/labsolution/lab1 (lab 2 solutions)Signal Routing 05_Signal_Routing.pptxLab 3 introduction05a_Lab3_Intro.pptxLab 3: : Signal Routinglab03.docx (lab 3 instructions)Day 2 AgendaDay 2 MaterialsImplementing System Control06_System_Control.pptxLab 4 introduction06a_Lab4_Intro.pptxLab 4: Implementing System Controllab04.docx (lab 4 instructions)Multi-Rate Systems07_Multirate_Systems.pptxLab 5 introduction07a_Lab5_Intro.pptxLab 5: Designing a MAC FIRlab05.docx (lab 5 instructions)Multi-rate systems08_Filter_design.pptxLab 6 introduction08a_Lab6_Intro.pptxLab 6: Designing a FIR Filterlab06.docx (lab 6 instructions) ................
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