Designing Digital Circuits a modern approach

Designing Digital Circuits a modern approach

Jonathan Turner

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Contents

I First Half

5

1 Introduction to Designing Digital Circuits

7

1.1 Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Gates and Flip Flops . . . . . . . . . . . . . . . . . . . . . . . 9

1.3 How are Digital Circuits Designed? . . . . . . . . . . . . . . . 10

1.4 Programmable Processors . . . . . . . . . . . . . . . . . . . . 12

1.5 Prototyping Digital Circuits . . . . . . . . . . . . . . . . . . . 15

2 First Steps

17

2.1 A Simple Binary Calculator . . . . . . . . . . . . . . . . . . . 17

2.2 Representing Numbers in Digital Circuits . . . . . . . . . . . 21

2.3 Logic Equations and Circuits . . . . . . . . . . . . . . . . . . 24

3 Designing Combinational Circuits With VHDL

33

3.1 The entity and architecture . . . . . . . . . . . . . . . . . . . 34

3.2 Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3 Processes and if-then-else . . . . . . . . . . . . . . . . . . . . 43

4 Computer-Aided Design

51

4.1 Overview of CAD Design Flow . . . . . . . . . . . . . . . . . 51

4.2 Starting a New Project . . . . . . . . . . . . . . . . . . . . . . 54

4.3 Simulating a Circuit Module . . . . . . . . . . . . . . . . . . . 61

4.4 Preparing to Test on a Prototype Board . . . . . . . . . . . . 66

4.5 Simulating the Prototype Circuit . . . . . . . . . . . . . . . . 69

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4.6 Testing the Prototype Circuit . . . . . . . . . . . . . . . . . . 70

5 More VHDL Language Features

77

5.1 Symbolic constants . . . . . . . . . . . . . . . . . . . . . . . . 78

5.2 For and case statements . . . . . . . . . . . . . . . . . . . . . 81

5.3 Synchronous and Asynchronous Assignments . . . . . . . . . 86

5.4 Structural VHDL . . . . . . . . . . . . . . . . . . . . . . . . . 89

6 Building Blocks of Digital Circuits

93

6.1 Logic Gates as Electronic Components . . . . . . . . . . . . . 93

6.2 Storage Elements . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.3 Larger Building Blocks . . . . . . . . . . . . . . . . . . . . . . 100

6.4 Lookup Tables and FPGAs . . . . . . . . . . . . . . . . . . . 105

7 Sequential Circuits

109

7.1 A Fair Arbiter Circuit . . . . . . . . . . . . . . . . . . . . . . 110

7.2 Garage Door Opener . . . . . . . . . . . . . . . . . . . . . . . 118

8 State Machines with Data

127

8.1 Pulse Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

8.2 Debouncer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

8.3 Knob Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 137

8.4 Two Speed Garage Door Opener . . . . . . . . . . . . . . . . 141

II Second Half

147

9 Still More VHDL

149

9.1 Making Circuit Specifications More Generic . . . . . . . . . . 149

9.2 Arrays and Records . . . . . . . . . . . . . . . . . . . . . . . 152

9.3 Using Assertions to Detect Bugs . . . . . . . . . . . . . . . . 155

9.4 VHDL Variables . . . . . . . . . . . . . . . . . . . . . . . . . 156

9.5 Functions and Procedures . . . . . . . . . . . . . . . . . . . . 159

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10 Design Studies

163

10.1 Four-way Max Finder . . . . . . . . . . . . . . . . . . . . . . 163

10.2 Binary Input Module . . . . . . . . . . . . . . . . . . . . . . . 168

10.3 LCD Display Module . . . . . . . . . . . . . . . . . . . . . . . 172

10.4 Binary Output Module . . . . . . . . . . . . . . . . . . . . . . 175

11 Verifying Circuit Operation

179

11.1 Assertion Checking in Circuit Specifications . . . . . . . . . . 180

11.2 Testing Combinational Circuits . . . . . . . . . . . . . . . . . 181

11.3 Testing State Machines . . . . . . . . . . . . . . . . . . . . . 187

11.4 Testing Larger Circuits . . . . . . . . . . . . . . . . . . . . . . 195

12 Continuing Design Studies

197

12.1 Simple Data Queue . . . . . . . . . . . . . . . . . . . . . . . . 197

12.2 Packet FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

12.3 Priority Queue . . . . . . . . . . . . . . . . . . . . . . . . . . 212

13 Small Scale Circuit Optimization

219

13.1 Algebraic Methods . . . . . . . . . . . . . . . . . . . . . . . . 220

13.2 Algorithmic Methods . . . . . . . . . . . . . . . . . . . . . . . 224

14 Still More Design Studies

235

14.1 VGA Display Circuit . . . . . . . . . . . . . . . . . . . . . . . 235

14.2 Mine Sweeper Game . . . . . . . . . . . . . . . . . . . . . . . 245

15 Implementing Digital Circuit Elements

265

15.1 Gates and Transistors . . . . . . . . . . . . . . . . . . . . . . 265

15.2 Delays in Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 272

15.3 Latches and Flip Flops . . . . . . . . . . . . . . . . . . . . . . 275

16 Timing Issues in Digital Circuits

281

16.1 Flip Flop Timing Parameters . . . . . . . . . . . . . . . . . . 281

16.2 Metastability and Synchronizers . . . . . . . . . . . . . . . . 290

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III Third Half

295

17 Introduction to Programmable Processors

297

17.1 Overview of the WASHU-2 Processor . . . . . . . . . . . . . . 297

17.2 Machine Language Programming . . . . . . . . . . . . . . . . 302

17.3 Prototyping the washu-2 . . . . . . . . . . . . . . . . . . . . 309

17.4 Using Subprograms . . . . . . . . . . . . . . . . . . . . . . . . 312

18 Implementing a Programmable Processor

321

18.1 Overview of the Implementation . . . . . . . . . . . . . . . . 321

18.2 Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 323

18.3 VHDL Implementation . . . . . . . . . . . . . . . . . . . . . . 326

19 Supporting Components

337

19.1 Overview of the Complete System . . . . . . . . . . . . . . . 337

19.2 Implementing the Console . . . . . . . . . . . . . . . . . . . . 341

20 Memory Components

353

20.1 SRAM Organization and Operation . . . . . . . . . . . . . . 353

20.2 Alternate Memory Organizations . . . . . . . . . . . . . . . . 360

20.3 Dynamic RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . 362

21 Improving Processor Performance

365

21.1 A Brief Look Back at Processor Design . . . . . . . . . . . . 365

21.2 Alternate Instruction Set Architectures . . . . . . . . . . . . . 367

21.3 Implementing the WASHU-16 . . . . . . . . . . . . . . . . . 372

22 Improving Processor Performance Even More

387

22.1 Cache Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 388

22.2 A Cache for the WASHU-2 . . . . . . . . . . . . . . . . . . . 391

22.3 Beyond Direct-Mapped Caches . . . . . . . . . . . . . . . . . 394

22.4 Other Ways to Boost Performance . . . . . . . . . . . . . . . 397

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23 Making Circuits Faster

399

23.1 Faster Increment Circuits . . . . . . . . . . . . . . . . . . . . 399

23.2 Faster Adder Circuits . . . . . . . . . . . . . . . . . . . . . . 403

23.3 Other Linear Circuits . . . . . . . . . . . . . . . . . . . . . . 405

23.4 Multiplication Circuits . . . . . . . . . . . . . . . . . . . . . . 408

24 Producing Better Circuits Using VHDL

413

24.1 Some Motivating Examples . . . . . . . . . . . . . . . . . . . 414

24.2 Estimating Resource Usage . . . . . . . . . . . . . . . . . . . 418

24.3 Estimating and Reducing Resource Usage . . . . . . . . . . . 421

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