Using ispDesignEXPERT Starter Software



Using Lattice’s ispDesignEXPERT Starter Software

Leif Ilvedson

October 15, 2001

Overview

The following is a procedure on the basic use of Lattice’s ispDesignEXPERT Starter Software. The scope of the following procedure is to produce a JEDEC file for the target PLD, the GAL16V8D-15LP, using two different design entries: Verilog and Schematic.

The design implemented is the D-latch.

The first procedure will demonstrate the Verilog design entry. The second procedure will demonstrate the Schematic design entry.

Understanding the Procedure Protocol

The following protocol may be seen: go to File/New Project/Open. This implies that one would click on the File menu, then on New Project button, and finally on the Open button.

Procedure 1: Verilog Design Entry

1. Start the ispDesignEXPERT Starter Software.

2. Go to File/New Project.

3. In the Create New Project window, name the project D_Latch.syn.

4. In the project type drop-down menu, select Schematic/Verilog HDL as in Figure 1.

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Figure 1

5. Give the project a title by double-clicking on “Untitled” in the left pane of the Project Navigator window as shown in Figure 2. Enter “D Latch” and click OK.

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Figure 2

6. Now the target device needs to be selected. Double-click the yellow square that says “ispLS1538…..” in the left pane of the Project Navigator window. In the Device Selector window (Figure 3), select the appropriate choice from the drop-down menus and click OK.

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Figure 3

7. Click Yes in the Confirm Change window (if this window pops up).

8. Click the New button at the bottom left of the Project Navigator window (the main window – see Figure 4).

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Figure 4

9. Select Verilog Module and click OK. (Figure 5)

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Figure 5

10. Enter “D_Latch” and “d_latch” in the Module Name and File Name text fields, respectively (Figure 6). Then click OK.

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Figure 6

11. Enter the following code into the Text Editor window and save it (click File/Save).

module D_Latch(Q, notQ, D, Enable);

parameter delay = 50;

output Q, notQ;

input D, Enable;

wire i1, i2, i3;

nand N1(i1, D, Enable);

nand N2(i2, Enable, notD);

nand N3(Q, i1, notQ);

nand N4(notQ, Q, i2);

not (notD, D);

endmodule

12. Back in the Project Navigator window, highlight the D_Latch Verilog module just created by clicking on it. (Figure 7)

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Figure 7

13. Compile time! In the right pane of the Project Navigator window, double-click on Compile EDIF File. A Process window will indicate compilation process. A warning window may appear, if so, click OK (see Figure 8). Then the Report Viewer window will pop up (Figure 9)…just close it.

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Figure 8

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Figure 9

In the Project Navigator window, an exclamation mark next to Compile EDIF File signifies that the Verilog code compiled successfully but with warnings. (Figure 10).

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Figure 10

14. Create the JEDEC file: In the left pane of the Project Navigator, click on GAL16V8D-15LP, then double-click JEDEC File in the right pane. A bunch of green check marks should appear (Figure 11).

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Figure 11

15. Find out the pin assignment: In the right pane of the Project Navigator window, double-click Fitter Report. The Report Viewer window will pop up (Figure 12). The Fitter Report tells what the pin assignment is.

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Figure 12

16. The pin assignments are known and the JEDEC file has been created. Now the target device is ready to be programmed!

Procedure 2: Schematic Design Entry

1. Start a new project and repeat steps 1 through 8 of Procedure 1. Name it D_Latch_Sch.syn to make it distinct from the project created in Procedure 1.

2. Select Schematic in the New Source window and then click OK. (Figure 13)

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Figure 13

3. Enter “D_Latch” for the Schematic File Name and click OK (Figure 14).

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Figure 14

4. In the Schematic Editor window, click View/Drawing Toolbar if the Drawing Toolbar isn’t already displayed.

5. Getting Parts: Click on the Add Symbol button (upper left button in the Drawing Toolbar). Then select GATES.LIB and G_2NAND in the Symbol Libraries window (Figure 15).

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Figure 15

6. Place parts as shown in Figure 16. (The inverter is the symbol G_Inv.) Tool Tip: Right-clicking ends the current operation.

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Figure 16

7. Click the Add Net Names button (has “abc” on it) and then notice the text field at the bottom of the Schematic Editor window; it says “Enter Net Name=”. Enter “D” and press Enter. Then click to place it. Do the same with “Enable,” “Q,” and “Q Bar.” (Figure 17).

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Figure 17

9. Make the inputs and outputs: Select the Add I/O Marker button (next to the Add Net Names button. In the I/O Marker window, select Input and then click on the little red square below each “D” and “Enable” in the drawing. The select Output and click on the “Q” and “QBar.” It should look like that in Figure 18.

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Figure 18

10. Wire it up: Select the Add Wire button (top middle) in the Drawing Toolbar. Wire the circuit like that shown in Figure 19. Tool Tip 1: To draw wires at a 45 degree angle, hold down the Shift key and click once (don’t drag), then click the end point. (It is somewhat tricky.) Tool Tip 2: To move things around, select the move button (Figure 20), click once on the little red square of an object such as “Enable” and then click where you want the little red square to be.

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Figure 19

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Figure 20

11. Save it: Click File/Save.

12. Compile: In the left pane of the Project Navigator window, highlight the schematic d_latch by clicking on it. Then double-click Compile Schematic in the right pane. A green check mark will appear next to it after it compiles successfully (Figure 21).

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Figure 21

13. Create the JEDEC file: Select GAL16V8D-15LP in the left pane of the Project Navigator window and then double-click JEDEC File in the right pane. Green check marks indicate what has been finished successfully (Figure 22).

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Figure 22

14. Determine the pin assignments: In the right pane of the Project Navigator window, double-click Fitter Report. The Report Viewer window will pop up and the pin assignments can be found (Figure 23).

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Figure 23

15. The pin assignments are known and the JEDEC file has been created. Now the target device is ready to be programmed!

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