University of Florida



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EEL 4914 Electrical Engineering Design

(Senior Design)

Summer Semester 2002

Wireless Transmission of Digital Audio

Final Paper

Submitted by:

Eric Donnelly, Scott Owen, Kahlil Khan

Project Abstract

The goal of the project is to wirelessly transmit digital audio over a short distance. This is accomplished by digitizing an analog input and then compressing the data to a rate of 56kbps or less using the MPEG 1 or 2 layer 3 compression algorithm. The data is transmitted over the 900MHz ISM radio band. At the receiving end, the data is down converted to base-band, uncompressed and then converted to an analog audio signal and pre-amplified.

Introduction

The application for this design is a consumer product that allows a user to play PC audio on a stereo not wired to the PC. Recent advances in technology have allowed users to digitize music collections and use the PC as a component in an entertainment system. However, practicality has limited the placement of the PC with other stereo components, blocking the further integration with a traditional entertainment system. The main problem so far has been getting the signal to the stereo, which traditionally is in a different place in the home. Wireless transmission of this signal would allow the PC to become a more integrated part of a stereo system by removing the limitations of running cable through a home. Existing products use analog transmission, which adds distortion and does not allow error correction or detection, making high signal-to-noise ratios unfeasible. With digital signaling and MPEG layer 3 psychoacoustic modeling, a high quality stereo signal is maintained.

Technical Objectives

• The primary technical goal of this project is the design and implementation of a transmitter and receiver that broadcasts digital, compressed audio wirelessly using an analog input from a PC and analog output to RCA terminals. The specifications include

• Transmitting audio using the frequency shift keying modulation technique

• Broadcasting digital data over a range of 25ft

• Converting to an analog signal at the receiving end.

• The learning objective of the study is to gain a better understanding of the principles behind wireless audio transmission. These principles include:

• Learning about different digital modulation techniques

• Using a microcontroller and I2C to interface components

• Understanding the structure of MP3 frames

• Learning about mixed-signal design process

• Designing printed circuit boards

• Soldering surface-mount components

Study Plan

• Core competencies:

• Knowledge of basic audio concepts

• Digital logic and Microprocessor programming (EEL 3701, EEL 4712, EEL 4744)

• Wireless data transmission (EEL 4930, EEL 4514)

• Digital encoding and error correction/detection (EEL 4750, EEL 4514)

• PC interfacing

• Antenna theory

• CAE Tools:

• MATLAB

• MaxPlus II

• A prototype will be assembled on a PCB and interfaced using standard inputs and outputs (analog audio).

• Resources:

• Instruction from professors

• Dr. McNair, Dr. Taylor, Dr. Latchman

• Microcontrollers and programming hardware and software

• Integrated transmitter and receiver

• Programmable Logic

• Test/Fab Equipment

• PROTEL milling machine

• Spectrum Analyzer

• Oscilloscope

• Logic Analyzer

Architecture

Analog audio is sent to the encoder via RCA cables. The audio is then converted to a digital stream through an A/D converter. Next, the signal is compressed into MP3 frames by the Micronas’ DSP core. The compressed signal is then sent to the Atmel AVR microcontroller through a parallel interface. The microcontroller then transfers the data to its UART, which passes the data serially to the wireless transmitter. Decoding is the reverse of this process, where the serial data is taken from the UART and passed to the Micronas chip. It is then decoded and converted back to an analog signal via a D/A converter, and sent to the stereo through RCA cables.

Encoder Design

Micronas MAS 3587F

The Micronas MAS 3587F contains three regions, the DSP core, audio codec, and direct configuration control registers. All controlling of this chip is done through the I2C interface. The audio codec contains A/D and D/A converters as well as signal mixing and audio processing such as volume control, bass, treble, loudness, and balance. The encoder uses the A/D converter to take in analog audio from the RCA jacks. The digital stream is then passed to the DSP core where firmware converts this signal into valid MP3 frames using variable bit-rate encoding. Values set in the DSP’s control registers determine the quality and configuration of the MP3 frames. Each byte of encoded data is sent out of the Micronas chip through a parallel port to the Atmel microcontroller.

Atmel ATMega163

The Atmel AVR microcontroller configures the MAS 3587F using the I2C interface and transfers parallel data to the UART for serial wireless transmission. I2C will be discussed in detail in the following section. The encoded data from the Micronas is read into the Atmel by a parallel I/O handshaking protocol. The figure below shows the timing diagram as described in the Micronas datasheet.

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Once data is read into the Atmel, it is sent to the built-in UART, which is connected to the wireless transmitter.

Power Supply

The power supply region outputs two separate, regulated voltages(3.5 and 5 Volts). A LM7805 5-volt, voltage regulator is used to create the regulated voltage needed by the Atmel microcontroller. A LM317 adjustable voltage regulator is used to generate a 3.5 Volt output for the Micronas’ five power regions. One-kΩ and 560Ω resistors are used to tune the adjustable regulator to the desired 3.5 Volt output level.

Discrete Components

DC blocking capacitors are connected in series to the left and right analog inputs of the Micronas chip. Filter capacitors are attached between the left and right inputs and ground. Inductance caused by leads is offset by capacitors connected between power and ground. Pull-up resistors are employed on the I2C bus as well as other various components. The schematic and circuit board design is shown in Appendix A.

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Encoder Board

Decoder Design

The decoder is very similar to the encoder. However, DC blocking capacitors are implemented on the outputs instead of the inputs, as well as low-pass filters on each channel. The parallel I/O is also handled differently s seen in the timing diagram below. The schematic is shown in App. B.

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Decoder Board

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Decoder Handshaking Protocol

SMT Adapters

The Micronas chip comes in a 64 pin quad flat pack (QFP) with a pin pitch of .5mm. This is too small to prototype, so adapter boards had to be considered. The two options were buying a pre-made adapter, or milling our own. We ended up choosing each option for the two boards. Both solutions offered their own advantages and disadvantages as shown below:

| |Advantages |Disadvantages |

|Milled Board |Free |Difficult to solder |

| |Fast |Difficult to mill |

| |Easy to Debug | |

|Purchased Adapter |Tinned pad |Cost ($40) |

| |Easy to solder |Lead Time (2 weeks) |

| | |Difficult to debug |

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Milled Adapter

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Purchased Adapter

Software

The software written for the Atmel microcontroller is composed of three main parts. These are the I2C library, the Micronas initialization, and the encoding and decoding subroutines.

I2C

The Codevision development environment included an I2C library, however this library was very basic, and did not perform all the functions in the way we required. Therefore, we built our own library that complied with the protocol specified in the Micronas datasheet. This required a full understanding of the I2C interface as well as the integration of a wait function into several of the subroutines. The I2C protocol specifies that a master (Atmel) and slave (Micronas) device should exist for communication. After the master has issued a command, it waits for an acknowledgement from the slave device. Sometimes it is necessary for the slave to process data before receiving further instruction from the master, therefore a wait function was written to instruct the master to wait for the clock line to go high, telling the master that the slave is finished processing and ready for the next command. Appendix D shows the C code for the complete I2C library written by us.

Micronas Initialization

The Atmel microcontroller uses I2C to initialize the control, DSP, and codec registers in the Micronas chip. The Micronas chip has three direct configuration control registers. Two of these registers deal with DC/DC conversion, which was not implemented, however the third register enables the DSP core and audio codec, as well as sets our analog supply voltage range. The range selected for our board was 1.6V, which was recommended for our particular supply voltage. We selected to run the decoding or encoding application from the application selection cell, and then verified the result in the application running cell. The encoder control memory cell was used to set the quality, sampling frequency, enable CRC, enable stereo, which is used to build the MPEG headers. The main I/O memory cell was used to set the inputs and outputs as analog, and choose between MPEG 1 and MPEG 2 encoding in order to synthesize the correct clock speed. Depending on the application used, various audio codec registers were set. These codec registers dealt with the A/D converters, amplifiers gains, volume control, balance, DSP/analog mix, and stereo/mono select. Table 1 shows the values set for the registers in both applications.

|(all values in hex) |Memory Address |Encoder |Decoder |

|Control register |6A |8C 00 |8C 00 |

|DSP app. select |07F6 |00 40 |00 0C |

|Encoder control |07F0 |08 C4 |NA |

|Main I/O control |F1 |00 0D |00 11 |

Table 1

Encoder/Decoder Loop

Referring to Figures 1 & 2 code was written to implement the handshaking for the parallel I/O interface (Appendix C).

o Encoder – The Atmel chip waits for the “End of Data” (EOD) signal to go high. The Atmel then sets the “Parallel Request” (PR) line high—signaling that it is ready to receive data. The Micronas chip the sets the “Ready to Write” (RTW) line low, indicating that valid data is on the I/O pins. Once this data is read into the Atmel, the PR line is set back to low. The Micronas responds by setting the RTW high. This process is repeated while the EOD line is high.

o Decoder – The Atmel chip waits for the EOD line to go high. It then puts the data out on the parallel I/O lines, and sets the PR line high to signal valid data on the bus. The Micronas responds by setting the “Ready to Read” (RTR) line low and reads in the 8-bits of data. It sets the line high—signaling data has been read—then the Atmel responds by setting the PR line low again. This process is repeated while the EOD line is high.

Test and Validation Methodology

The design was broken down in to discrete components that allowed testing and debugging of each component before it was integrated with the final design. These steps included:

• Wireless data transmission: This portion of the design was inputting a signal using a function generator and observing the output on an oscilloscope and a spectrum analyzer. Next we verified the ability to transmit UART frames by sending ASCII text files between two computer and verifying a stable connection. At speeds of 38kbps, the transmission had errors in roughly 1 in 10,000 bits sent (BER = 10-5).

• Circuit board design: Before and after soldering components onto the milled boards, we performed continuity checks to verify proper connections between components.

• Power regions test: Both the encoder and decoder boards have two power regions. We validated that proper voltage levels were reaching the microcontroller as well as the five power regions of the Micronas chip.

• Surface-mount adapter design: After the Micronas QFPs was soldered to the adapters, we verified the continuity on each pin and checked for solder bridges.

• I2C: An oscilloscope was connected to the data and clock lines to test proper operation of the software. Furthermore, we connected the microcontroller to the serial communication port to verify correct writing and reading of I2C data to the Micronas chip.

• Encoder design: The UART of the encoder was attached to the serial communication port of the computer via a level-shifter. The data was read in by a terminal application and the binary values were analyzed to ensure proper MP3 header and data creation. We also looked at the information given by an audio editing program to verify that the correct bit rate, error correction, etc., were implemented. If the data looked fine, we listened to the data through an MP3 player.

Market Analysis

We believe that this device could have a very large market potential if it were to be released as a product. If made in quantity the device would cost under $100 dollars, and would fulfill a need that has yet to be satisfied. The applications of this product are very versatile, and not limited to a PC-to-stereo configuration, in fact any analog source may be used as the input and slight changes to the software would allow digital input and outputs in the S/PDIF format. The market advantage that this product has over the any product that is offered at this time, is its ability to transmit digitally, which ensures lossless transmission, providing high quality audio.

Expected versus Actual Outcome

The expected outcome of this project was a device that would take an analog input and digitally modulate the signal and transmit wirelessly to a receiver, where it would be demodulated and output to an analog source. Unforeseen in the original proposals were limitations of bandwidth that would allow an uncompressed audio stream. To solve this problem the signal had to be compressed. The compression scheme chosen was MP3, which ran at a rate that was suitable for the bandwidth that was available to us. The limitations of bandwidth could be resolved and the compression eliminated in a commercial product, but because of financial and time limitations it was necessary to get a low priced, easily implemented solution to the wireless portion of the project.

Study Organization

Portions of the project were broken into discreet areas of study and expertise:

• I2C, circuit board verification (Eric)

• Soldering, circuit board verification (Scott)

• Schematic and board design (Kahlil)

References or Bibliography

• Datasheets (Linx, TI, Micronas, Microchip)

• Digital & Analog Communications, L. Couch

• Internet resources:

o

o

o USENET

Supplementary Information

What percentage of your proposed total study relates to:

Hardware design and implementation? 70%

Software design and implementation? 5%

Design integration? 10%

Test and validation? 10%

Documentation? 5%

Materials and Resources

• IC’s:

o Linx EVAL-916-ES 916.45 MHz evaluation kit. (transmitter & receiver)

▪ RXM-916-ES (Reciever)

▪ TXM-916-ES (Transmitter)

o Micronas MAS3587F compression/decompression chip

o ST Microelectronics STA013, Micronas MAS3507 decoder chips

o TI ADC and DAC chips

o Microcontroller (PIC, Motorola, Atmel, Alter)

• Discrete Components (R, L, C’s)

• Oscillators

• Protel and Milling Machine

Appendix A: Encoder

Schematic

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Printed Circuit Board

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Appendix B: Decoder

Schematic

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Printed Circuit Board

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Appendix C: Software: Encoder/Decoder

// INCLUDES

#include

#include

#include

// DEFINES

#define BUFFER_SIZE 250

#define ENCODE PINA

#define EOD PINC.3

#define RTW PINC.5

#define PR PORTC.6

// FUNCTION FORMS

void control_write_verify(char sub_addr, char data_h, char data_l);

void control_write(char sub_addr, char data_h, char data_l);

void control_read();

void dsp_write_verify(char addr_h, char addr_l, char data_h, char data_m, char data_l);

void dsp_write_long(char addr_h, char addr_l, char data_h, char data_m, char data_l);

void dsp_read_long(char addr_h, char addr_l);

void codec_write_verify(char addr_h, char addr_l, char data_h, char data_l);

void codec_write(char addr_h, char addr_l, char data_h, char data_l);

void codec_read(char addr_h, char addr_l);

void mas_init(void);

char mas_config_encoder(void);

void send_to_UART(void);

void toU(char first);

// GLOBAL VARIABLES

char flag = 0;

char uflag = 0;

static char read_h = 0x99;

static char read_m = 0x98;

static char read_l = 0x97;

// MAIN SUBROUTINE

void main(void){

char count =0;

// PORT INITS

PORTB=0x00;

DDRB=0x00;

PORTC=0x00;

DDRC.6=1;

DDRC.7=1;

// UART initialization

UCSRA=0x02; //57600

UCSRB=0x08;

UBRR=12;

UBRRHI=0x00;

// Analog Comparator initialization

ACSR=0x80;

SFIOR=0x04; //disable pull-up

// START COMMUNICATION BTWN CHIPS

mas_init();

flag = mas_config_encoder();

delay(100);

// INFINITE LOOP

if (flag) toU(flag);

else while (1) send_to_UART();

// else while (1) toU(count++);

}

// SUBROUTINE: INITIALIZE MAS CHIP

void mas_init(void){

// RESET MAS CHIP

DDRB.2 = 1;

delay_ms(100);

DDRB.2 = 0;

delay_ms(1000);

}

// SUBROUTINE: CONFIGURE TO ENCODER

char mas_config_encoder(void){

control_write_verify(0x6A, 0x8C, 0x00);

delay_ms(20);

dsp_write_verify(0x07, 0xF0, 0x08, 0x08, 0x64); // ENCODER CONTROL

dsp_write_verify(0x07, 0xF6, 0x00, 0x00, 0x40); // APPLICATION SELECTION

delay_ms(200);

dsp_read_long(0x07, 0xF7); // APPLICATION RUNNING

if (read_l != 0x40) flag = 4;

dsp_write_long(0x07, 0xF1, 0x00, 0x00, 0x09); // MAIN IO CONTROL (put last)

delay_ms(200);

dsp_read_long(0x07,0xF1);

if (read_l != 0x08) flag = 5;

codec_write_verify(0x00, 0x00, 0x22, 0x06); // AUDIO CODEC CONFIG

codec_write_verify(0x00, 0x08, 0x00, 0x00); // INPUT SELECT MODE

codec_write_verify(0x00, 0x11, 0x00, 0x00); // BALANCE

return flag;

}

// SUBROUTINE: CONFIGURE TO DECODER

char mas_config_decoder(void){

DDRA = 0xFF; // Set Port A to OUT

control_write_verify(0x6A, 0x8C, 0x00);

delay_ms(20);

dsp_write_verify(0x07, 0xF6, 0x00, 0x00, 0x0C); // APPLICATION SELECTION

delay_ms(200);

dsp_read_long(0x07, 0xF7); // APPLICATION RUNNING

if (read_l != 0x0C) flag = 4;

dsp_write_long(0x07, 0xF1, 0x00, 0x00, 0x11); // MAIN IO CONTROL (put last)

delay_ms(200);

dsp_read_long(0x07,0xF1);

if (read_l != 0x10) flag = 5;

codec_write_verify(0x00, 0x00, 0x22, 0x07); // AUDIO CODEC CONFIG

codec_write_verify(0x00, 0x06, 0x00, 0x00); // MIX ADC SCALE (0x40 = 100%)

codec_write_verify(0x00, 0x07, 0x40, 0x00); // MIX DSP SCALE (0x40 = 100%)

codec_write_verify(0x00, 0x08, 0x00, 0x00); // INPUT SELECT MODE

codec_write_verify(0x00, 0x0E, 0x00, 0x00); // D/A CONVERTER OUTPUT

codec_write_verify(0x00, 0x10, 0x7F, 0x00); // VOLUME CONTROL (Ox73 = 0 dB)

codec_write_verify(0x00, 0x11, 0x00, 0x00); // BALANCE (Ox73 = 0 dB)

return flag;

}

// SUBROUTINE: UART

void send_to_UART(){

while(!EOD); //wait till EOD goes high

while(!uflag) {

PR = 1; //signal we're ready

while(RTW); //wait till RTR drops low

UDR = ENCODE; //put data out to UART

while(!UCSRA.5) //wait till UART can receive another byte

if (!EOD) uflag = 1;

PR = 0;

while(!RTW) //wait till RTW goes high

if (!EOD) uflag = 1;

}

uflag = 0;

}

// I2C SUBROUTINES

void dsp_write_long(char addr_h, char addr_l, char data_h, char data_m, char data_l){

my_start();

my_write(0x3C); //device write address

my_write(0x68); //dsp sub_addr

my_write(0xE0);

my_write(0x00);

my_write(0x00);

my_write(0x01);

my_write(addr_h);

my_write(addr_l);

my_write(0x00);

my_write(data_h);

my_write(data_m);

my_write(data_l);

my_stop();

}

void dsp_read_long(char addr_h, char addr_l){

my_start();

my_write(0x3C); //device write address

my_write(0x68); //dsp sub_addr

my_write(0xC0);

my_write(0x00);

my_write(0x00);

my_write(0x01);

my_write(addr_h);

my_write(addr_l);

my_stop();

my_start(); //read value

my_write(0x3C);

my_write(0x69); //dsp data_read

my_start();

my_write(0x3D);

read_h = my_read(1);

read_h = my_read(1);

read_m = my_read(1);

read_l = my_read(0);

my_stop();

read_h = read_h & 0x0F;

}

void codec_read(char addr_h, char addr_l){

my_start();

my_write(0x3C); //device write address

my_write(0x6C); //codec sub_addr

my_write(addr_h);

my_write(addr_l);

my_stop();

my_start(); //read value

my_write(0x3C);

my_write(0x6D); //codec data_read

my_start();

my_write(0x3D);

read_h = my_read(1);

read_l = my_read(0);

my_stop();

}

void control_read(){

my_start();

my_write(0x3C); //device write address

my_write(0x6A); //control sub_addr

my_start(); //read value

my_write(0x3D);

read_h = my_read(1);

read_l = my_read(0);

my_stop();

}

void control_write(char sub_addr, char data_h, char data_l){

my_start();

my_write(0x3C); //device write address

my_write(sub_addr); //control sub_addr

my_write(data_h);

my_write(data_l);

my_stop();

}

void codec_write(char addr_h, char addr_l, char data_h, char data_l){

my_start();

my_write(0x3C); //device write address

my_write(0x6C); //codec write

my_write(addr_h);

my_write(addr_l);

my_write(data_h);

my_write(data_l);

my_stop();

}

void toU(char first) {

UDR = first;

while (!UCSRA.5);

}

// SUBROUTINES: WRITE AND VERIFY

void control_write_verify(char sub_addr, char data_h, char data_l) {

control_write(sub_addr, data_h, data_l);

delay_ms(100);

control_read();

if(read_h != data_h || read_l != data_l) {

toU(sub_addr);

flag = 1;

}

}

void dsp_write_verify(char addr_h, char addr_l, char data_h, char data_m, char data_l){

dsp_write_long(addr_h, addr_l, data_h, data_m, data_l);

delay_ms(100);

dsp_read_long(addr_h, addr_l);

if(read_h != data_h || read_m != data_m || read_l!= data_l){

toU(addr_l);

flag = 2;

}

}

void codec_write_verify(char addr_h, char addr_l, char data_h, char data_l){

codec_write(addr_h, addr_l, data_h, data_l); //enable A/D

delay_ms(100);

codec_read(addr_h, addr_l);

if(read_h != data_h || read_l != data_l){

toU(addr_l);

flag=3;

}

}

Appendix D: Software: I2C

#define SDA DDRB.0

#define SCL DDRB.1

#define SDA_PIN PINB.0

#define SCL_PIN PINB.1

#define LOW 1

#define HIGH 0

void delay(char type){ //5us if pulse, 2.5 us is half pulse

#asm("push r22")

while(type-- > 0){ //do twice for full pulse

#asm

ldi r22, 7

delayl:

dec r22

brne delayl

#endasm

}

#asm("pop r22")

}

char my_read(char ack){ //SDA == == =

unsigned char data; //release data line

char i = 0;

SDA = HIGH; //SCL /--\_

while(i++ < 8){

delay(1);

data = data ................
................

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