SWARNANDHRA



COURSE OUTCOMES: Students are able to:

CO1. Describe about fundamental VERILOG HDL Programming basics and different tools used in developing HDL Programs.

CO2. Summarize different VERILOG Programming models and different applications.

CO3. Design and develop any digital circuit using both concurrent and Sequential Programming concepts.

CO4. Explain about various Testing techniques used in testing digital circuits.

|Unit No | Outcome |Topics/Activity |Ref. Text book|Total | |

| | | | |Periods |Delivery Method |

| | |UNIT I: INTRODUCTION AND HISTORY OF VERILOG HDL | | |

| |CO1: Describe about fundamental | | | |

| |VERILOG HDL Programming basics and | | | |

|1 |different tools used in developing | | | |

| |HDL Programs. | | | |

| | | | | |

| | | | | |

| | | | | |

| | |1.1 Design flow-Design Domain & Levels of Abstraction |T1, R1 |10 |Chalk & Talk, |

| | | | | |PPT, Active |

| | | | | |Learning |

| | | | | |& Tutorial |

| | |1.2 Levels of Design Description- Circuit Level, Gate level, Data Flow, |T1, R1 | | |

| | |Behavioral Level. | | | |

| | |1.3 Concurrency, Simulation and Synthesis |T1, R1 | | |

| | |1.4 Function Verification- Test bench Inputs, Modeling time delays. |T1, R1 | | |

| | |1.5 System Tasks, Programming Language Interface, Module, Simulation and |T1, R1 | | |

| | |Synthesis Tools – Use of Xilinx or ModelSim | | | |

| | |1.6 Different styles of coding in VERILOG- Keywords, Identifiers, |T1, R1 | | |

| | |Comments, Logic Values, Strengths, Data Types-Net, Variable type, Scalars| | | |

| | |and Vectors, Parameters, Operators, Exercise programs. | | | |

|2 |CO2: Summarize different VERILOG |UNIT II: GATE LEVEL MODELING | | 15 |Chalk & Talk, |

| |Programming models and different | | | |PPT, Active |

| |applications. | | | |Learning |

| | | | | |& Tutorial |

| | |2.1 AND Gate Primitive – truth table and program call, Module Structure &|T1, R1 | | |

| | |Other Gate Primitives | | | |

| | |2.2 Tristate Gates – ON, OFF, Control state buffer, Array of Instances of|T1, R1 | | |

| | |Primitives | | | |

| | |2.3 Flip-Flops- SR Latch, D Latch, Delay – Net Delay, Gate Delay, Tri |T1, R1 | | |

| | |State Gate Delay | | | |

| | |2.4 Strengths and Construction Resolution- Gate Contention, strengths, |T1, R1 | | |

| | |Net types and ports | | | |

| | |2.5 Net Types- wand wor,tri-tri0, tri1, Combining delays. |T1,R1 | | |

| | |2.6 Design of Basic Circuits- design of ALU using adder, encoder, |T1,R1 | | |

| | |decoder. | | | |

| | |Data Flow level modeling- Assign structure, Net Declaration, Delays and |T1,R1 | | |

| | |Continuous Assignment Structure. | | | |

| 3 |CO2: Summarize different VERILOG |UNIT III: BEHAVIORAL MODELING | | |Chalk & Talk, |

| |Programming models and different | | | |PPT, Active |

| |applications. | | | |Learning |

| | | | |12 |& Tutorial |

| | |3.1 Operations and Assignments-using reg, Functional Bi-furacation – |T1, R1 | | |

| | |Begin, End Block, Local Variables, | | | |

| | |3.2 Initial Construct – Mutiple Intial Block, Always Construct- Event |T1, R1 | | |

| | |Control. | | | |

| | |3.3 Assignments with Delays- delay, Zero Delay, Wait Construct. |T1, R1 | | |

| | |3.4 Multiple Always Block- sequential model, Design at Behavioral Level, |T1, R1 | | |

| | |Blocking and Non-Blocking Assignments | | | |

| | |3.5 Case Statement- CaseX, CaseZ Statements, Simulation Flow- Queue |T1, R1 | | |

| | |Concepts. 'If' an 'if-Else' Constructs- Assign De-assign-loop, repeat. | | | |

|CYCLE- I EXAMINATION |

|4 |CO3: Design and develop any digital|UNIT IV: SWITCH LEVEL MODELING | |13 |Chalk & Talk, |

| |circuit using both concurrent and | | | |PPT, Active |

| |Sequential Programming concepts | | | |Learning |

| | | | | |& Tutorial |

| | |4.1 Basic Transistor Switches – Basic Switch Primitives, Resistive |T1, T2, R1 | | |

| | |Switches, CMOS Switches | | | |

| | |4.2 CMOS Switches, Bi-Directional Gates- tran, rtarn, Bus Switching. |T1, T2, R1 | | |

| | |4.3 Time Delays with Switch Primitives, Instantiation with 'Strengths' | T1, T2, R1 | | |

| | |and 'Delays', Strength Contention with Tri-reg Nets | | | |

| | |4.4 System Tasks, Functions and Compiler Directives-Parameters, time |T1, T2, R1 | | |

| | |delay, Declaraion and assignments, , Path Delays, Module | | | |

| | |Parameters,System Tasks and Functions | | | |

| | |UNIT V: SEQUENTIAL CIRCUIT DESCRIPTION | |10 |Chalk & Talk, |

| | | | | |PPT, Active |

| | | | | |Learning |

| | | | | |& Tutorial |

|5 |CO3.Design and develop any digital |5.1 Sequential Models, Sequential Models, Feedback Model, Capacitive |T2 | | |

| |circuit using both concurrent and |Model, Implicit Model | | | |

| |Sequential Programming concepts.| | | | |

| | |5.2 Memory Components- gate level seqeuntail primitives, assignments, |T2 | | |

| | |memory elements, flip flop timing | | | |

| | |5.3 Mixed model programs – MOS Transistors |T2 | | |

| | |5.4 Functional Registers – shift register, counters, stack, queue. | | | |

| | |5.5 State Machine Coding- Moore, Mealy, Huffman coding, Sequential | | | |

| | |Synthesis, Mixed model programs. | | | |

| | |UNIT VI: INTRODUCTION TO COMPONENTS TEST AND VERIFICATION | | |

| | | |10 |Chalk & Talk, |

| | | | |PPT, Active |

| | | | |Learning |

| | | | |& Tutorial |

|6 |CO4: Explain different Transducers |6.1 Test Bench - Combinational Circuits Testing, Sequential Circuit | T2 | | |

| |and Bridges for the measurement of |Testing | | | |

| |different parameters like | | | | |

| |resistance, inductance, | | | | |

| |capacitance, force, temperature and| | | | |

| |frequency etc.. [K2] | | | | |

| | |6.2 Test Bench Techniques – Test data, simulation control, Limiting Data |T2 | | |

| | |Test, Synchronized display. | | | |

| | |6.3 Design Verification, Assertion Verification- open assertion |T2 | | |

| | |6.4 BIST and BILBO techniques |T2 | | |

| | | | | | |

| | | |Total |70 | |

| |

|CYCLE- II EXAMINATION |

|END EXAMINATIONS |

|Text Books: |

|S.No. |AUTHORS, BOOK TITLE, EDITION, PUBLISHER, YEAR OF PUBLICATION |

| |R. Padmanabhan, B Bala Tripura Sundari, Design Through Verilog HDL, Wiley 2009. |

| |ZainalabdienNavabi, Verliog Digital System Design,TMH, 2nd Edition,2012. |

|Reference Books: |

|S.No. |AUTHORS, BOOK TITLE, EDITION, PUBLISHER, YEAR OF PUBLICATION |

| |Samir Palnitkar, Verilog HDL - 2nd Edition, Pearson Education, 2009. |

| |Michel D. Ciletti, Advanced Digital Design with Verilog HDL - PHI,2009. |

| |Name |Signature with Date |

| |Faculty | Dr.N.K.Devi | |

| |Course Coordinator |Dr.N.K.Devi | |

| |Module Coordinator |Dr.Balamurugan | |

| |Programme Coordinator |Dr.B.S.Rao | |

PRINCIPAL

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