Overview - Intel



-748030-5651500-3954123347085MAX 10 Debugging with System ConsoleDE10-Lite Development Kit0MAX 10 Debugging with System ConsoleDE10-Lite Development KitDecember 2016Version 1.0Contents TOC \o "1-3" \h \z \u Overview PAGEREF _Toc474162854 \h 3Lab Notes PAGEREF _Toc474162855 \h 3Quartus Installation PAGEREF _Toc474162856 \h 3Design Flow PAGEREF _Toc474162857 \h 4System Console Usage Flow PAGEREF _Toc474162858 \h 6Introduction to the DE10-LITE Development Kit PAGEREF _Toc474162859 \h 7HARDWARE DESIGN PAGEREF _Toc474162860 \h 8Objective of Section: PAGEREF _Toc474162861 \h 8Initial Setup PAGEREF _Toc474162862 \h 8Get started with Quartus PAGEREF _Toc474162863 \h 10Building your Qsys based processor system PAGEREF _Toc474162864 \h 13Building the top level design PAGEREF _Toc474162865 \h 27Adding the Qsys system into your design PAGEREF _Toc474162866 \h 31SYSTEM CONSOLE DESIGN PAGEREF _Toc474162867 \h 34Creating the System Console design PAGEREF _Toc474162868 \h 34Launching System Console PAGEREF _Toc474162869 \h 34Running Tcl Scripts on System Console PAGEREF _Toc474162870 \h 35Lab Summary PAGEREF _Toc474162871 \h 38 OverviewThis lab tutorial teaches you how to use one of the Quartus System Debugging Tools: System Console to debug your hardware.It will show you how to install the DE10-Lite Development kit pin settings, design the processor-based hardware system with Qsys, download it to the DE10-LITE Development Kit, and run few tcl scripts on System Console to verify that your system is functional and demonstrate the use this System Debugging Tool. The lab is split into a Hardware Section and Software Section. You can skip the hardware section and move directly to the software section should you choose.Lab NotesMany of the names that the lab asks you to choose for files, components, and other objects in this exercise must be spelled exactly as directed. This is necessary for consistency and to ensure that each step works properly in the lab. When creating your own systems, you can choose your own names as long, as you use them consistently in your project. The directory paths shown in the figures are for Windows (backslash directory delimiters). If you are using Linux, the paths will be shown with forward slash directory delimiter. Quartus InstallationQuartus is Intel FPGA’s design tool suite. It serves a number of functions:Design creation through the use of HDL languages or schematicsSystem creation through the Qsys graphical interfaceGeneration and editing of constraints: timing, pin locations, physical location on die, IO voltage levelsSynthesis of high level language into an FPGA netlist (“mapping” in FPGA terminology)FPGA place and route (“fitting” in FPGA terminology)Generation of design image (used to program FPGA, “assembly” in FPGA terminology)Timing AnalysisProgramming/download of design image into FPGA hardwareDebugging by insertion of debug logic (in-chip logic analyzer)Interfaces to 3rd party tools such as simulatorsLaunching of Software Build Tools (Eclipse) for Nios II and System Debugging Tools such as System Console and External Memory Interface Toolkit.To download Quartus, follow these instructions:Visit this site: to download version 16.1.00 of Quartus II.Select version 16.1.00 and your PC’s operating system.For the smallest installation, and quickest download time, enter only the entries shown below.Figure SEQ Figure \* ARABIC 1: Quartus download pageFollow the download instructions provided from the web page. No license is required to run MAX 10 FPGAs on the Quartus software.Design FlowUnlike system development with hard processors, development with soft processors enables you to optimize the processor system to your application requirements and use the FPGA to add performance and the interfaces required by your system. This means that you need to know how to modify the processor system hardware; this may sound challenging, but thanks to the Qsys graphical system design tool, this is actually relatively easy, which we will demonstrate in this lab. With any Qsys systems, you can quickly create your own custom GUI to control and monitor your design running on Intel FPGAs. Figure 3 illustrates how an overall system is integrated using the combination of the Qsys system integration tool, Quartus for mapping (FPGA terminology for synthesis), fitting (FPGA terminology for place and route), and the NIOS Software Build Tool (SBT) for software development.Figure SEQ Figure \* ARABIC 2: Development FlowThe above diagram depicts the typical flow for Nios II system design. Hardware System definition is performed using Qsys; the resultant HDL files from the Qsys system are used by the Quartus II FPGA design software to map, fit and download the hardware image into the FPGA device. Quartus II also generates information that describes the configuration of the system designed in Qsys so that the Nios II SBT can be configured to create a software library that matches the hardware system and contains the correct peripheral drivers. However, in this lab, we will be using System Console instead of NIOS to test our hardware. As shown in REF _Ref471218629 \h Figure 3, system console interconnects with Qsys via several interfaces such as USB and the JTAG to Avalon Master Bridge:Figure SEQ Figure \* ARABIC 3: System Console InterfacesBefore we discuss its typical flow, let’s review the components required for system console to be used.System Console Usage FlowIn order to use System console for your design, you need:A system including one or several IPs – called a debug agent that System Console can connect to.A current install of the Quartus sofware toolThe .sof file for the project that includes the Qsys system.Figure SEQ Figure \* ARABIC 4: System Console Usage FlowSystem Console uses a virtual file system to organize the available services, which is similar to the /dev location on Linux systems. Instances of services are referred to by their unique service path in the file system. Most System Console service instances are automatically discovered when you start the System Console. After ensuring that your board is properly configured and that System Console is launched and ready for interactive usage, you start by finding the service. This is done using the “get_service_paths” command. After locating your service, it’s convenient to set a variable equal to it. This is what is done in step 3. Step 4 opens the service using the variable defined in the previous step. System console offers several service types including a master service and a dashboard. The master service type provides control of an Avalon master port; and thus allows reading or writing to any connected Avalon slave. As for the dashboard service, it allows one to create graphical tools that integrate into the System Console and use widgets such as buttons, dials, and charts. Step 5 illustrates the sorts of commands that can be used on this sort of service. Step 6 closes the device.Introduction to the DE10-LITE Development KitIntel PSG and its design partners create a number of development kits to allow users a quick and convenient starting point for designing with MAX10 devices. These kits include schematics and bill of materials if you want to use the DE10-LITE Development Kit for production or a derivative product based on the bill of materials. As seen on the diagram below, the DE10-LITE Dev Kit is a full featured kit with a variety of interfaces for a broad range of applications. The board includes hardware such as on-board USB Blaster, 3-axis accelerometer, video capabilities and much more. In this lab, we will not use many of the interfaces, but there is a wealth of design examples and reference material demonstrating how to use these interfaces. Figure SEQ Figure \* ARABIC 5: DE10-LITE Development Kit FeaturesHARDWARE DESIGN(If you want to skip the hardware design section, continue in the section called SOFTWARE DESIGN)Objective of Section:System console enables a system-level debug of Qsys systems through a tcl console. Debugging is possible over various available communication channels such as JTAG, TCP/IP or USB. One major and beneficial functionality of System Console is allowing users to read from or write to memory-mapped components. AnoOther of its usage examples include bug isolation, process automation, and custom debug tool visualization.This lab hardware is constructed with the following components: 2 on-chip memories, a JTAG to Avalon Master Bridge, a JTAG UART, a NIOS II Processor, switches and LEDs. Intel FPGAs utilize the Qsys network on chip interconnect to connect the master and slave devices together. Initial SetupIntel PSG (formerly Altera) provides a starting point design to get the FPGA device pinouts associated with the development kits layout and your design via what is called the Baseline design. Navigate to the Altera design store: on Design ExamplesFigure SEQ Figure \* ARABIC 6: Design StoreOnce in Design Examples:Filter by DE10-LITE Development KitFigure SEQ Figure \* ARABIC 7: Design Examples under Design Store (note: this list changes over time and might not look the same as this picture)Select the DE10-Lite Development Kit Baseline Design .Figure SEQ Figure \* ARABIC 8: DE10-LITE Development Baseline Design Example Select the Download button and save the baseline.par design locally to your lab working directory (call the directory system_console_proj). Get started with QuartusNow you are ready to get started designing hardware! Double-click the Quartus Icon to launch Quartus. Click on Help About Quartus and check if you are running Quartus v16.10.0Next you will launch the New Project Wizard from Quartus from the main panel or alternatively File New Project Wizard Figure SEQ Figure \* ARABIC 9: Quartus Main PanelFill in the New Project Wizard first panel with your system_console_proj directory and project named system_consoleFigure SEQ Figure \* ARABIC 10: New Project Wizard first panelClick next and select project template and click next.Figure SEQ Figure \* ARABIC 11: New project wizard second panelSelect the Baseline Pinout – MAX10 DE10-Lite Design. Then, click on Install the design templates, and navigate to where the DE10_LITE_Golden_Top.par file is located.Figure SEQ Figure \* ARABIC 12: Design Template InstallOnce you hit ok, Quartus loads this starting point design that contains the pinout for the MAX10 - DE10-LITE Development Kit. Note: only a handful of pins are needed for the lab, but you can rely on the settings utilized in the Baseline project to make sure the right pin locations and voltage settings are correct for your project.Building your Qsys based processor systemThe system you will be designing in the Qsys environment consists of a Nios II processor, a JTAG to Avalon Master, and 5 slave devices (the second on-chip memory is optional, one could use only one on-chip memory with enough memory size). Building the Qsys system is a highly efficient way of designing systems with or without a processor.Launch Qsys from Quartus: Tools Qsys. The initial screen looks something like this:Figure SEQ Figure \* ARABIC 13: Qsys main panelNext, we will add the various components of the system and make the connections between them. By default, Qsys inserts a clock module. We will connect to this later on in the lab. Below the IP catalog tab, you can search for the various components you want to add to your Qsys based system. Enter Nios in the IP catalog search tabSelect the Nios II Gen 2 processor from the libraryA configuration window will appearSelect the Nios II/e processor under the “select an implementation” option on the main tabThis version of the Nios II processor is resource optimized and will work well for this lab implementation. Figure SEQ Figure \* ARABIC 14: Nios II Gen 2 Configuration panelClick finish and you will see the Nios IIe processor in your connection diagram. For now, don’t worry about the system errors reported, we will address them soon.Figure SEQ Figure \* ARABIC 15: Qsys System Contents panelQsys has a very elegant and efficient way of making connections by clicking on the nodes on ‘wires’ in the connections panel on the 2nd column from the left. You can add the connections as you add components, but it’s often easier to make all the connections once you have finished adding the various blocks. With the Nios II processor added, you still need to add the On-Chip Memory, the (JTAG to AVALON) Master, SWITCH and LED to your system. Search for memory in the IP catalog. You will see many options for memory. It might be easiest to detach the IP Catalog from the main panel by clicking on the detach window iconFigure SEQ Figure \* ARABIC 16: Detach window iconFigure SEQ Figure \* ARABIC 17: IP catalog search for on chip memoryLocate the On-Chip Memory (RAM or ROM) component and click add You can use all of the default settings except that you need to change the memory size from 4096 to 32768. This will ensure that you have a plenty of space for your system.Uncheck initialize memory contentFigure SEQ Figure \* ARABIC 18: On chip memory configuration panelClick finish and you will now see a total 3 components in your Qsys system: clock, Nios II processor and on-chip memory. Add another On-chip RAM with memory size 16384. Again uncheck initialize memory contentThis is more for instruction purposes. If for some reason, you would like to use Eclipse II and may need separate additional memory space, this second on-chip will be the way to do it. Its connections to the rest of the Qsys system are similar to that of the first on-chip RAM except that the second on-chip slave will be just connected to the NIOS II processor data and instruction masters, and not to the JTAG to Avalon Master Bridge.Figure SEQ Figure \* ARABIC 19: System contents with NIOSII and on chip memoryThe next component you will add is the JTAG to Avalon Master Bridge: Search for “JTAG to Avalon” in the IP catalog, locate the memory and either double click or press add for this component. Keep the default settings and click finishFigure SEQ Figure \* ARABIC 20: JTAG to Avalon Master BridgeNext, you will add the JTAG UART: Search for JTAG in the IP catalog, locate the JTAG UART and double click or add that component. Keep the default settings and click finishFigure SEQ Figure \* ARABIC 21: JTAG UART configuration panelThe next two components SWITCH and LED are actually configured instances of general purpose parallel IO components in the IP catalog. Search for parallel IO (PIO) and select this block For the switch block, you will set this up as a 10-bit input interface using the settings shown belowFigure SEQ Figure \* ARABIC 22: Parallel IO configuration panel for SWITCH inputsNext, you will add a second PIO block, the LED:Double click on the PIO component as you did for the SWITCH. This time you will configure this component as the LED which is a 10-bit output.Figure SEQ Figure \* ARABIC 23: Parallel IO configuration panel for LED outputs Click finish. You have completed adding the 7 components that make up your Qsys system. Next you will rename the components in the design with names that are easy to remember:In the system contents tab, right click on the nios2_gen_2_0 component and select rename. Type in nios2eRename the rest of the components: my_onchip_memory (the one with the 32768-bytes memory size) onchip_memory2_0_0 (the other on-chip memory)my_jtag_masterjtag_uart_0_0switchledThis will make these components names easy to remember and reference in future steps.Figure SEQ Figure \* ARABIC 24: System Content connections starting panelThe next step consists of making the appropriate connections between the components within Qsys. Click on the clk net coming out of clk_0. When first selected, it will be gray color. Make connections by clicking on the small open circles on the lines that intersect with the 7 other components.You should see something similar to REF _Ref413419633 \h Figure 255.Figure SEQ Figure \* ARABIC 25: System contents after clock connectionPerform the same operation to connect the clk_reset to the resets on the other components.Next, connect the nios2e data master to the slaves.Make the connections between the Nios2e data master and:the s1 connection of both onchip memory unitsthe debug_mem_slave of the NIOS II processorthe avalon_jtag_slave on the jtag_uartthe s1 port on the switch and the s1 port on the led component As shown below:Figure SEQ Figure \* ARABIC 26: System contents after data master/slave connectionsThe instruction_master signal from the nios2e component does not need to be connected to each slave component as it only needs access to memory that contains the software executable. Make the connection between the nios2e instruction master and the s1 port for both: my_onchip_memorydebug_mem_slave (if it’s not already connected).Figure SEQ Figure \* ARABIC 27: System contents after instruction master/slave connectionsThe next connections to make are the processor interrupt request (IRQ) signals. The JTAG UART can drive interrupts and hence needs to be wired to the nios2e processor interrupt lines. Make JTAG UART to Nios2e IRQ connection as shown in 28. We will use the default setting for the IRQ number.Figure SEQ Figure \* ARABIC 28: System contents after interrupt connectionsNow, because we will use system console to debug the system using memory map of the led component:Connect the my_jtag_master master tothe s1 ports of ledthe s1 port of my_onchip_memory. You have now completed the internal connections for this Nios II processor based system. The next step is to make the external connections that connect the Qsys based system to the next higher level in the hierarchy of your FPGA design, or to FPGA device pins that connect to the PCB. Double click on the switch conduit, led conduit and my_jtag_master master_reset items under the export column circled in REF _Ref413422398 \h Figure 29. This will bring these ports out of the Qsys component to connect to the top-level design.Figure SEQ Figure \* ARABIC 29: System contents after exporting PIO switch and LEDNext you will need to generate the base Addresses for your Qsys system. This is achieved by using the command System Assign Base AddressesSave your Qsys system by using File Save As and pick a name for the Qsys system that you will remember. Note: that the lab figures call it my_qsys_system so to avoid confusion you should name your .qsys file the same. The information is saved in what is called a .qsys file. Although you are not entirely finished, it’s good practice to save edits along the way.You should see 2 major error messages in the Message Console of Qsys. They are shown in REF _Ref413422899 \h Figure 30.Figure SEQ Figure \* ARABIC 30: Error message prior to assign memory location to execute fromThese error messages have to do with the fact that nios2e processor doesn’t know where the software code that handles resets and exceptions is located. This is fairly straightforward to fix. Double click on the nios2e componentSet the reset vector memory and exception vector memory both to my_onchip_memory2_0.s1 This will set the system to execute from my_onchip_memory.s12_0 at these respective locations upon reset or interrupt. The 2 errors that were shown in REF _Ref413422899 \h Figure 30 should now be resolved.Figure SEQ Figure \* ARABIC 31: Assign vectors in the NIOS2E panel The final system should look similar to REF _Ref471219753 \h Figure 32.Figure SEQ Figure \* ARABIC 32: Final Qsys SystemSave your design once again. Note that by saving, you still have not generated the files that you need for Quartus II compilation and System Console. The step to complete this is to click on the button on the lower right of Qsys.Click on the button ‘Generate HDL’. Navigate to the project directory in the path section under Output Directory and click Generate on the panel that appears. Congratulations, this completes the Qsys section of the lab!!Figure SEQ Figure \* ARABIC 33: Generating the Qsys system HDL filesBuilding the top level designThe next step will take a little bit of knowledge in Verilog. If you are familiar with VHDL, you can make the same connections in VHDL, but you will have to change the design to VHDL on your own. For ease of following along the lab document, we recommend continuing the lab in Verilog. During the early steps using the project wizard, you loaded the baseline design, and have a baseline.v preloaded in the Quartus project. We will take a look at this starting point baseline.v file and strip out the unnecessary signals, while only leaving the signals that are needed to run the system console design. Quartus should be open, bring it up on screen Make sure the hierarchy tab is highlighted and double click the baseline designFor this design there is a clock, reset, switch inputs, LED outputs, a JTAG to Avalon Master Bridge and a JTAG UART. The JTAG UART pins are hard wired into the FPGA so you don’t need to add them in your Verilog source file. The 4 pins: TCLK, TDI, TMS and TDO that constitute a 4 wire JTAG interface are at a fixed location in your FPGA and they don’t need to be added to your Verilog source file. Only pins that are synthesized from your RTL source code need to be specified. The baseline.v design includes all non-hardwired device pins and you will need to delete extra pins and include the following pins in the port list: MAX10_CLK1_50, SW, LEDR, my_jtag_master_master_reset_reset Delete all other pins from the port list 00Part of the original baseline.v is shown in REF _Ref413659872 \h Figure 34.Make the changes including changing the module from baseline to top and save the file as top.vFigure SEQ Figure \* ARABIC 34: Original baseline.v designFigure SEQ Figure \* ARABIC 35: Edited baseline design with pins removed. Note save as: top.vNext we need to check that the top.v file is included in your project. Note that it should be the only file in your project so far. Go to Project Add/Remove Files. Confirm that top.v is listedFigure SEQ Figure \* ARABIC 36: Add/Remove Files paneNext you need to make the top level entity top since its currently set at baseline. In the same window upper left corner, click on General. Change baseline to top. You can also change by right clicking on the top.v and set as top level entityFigure SEQ Figure \* ARABIC : Settings paneClick OK when complete. Now, it is a good idea to make sure your Verilog is syntax correct.Return to the main Quartus window and select the Tasks pane. Double-Click on the Play (right triangle) in the tool bar for analysis/synthesis.You will get warnings, but you should get no errors. If you do get an error, it’s likely syntax (eg missing semicolon). Make changes, save, and continue to run analysis/synthesis until the Verilog runs error/free (ignore dangling pin warning for now). Figure SEQ Figure \* ARABIC 37: Task pane (successful compilation highlighted in red)The baseline design that you uploaded in the prior steps contain all of the pin settings needed so that the pin locations are consistent with how the MAX10 device is connected to the PCB on the DE10-LITE Dev Kit. You can inspect the pin setting locations to understand where they come from. Launch Assignments Assignment Editor. You will see a list of pins in spreadsheet form that contain pin (package ball to be specific) locations, IO standard and current strength settings. Note: you are not using all the pins in the design, but this is ok – Quartus will ignore pin assignments that are not referenced in your design. Figure SEQ Figure \* ARABIC 38: Assignment EditorAdding the Qsys system into your designNow that you have the top entity completed and syntactically correct, you will need to add the Qsys system into your design. Qsys makes this task quite convenient. Go to File Open and navigate to the name of the Qsys project you created (the one shown in the lab is called my_qsys_system.qsys).You should see a file called my_qsys_system _inst.v . Open this file and you see how to instantiate (fancy word meaning placing this component in your design) the Qsys system. The contents of this file is shown in REF _Ref471219966 \h Figure 39 : Figure SEQ Figure \* ARABIC 39: Verilog File to be instantiatedYou will need to connect the IO ports to the my_qsys_system. Copy the entire contents of the my_qsys_system file by highlighting and copy (ctrl-c), followed by inserting into the Verilog file top.v and pasting (ctrl-v). Next we will connect the switches to the LEDs in the system console tool. The LEDs [9:0] will be connected here (non-inverted) in software by connection to the Qsys system. Note that the LEDR is defined as 10 bits wide. If you get any dangling wire warning messages when you compile, this is ok. Click the save icon or File Save.Figure SEQ Figure \* ARABIC 40: top.v after integrating Qsys into designYou now have completed the creation of your system using Qsys, instantiating this component into the top level design, and making connections from led to switches for testing in your Verilog file called top.v. You now add the system into your project using the Project Add/Remove Files in Project command. Instead of adding individual Qsys generated Verilog files and settings into the project, you add the qip file which is located under either: my_qsys_system/synthesis/my_qsys_system.qip/synthesis/my_qsys_system.qip The qip file contains pointers to the location of all the generated source files generated from Qsys and necessary settings required to compile. You can open this file in a text editor to see its content. Navigate using the button and select the file. Hit Add followed by OK.Figure SEQ Figure \* ARABIC 41: Add/Remove Files from Project - .qip fileNow you can compile your design which will run analysis & synthesis, fitter (place and route in FPGA terminology), Assembler (generate programming image) and TimeQuest (the static timing analyzer). This can be achieved by clicking on the play button as shown in REF _Ref413699973 \h \* MERGEFORMAT Figure 42. Figure SEQ Figure \* ARABIC 42: Compilation buttonNote that some warnings and information messages come up in the bottom window. You can filter by message level. The errors are filtered with the button, critical warnings with the button, warnings with the button and informational messages with the button. You cannot proceed if you have errors. In this case there are only critical and standard warnings, primarily because we did not add timing constraints to this project. Due to the simplicity of this design and low frequency, it’s okay to start without timing constraints. Consult other Altera online training courses for instructions on how to add timing constraints to your design.Figure SEQ Figure \* ARABIC 43: Filter for critical warningsCongratulations, your FPGA hardware design is now complete.SYSTEM CONSOLE DESIGNCreating the System Console designFor the simplest example, ‘read/write off/to memory address’, we will utilize the system console usage flow to turn LEDs on and off by writing inputs to the Qsys generated LED base address. This requires a working processor to execute the code, on-chip memory to store the inputs, and an Avalon master to interface between the LED register and the hardware. To make the lab a little bit more interesting and hardware-centric, in the project zip file, you will find 3 other tcl script codes which make use of different tcl commands, as well as different system console functions. Should you choose to start directly in the Software Design section and skip the Hardware Design section, consult with your lab facilitator to get this file: top.sof as if you generated it from the Hardware Design lab. You will be able to complete all subsequent steps with this one file.Launching System ConsoleSystem Debugging Tools are included as part of Quartus. Before launching the console, make sure that you ‘ve programmed the MAX10 De10-Lite Kit successfully. System console can be launched via three ways:From Quartus tools menuFrom qsys tools menuFrom Nios II or embedded command shell with <system-console>Figure SEQ Figure \* ARABIC 44: Launching System ConsoleFigure SEQ Figure \* ARABIC 45:Launching System ConsoleUpon launching system console, you will be presented to a display like the one shown in Figure 46. The System Console GUI is divided in 4 main pieces:System Explorer — Allows you to view a hierarchy of the System Console virtual file system in your design, which may include connections, designs, design instances, and scripts. When you write scripts and specify the path where they are located in the environment settings of your operating system, you can then run the scripts from the System Explorer. Note:?For example, to view Tcl scripts in the System Explorer you can place the scripts in $Home directory path/system_console/scripts.Tools — Allows you to launch tools that use the System Console framework.Tcl Console—Allows you to run commands and Tcl scripts from within the System Console.Messages—Displays messages generated when running tools within the System Console.Running Tcl Scripts on System ConsoleUnder File, click on Load Design and navigate to the directory in which the .sof file residesOnce the design is loaded, you will receive few initialization messages. Under the System Explorer, check that top.sof is shown when you click on designsRight above design, are the located devices under the devices folder Verify that you are seeing the 10M50DA. Right click 10M50DA and scroll over Link Device, make sure that top.sof (below Auto) is checked. Do the same for Program deviceYou may need to click system_console.sof under “Program device” before clicking the system_console.sof under “Link Device to”Then, click on Execute Script on the menu under FileA message will pop up asking you to create a user script folder, don’t click create Instead, navigate to where the example tcl scripts are saved in (tcl scripts folder)Open the master_write_and_read.tcl script with Notepad (++)Let’s go briefly over what each line of this code does. Figure SEQ Figure \* ARABIC 46: TCL Script – master_write_and_read.tclAs mentioned earlier in the usage flow, after successful launch of system console, the next step is to locate and claim service path. This is exactly what it is done in lines 3 and 5.<Get_service_paths> master looks through your system and identifies all the master services available. Typing this command in the Tcl console window will return a list of the location paths for all the masters present in your hardware design.Line 5 retrieves one particular master service, which in this lab is the jtag_master. The Tcl command <lindex> refers to an element from a list, in this case, the 0th (first) in the master service instances identified by the command <get_service_paths master >. Claiming a specific service is optional; however, it enables a finer control over a specific address space of a service type, should you choose to do so, with the tcl command <claim_service>.Once you have located and claimed the service path you want to work with, then you can begin performing the desired operation with the given service. But first, you need to open that service, which is accomplished in line 7. Notice that the service path has been given a variable name called my_master, through the use of the Tcl command <set>. You can verify this by typing in the Tcl console: puts $my_master. Line 9 command master_write_32 writes the hex number 0xdeadbeef (in 32-bit writes) starting with the least significant bit (until the base address for the specific component is full) onto the memory address 0x00008000, which is that of the LEDs (you can check that by locating the base address of the LEDs in Qsys). In order to read what you have written on the console, you will need to set that master read (the 1 after the address signifies a 1 byte read) operation to a variable. This is done in line 11 with the variable name data which you associate to the Tcl command <master_read_32>. <Puts> write to the tcl console whatever data holds along with the text entry denoted with quotation marks “Data at address 0x00008000: ” beforehand.To exit the tcl script and open other tcl scripts (to perform different operations), it’s recommended that you close the current service type with the command line <close_service master $variable name > (see line 14 commented out).Before you either uncomment that line (or write it out on the tcl console) and run the script, notice that the input value written to the LEDs base address is arbitrary. Run the script and write to the console any value on the led memory address (with command master_write_32 ) and notice the LEDs lighting up accordingly.Should you want to try the other tcl scripts including a data entry box, a led shifting tool, and a led pio, make sure to close the service before running the next script.See attached pictures of what these additional scripts accomplish.Figure SEQ Figure \* ARABIC 47: Data entry boxThe Tcl script for the data entry box creates a dashboard (text box here) in which any data the user inputs, also shows up in the TCL Console.Figure SEQ Figure \* ARABIC 48: LED shifting – read Tcl script descriptionThis TCL script writes to the LED pio which is defined at a specific base address in the Qsys system, and sequentially turns off led 1 at a time starting with the far left one.Figure SEQ Figure \* ARABIC 49: LedPIOThe LedPio script monitors the live state of the physical LED PIO bits in the Qsys design and displays them on LED widgets in the console, and provides a “toggle” button along with each LED to allow the user to toggle the state of the LED.Lab SummaryYou now have completed the hardware and software sections of this lab. This includes:Loading the Device Kit pin settings into QuartusUsing Qsys to build a Nios II based systemInstantiating the Qsys component into your top level designAdd some connections between switches and LEDsCompiling your hardwareLoading your project design into System ConsoleCreating a system console projectModifying a Tcl script to perform some simple IO functionsRunning ScriptsTesting the hardwareThere is a wealth of resources from Intel PSG and partners to take classes on Tcl Script Language, Embedded Hardware, and reference design starting points to advance your skills using System Debugging Tools such as System Console. ................
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