Verilog 2 - Design Examples
Verilog 2 - Design Examples
Courtesy of Arvind
L03-1
Verilog can be used at several levels
High-Level Behavioral
A common approach is to use C/C++ for initial behavioral modeling, and for building test rigs
Register Transfer Level Gate Level
automatic tools to synthesize a low-level gate-level model
Courtesy of Arvind
L03-2
Writing synthesizable Verilog:
Combinational logic
! Use continuous assignments (assign)
assign C_in = B_out + 1;
! Use always@(*) blocks with blocking
assignments (=)
always @(*) begin out = 2'd0; if (in1 == 1)
always blocks allow more expressive control structures, though not
all will synthesize
out = 2'd1; else if (in2 == 1)
default
out = 2'd2;
end
! Every variable should have a default value to
avoid inadvertent introduction of latches
! Do not assign the same variable from more
than one always block ? ill defined semantics
Courtesy of Arvind
L03-3
Writing synthesizable Verilog:
Sequential logic
! Use always @(posedge clk) and non-
blocking assignments ( ................
................
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